Use meaningful class names

diff --git a/milkymist/clkfx/__init__.py b/milkymist/clkfx/__init__.py
index 2e65f089a76aced9568e626bb72662f37be77927..e90183ebe6c63bccdaa3ec9c2084d7419283153b 100644 (file)
--- a/milkymist/clkfx/__init__.py
+++ b/milkymist/clkfx/__init__.py
@@ -2,7 +2,7 @@ from fractions import Fraction
 
 from migen.fhdl.structure import *
 
-class Inst:
+class ClkFX:
        def __init__(self, infreq, outfreq):
                self.clkin = Signal()
                self.clkout = Signal()

diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py
index 26b47947ef2fb8543aec8f475a0cc74db5538ebb..3245954195656eaba40b063c8c66446943324ac4 100644 (file)
--- a/milkymist/lm32/__init__.py
+++ b/milkymist/lm32/__init__.py
@@ -1,7 +1,7 @@
 from migen.fhdl.structure import *
 from migen.bus import wishbone
 
-class Inst:
+class LM32:
        def __init__(self):
                self.ibus = i = wishbone.Master("lm32i")
                self.dbus = d = wishbone.Master("lm32d")

diff --git a/milkymist/m1reset/__init__.py b/milkymist/m1reset/__init__.py
index 71612538e7c2dae9a59c59254c2f0de697a1502c..64b973b99653a5b00f53233147a65f88faed158b 100644 (file)
--- a/milkymist/m1reset/__init__.py
+++ b/milkymist/m1reset/__init__.py
@@ -1,6 +1,6 @@
 from migen.fhdl.structure import *
 
-class Inst:
+class M1Reset:
        def __init__(self):
                self.trigger_reset = Signal()
                self.sys_rst = Signal()

diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py
index ccb2c1f10e64d8e9e52f054ab585d137fdc9b8db..0ee19ec27894f7d3a08855d8578fbe628f2a3232 100644 (file)
--- a/milkymist/norflash/__init__.py
+++ b/milkymist/norflash/__init__.py
@@ -2,7 +2,7 @@ from migen.fhdl.structure import *
 from migen.bus import wishbone
 from migen.corelogic import timeline
 
-class Inst:
+class NorFlash:
        def __init__(self, adr_width, rd_timing):
                self.bus = wishbone.Slave("norflash")
                self.adr = Signal(BV(adr_width-1))
@@ -10,7 +10,7 @@ class Inst:
                self.oe_n = Signal()
                self.we_n = Signal()
                self.ce_n = Signal()
-               self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
+               self.timeline = timeline.Timeline(self.bus.cyc_i & self.bus.stb_i,
                        [(0, [self.adr.eq(Cat(0, self.bus.adr_i[:adr_width-2]))]),
                        (rd_timing, [
                                self.bus.dat_o[16:].eq(self.d),

diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py
index 2e83cbe14d9d0ab50c84efd1c8d57ae595478d94..42f763ca259b8a83757185a33013bd8a2422d8c0 100644 (file)
--- a/milkymist/uart/__init__.py
+++ b/milkymist/uart/__init__.py
@@ -2,7 +2,7 @@ from migen.fhdl.structure import *
 from migen.bank.description import *
 from migen.bank import csrgen
 
-class Inst:
+class UART:
        def __init__(self, address, clk_freq, baud=115200):
                self._rxtx = rxtx = Register("rxtx", BV(8))
                divisor = Register("divisor")

diff --git a/top.py b/top.py
index d865a3c50a8d134d4ac85e96d24d95cc0a78c6ee..a2097b81fdcb75b4e3ceade963343b3748130332 100644 (file)
--- a/top.py
+++ b/top.py
@@ -9,18 +9,18 @@ def get():
        MHz = 1000000
        clk_freq = 80*MHz
        
-       clkfx_sys = clkfx.Inst(50*MHz, clk_freq)
-       reset0 = m1reset.Inst()
+       clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
+       reset0 = m1reset.M1Reset()
        
-       cpu0 = lm32.Inst()
-       norflash0 = norflash.Inst(25, 12)
-       wishbone2csr0 = wishbone2csr.Inst()
+       cpu0 = lm32.LM32()
+       norflash0 = norflash.NorFlash(25, 12)
+       wishbone2csr0 = wishbone2csr.WB2CSR()
        wishbonecon0 = wishbone.InterconnectShared(
                [cpu0.ibus, cpu0.dbus],
                [(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
                register=True,
                offset=1)
-       uart0 = uart.Inst(0, clk_freq, baud=115200)
+       uart0 = uart.UART(0, clk_freq, baud=115200)
        csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
        
        frag = autofragment.from_local()