litedram: Add simulation support

This adds a simulated litedram model along with the necessary
Makefile gunk to verilate it and wrap it for use by ghdl.

The core_dram_tb test bench is a variant of core_tb with
LiteDRAM simulated. It's not built by default, an explicit

make core_dram_tb

is necessary as to not require verilator to be installed for
the normal build process (also it's slow'ish).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/Makefile b/Makefile
index bf1e7616efb0fd9091a0da6021155008f882f3b0..ea7181c7c95d09db6e0c79eaff50a829b759861a 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
 GHDL ?= ghdl
 GHDLFLAGS=--std=08 --work=unisim
-CFLAGS=-O2 -Wall
+CFLAGS=-O3 -Wall
 
 GHDLSYNTH ?= ghdl.so
 YOSYS     ?= yosys
@@ -66,6 +66,7 @@ soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
 
 core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
 soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
+soc_dram_tbs = core_dram_tb
 
 $(soc_tbs): %: $(core_files) $(soc_files) $(soc_sim_files) $(soc_sim_obj_files) %.vhdl
        $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(core_files) $(soc_files) $(soc_sim_files) $@.vhdl -e $@
@@ -76,6 +77,34 @@ $(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
 soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
        $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
 
+# LiteDRAM sim
+VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null)
+ifeq (, $(VERILATOR_ROOT))
+$(soc_dram_tbs):
+       $(error "Verilator is required to make this target !")
+else
+
+VERILATOR_CFLAGS=-O3
+VERILATOR_FLAGS=-O3
+verilated_dram: litedram/generated/sim/litedram_core.v
+       verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
+       make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
+
+SIM_DRAM_CFLAGS  = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
+SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -faligned-new
+sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
+       $(CC)  $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
+
+soc_dram_files = $(soc_files) litedram/extras/wrapper-mw-init.vhdl litedram/generated/sim/litedram-initmem.vhdl
+soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
+soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
+dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
+soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files)
+
+$(soc_dram_tbs): %: $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) %.vhdl
+       $(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $@.vhdl -e $@
+endif
+
 # Hello world
 MEMORY_SIZE=8192
 RAM_INIT_FILE=hello_world/hello_world.hex
@@ -167,6 +196,7 @@ _clean:
        rm -f *.o work-*cf unisim-*cf $(all)
        rm -f fpga/*.o fpga/work-*cf
        rm -f sim-unisim/*.o sim-unisim/unisim-*cf
+       rm -f litedram/extras/*.o
        rm -f TAGS
        rm -f scripts/mw_debug/*.o
        rm -f scripts/mw_debug/mw_debug

diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl
new file mode 100644 (file)
index 0000000..835c1e2
--- /dev/null
+++ b/core_dram_tb.vhdl
@@ -0,0 +1,114 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.common.all;
+use work.wishbone_types.all;
+
+entity core_dram_tb is
+end core_dram_tb;
+
+architecture behave of core_dram_tb is
+       signal clk, rst: std_logic;
+        signal system_clk, soc_rst : std_ulogic;
+
+       -- testbench signals
+       constant clk_period : time := 10 ns;
+
+        -- Sim DRAM
+       signal wb_dram_in : wishbone_master_out;
+       signal wb_dram_out : wishbone_slave_out;
+       signal wb_dram_ctrl_in : wb_io_master_out;
+       signal wb_dram_ctrl_out : wb_io_slave_out;
+        signal wb_dram_is_csr   : std_ulogic;
+        signal wb_dram_is_init  : std_ulogic;
+        signal core_alt_reset : std_ulogic;
+begin
+
+    soc0: entity work.soc
+       generic map(
+           SIM => true,
+           MEMORY_SIZE => (384*1024),
+           RAM_INIT_FILE => "main_ram.bin",
+           RESET_LOW => false,
+            HAS_DRAM => true,
+           DRAM_SIZE => 256 * 1024 * 1024,
+           CLK_FREQ => 100000000
+           )
+       port map(
+           rst => soc_rst,
+           system_clk => system_clk,
+           uart0_rxd => '0',
+           uart0_txd => open,
+           wb_dram_in => wb_dram_in,
+           wb_dram_out => wb_dram_out,
+           wb_dram_ctrl_in => wb_dram_ctrl_in,
+           wb_dram_ctrl_out => wb_dram_ctrl_out,
+            wb_dram_is_csr => wb_dram_is_csr,
+            wb_dram_is_init => wb_dram_is_init,
+           alt_reset => core_alt_reset
+           );
+
+       dram: entity work.litedram_wrapper
+           generic map(
+               DRAM_ABITS => 24,
+               DRAM_ALINES => 1
+               )
+           port map(
+               clk_in          => clk,
+               rst             => rst,
+               system_clk      => system_clk,
+               system_reset    => soc_rst,
+               core_alt_reset  => core_alt_reset,
+               pll_locked      => open,
+
+               wb_in           => wb_dram_in,
+               wb_out          => wb_dram_out,
+               wb_ctrl_in      => wb_dram_ctrl_in,
+               wb_ctrl_out     => wb_dram_ctrl_out,
+               wb_ctrl_is_csr  => wb_dram_is_csr,
+               wb_ctrl_is_init => wb_dram_is_init,
+
+               serial_tx       => open,
+               serial_rx       => '1',
+
+               init_done       => open,
+               init_error      => open,
+
+               ddram_a         => open,
+               ddram_ba        => open,
+               ddram_ras_n     => open,
+               ddram_cas_n     => open,
+               ddram_we_n      => open,
+               ddram_cs_n      => open,
+               ddram_dm        => open,
+               ddram_dq        => open,
+               ddram_dqs_p     => open,
+               ddram_dqs_n     => open,
+               ddram_clk_p     => open,
+               ddram_clk_n     => open,
+               ddram_cke       => open,
+               ddram_odt       => open,
+               ddram_reset_n   => open
+               );
+
+    clk_process: process
+    begin
+       clk <= '0';
+       wait for clk_period/2;
+       clk <= '1';
+       wait for clk_period/2;
+    end process;
+
+    rst_process: process
+    begin
+       rst <= '1';
+       wait for 10*clk_period;
+       rst <= '0';
+       wait;
+    end process;
+
+    jtag: entity work.sim_jtag;
+
+end;

diff --git a/litedram/extras/fusesoc-add-files.py b/litedram/extras/fusesoc-add-files.py
index b646bea4b2b2cb1a5cbc2fd656cdb164aca5e70e..efc2233e594faa280911cee1226b18a1a2a4b05c 100644 (file)
--- a/litedram/extras/fusesoc-add-files.py
+++ b/litedram/extras/fusesoc-add-files.py
@@ -21,14 +21,14 @@ class LiteDRAMGenerator(Generator):
         if os.path.exists(cpu_file):
             cpu = pathlib.Path(cpu_file).read_text()
         else:
-            cpu = None
+            cpu = "none"
+
+        print("CPU is ", cpu)
 
         # Add files to fusesoc
         files = []
         f = os.path.join(gen_dir, "litedram_core.v")
         files.append({f : {'file_type' : 'verilogSource'}})
-        f = os.path.join(gen_dir, "litedram-wrapper.vhdl")
-        files.append({f : {'file_type' : 'vhdlSource-2008'}})
         f = os.path.join(gen_dir, "litedram-initmem.vhdl")
         files.append({f : {'file_type' : 'vhdlSource-2008'}})
         f = os.path.join(gen_dir, "litedram_core.init")
@@ -36,8 +36,15 @@ class LiteDRAMGenerator(Generator):
 
         # Look for init CPU types and add corresponding files
         if cpu == "vexriscv":
-            f = os.path.join(base_dir, "extras", "VexRiscv.v")
+            print("Adding VexRiscv files and wrapper")
+            f = os.path.join(extras_dir, "VexRiscv.v")
             files.append({f : {'file_type' : 'verilogSource'}})
+            f = os.path.join(extras_dir, "wrapper-self-init.vhdl")
+            files.append({f : {'file_type' : 'vhdlSource-2008'}})
+        else:
+            print("Adding wrapper")
+            f = os.path.join(extras_dir, "wrapper-mw-init.vhdl")
+            files.append({f : {'file_type' : 'vhdlSource-2008'}})
 
         self.add_files(files)
 

diff --git a/litedram/extras/sim_dram_verilate.mk b/litedram/extras/sim_dram_verilate.mk
new file mode 100644 (file)
index 0000000..0d760d4
--- /dev/null
+++ b/litedram/extras/sim_dram_verilate.mk
@@ -0,0 +1,10 @@
+OPT_FAST=-O3 -fstrict-aliasing
+OPT_SLOW=-O3 -fstrict-aliasing
+
+top_all: top_all2
+
+include Vlitedram_core.mk
+
+top_all2: default $(VK_GLOBAL_OBJS)
+
+.PHONY: top_all top_all2

diff --git a/litedram/extras/sim_litedram.vhdl b/litedram/extras/sim_litedram.vhdl
new file mode 100644 (file)
index 0000000..0016240
--- /dev/null
+++ b/litedram/extras/sim_litedram.vhdl
@@ -0,0 +1,214 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package sim_litedram is
+    -- WB req format:
+    -- 73 .. 71 : cti(2..0)
+    -- 70 .. 69 : bte(1..0)
+    -- 68 .. 65 : sel(3..0)
+    -- 64       : we
+    -- 63       : stb
+    -- 62       : cyc
+    -- 61 .. 32 : addr(29..0)
+    -- 31 ..  0 : write_data(31..0)
+    --
+    procedure litedram_set_wb(req : in std_ulogic_vector(73 downto 0));
+    attribute foreign of litedram_set_wb : procedure is "VHPIDIRECT litedram_set_wb";
+
+    -- WB rsp format:
+    -- 35       : init_error;
+    -- 34       : init_done;
+    -- 33       : err
+    -- 32       : ack
+    -- 31 ..  0 : read_data(31..0)
+    --
+    procedure litedram_get_wb(rsp : out std_ulogic_vector(35 downto 0));
+    attribute foreign of litedram_get_wb : procedure is "VHPIDIRECT litedram_get_wb";
+
+    -- User req format:
+    -- 171        : cmd_valid
+    -- 170        : cmd_we
+    -- 169        : wdata_valid
+    -- 168        : rdata_ready
+    -- 167 .. 144 : cmd_addr(23..0)
+    -- 143 .. 128 : wdata_we(15..0)
+    -- 127 ..   0 : wdata_data(127..0)
+    --
+    procedure litedram_set_user(req: in std_ulogic_vector(171 downto 0));
+    attribute foreign of litedram_set_user : procedure is "VHPIDIRECT litedram_set_user";
+
+    -- User rsp format:
+    -- 130        : cmd_ready
+    -- 129        : wdata_ready
+    -- 128        : rdata_valid
+    -- 127 ..   0 : rdata_data(127..0)
+    
+    procedure litedram_get_user(req: in std_ulogic_vector(130 downto 0));
+    attribute foreign of litedram_get_user : procedure is "VHPIDIRECT litedram_get_user";
+    
+    procedure litedram_clock;
+    attribute foreign of litedram_clock : procedure is "VHPIDIRECT litedram_clock";
+
+    procedure litedram_init(trace: integer);
+    attribute foreign of litedram_init : procedure is "VHPIDIRECT litedram_init";
+end sim_litedram;
+
+package body sim_litedram is
+    procedure litedram_set_wb(req : in  std_ulogic_vector(73 downto 0)) is
+    begin
+        assert false report "VHPI" severity failure;
+    end procedure;
+    procedure litedram_get_wb(rsp : out std_ulogic_vector(35 downto 0)) is
+    begin
+        assert false report "VHPI" severity failure;
+    end procedure;
+    procedure litedram_set_user(req: in std_ulogic_vector(171 downto 0)) is
+    begin
+        assert false report "VHPI" severity failure;
+    end procedure;
+    procedure litedram_get_user(req: in std_ulogic_vector(130 downto 0)) is
+    begin
+        assert false report "VHPI" severity failure;
+    end procedure;
+    procedure litedram_clock is
+    begin
+        assert false report "VHPI" severity failure;
+    end procedure;
+    procedure litedram_init(trace: integer) is
+    begin
+        assert false report "VHPI" severity failure;
+    end procedure;
+end sim_litedram;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.sim_litedram.all;
+
+entity litedram_core is
+    port(
+       clk                            : in std_ulogic;
+       rst                            : in std_ulogic;
+       pll_locked                     : out std_ulogic;
+       ddram_a                        : out std_ulogic_vector(0 downto 0);
+       ddram_ba                       : out std_ulogic_vector(2 downto 0);
+       ddram_ras_n                    : out std_ulogic;
+       ddram_cas_n                    : out std_ulogic;
+       ddram_we_n                     : out std_ulogic;
+       ddram_cs_n                     : out std_ulogic;
+       ddram_dm                       : out std_ulogic_vector(1 downto 0);
+       ddram_dq                       : inout std_ulogic_vector(15 downto 0);
+       ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
+       ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
+       ddram_clk_p                    : out std_ulogic;
+       ddram_clk_n                    : out std_ulogic;
+       ddram_cke                      : out std_ulogic;
+       ddram_odt                      : out std_ulogic;
+       ddram_reset_n                  : out std_ulogic;
+       init_done                      : out std_ulogic;
+       init_error                     : out std_ulogic;
+       user_clk                       : out std_ulogic;
+       user_rst                       : out std_ulogic;
+       wb_ctrl_adr                    : in std_ulogic_vector(29 downto 0);
+       wb_ctrl_dat_w                  : in std_ulogic_vector(31 downto 0);
+       wb_ctrl_dat_r                  : out std_ulogic_vector(31 downto 0);
+       wb_ctrl_sel                    : in std_ulogic_vector(3 downto 0);
+       wb_ctrl_cyc                    : in std_ulogic;
+       wb_ctrl_stb                    : in std_ulogic;
+       wb_ctrl_ack                    : out std_ulogic;
+       wb_ctrl_we                     : in std_ulogic;
+       wb_ctrl_cti                    : in std_ulogic_vector(2 downto 0);
+       wb_ctrl_bte                    : in std_ulogic_vector(1 downto 0);
+       wb_ctrl_err                    : out std_ulogic;
+       user_port_native_0_cmd_valid   : in std_ulogic;
+       user_port_native_0_cmd_ready   : out std_ulogic;
+       user_port_native_0_cmd_we      : in std_ulogic;
+       user_port_native_0_cmd_addr    : in std_ulogic_vector(23 downto 0);
+       user_port_native_0_wdata_valid : in std_ulogic;
+       user_port_native_0_wdata_ready : out std_ulogic;
+       user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
+       user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
+       user_port_native_0_rdata_valid : out std_ulogic;
+       user_port_native_0_rdata_ready : in std_ulogic;
+       user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
+        );
+end entity litedram_core;
+
+architecture behaviour of litedram_core is
+    signal idone      : std_ulogic := '0';
+    signal ierr       : std_ulogic := '0';
+    signal old_wb_cyc : std_ulogic := '1';
+begin
+    user_rst <= rst;
+    user_clk <= clk;
+    pll_locked <= '1';
+    init_done <= idone;
+    init_error <= ierr;
+
+    poll: process(user_clk)
+        procedure send_signals is
+        begin
+            litedram_set_wb(wb_ctrl_cti & wb_ctrl_bte &
+                            wb_ctrl_sel & wb_ctrl_we &
+                            wb_ctrl_stb & wb_ctrl_cyc &
+                            wb_ctrl_adr & wb_ctrl_dat_w);
+            litedram_set_user(user_port_native_0_cmd_valid &
+                              user_port_native_0_cmd_we &
+                              user_port_native_0_wdata_valid &
+                              user_port_native_0_rdata_ready &
+                              user_port_native_0_cmd_addr &
+                              user_port_native_0_wdata_we &
+                              user_port_native_0_wdata_data);
+        end procedure;
+
+        procedure recv_signals is
+            variable wb_response  : std_ulogic_vector(35 downto 0);
+            variable ur_response  : std_ulogic_vector(130 downto 0);
+        begin
+            litedram_get_wb(wb_response);
+            wb_ctrl_dat_r <= wb_response(31 downto 0);
+            wb_ctrl_ack   <= wb_response(32);
+            wb_ctrl_err   <= wb_response(33);
+            idone         <= wb_response(34);
+            ierr          <= wb_response(35);
+            litedram_get_user(ur_response);
+            user_port_native_0_cmd_ready   <= ur_response(130);
+            user_port_native_0_wdata_ready <= ur_response(129);
+            user_port_native_0_rdata_valid <= ur_response(128);
+            user_port_native_0_rdata_data  <= ur_response(127 downto 0);
+        end procedure;
+
+    begin
+        if rising_edge(user_clk) then
+
+            send_signals;
+            recv_signals;
+            -- Then generate a clock cycle ( 0->1 then 1->0 )
+            litedram_clock;
+            recv_signals;
+        end if;
+
+        if falling_edge(user_clk) then
+            send_signals;
+            recv_signals;
+        end if;
+    end process;
+
+end architecture;
+
+library work;
+use work.sim_litedram.all;
+
+entity litedram_trace_stub is
+end entity;
+
+architecture behaviour of litedram_trace_stub is
+begin
+    process
+    begin
+        litedram_init(1);
+        wait;
+    end process;
+end architecture;

diff --git a/litedram/extras/sim_litedram_c.cpp b/litedram/extras/sim_litedram_c.cpp
new file mode 100644 (file)
index 0000000..265e9b2
--- /dev/null
+++ b/litedram/extras/sim_litedram_c.cpp
@@ -0,0 +1,198 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+#include <termios.h>
+#include <unistd.h>
+#include <poll.h>
+
+#include "sim_vhpi_c.h"
+#include "Vlitedram_core.h"
+#include "verilated_vcd_c.h"
+
+static Vlitedram_core *v;
+vluint64_t main_time = 0;
+
+#if VM_TRACE
+VerilatedVcdC *tfp;
+#endif
+
+static void cleanup(void)
+{
+#if VM_TRACE
+       if (tfp) {
+               tfp->flush();
+               tfp->close();
+               delete tfp;
+       }
+#endif
+}
+
+static inline void check_init(bool traces)
+{
+       if (v)
+               return;
+       // XX Catch exceptions ?
+       v = new Vlitedram_core;
+       if (!v) {
+               fprintf(stderr, "Failure allocating litedram core\n");
+               exit(1);
+       }
+#if VM_TRACE
+       if (traces) {
+               // init trace dump
+               Verilated::traceEverOn(true);
+               tfp = new VerilatedVcdC;
+               v->trace(tfp, 99);
+               tfp->open("litedram.vcd");
+       }
+#endif
+       atexit(cleanup);
+}
+
+unsigned char get_bit(unsigned char **p)
+{
+       unsigned char b = **p;
+
+       *p = *p + 1;
+
+       return b  == vhpi1 ? 1  : 0;
+}
+
+uint64_t get_bits(unsigned char **p, int len)
+{
+       uint64_t r = 0;
+
+       while(len--)
+               r = (r << 1) | get_bit(p);
+       
+       return r;
+}
+
+void set_bit(unsigned char **p, int bit)
+{
+       **p = bit ? vhpi1 : vhpi0;
+       *p = *p + 1;
+}
+
+void set_bits(unsigned char **p, uint64_t val, int len)
+{
+       while(len--)
+               set_bit(p, (val >> len) & 1);
+}
+
+double sc_time_stamp(void)
+{
+       return main_time;
+}
+
+#define check_size(s, exp)                                             \
+       do {                                                            \
+               int __s = (s);                                          \
+               int __e = (exp);                                        \
+               if (__s != __e)                                         \
+                       fprintf(stderr, "WARNING: %s exp %d got %d\n", __func__, __e, __s); \
+       } while(0)
+
+static void do_eval(void)
+{
+       v->eval();
+#if VM_TRACE
+       if (tfp)
+               tfp->dump((double) main_time);
+#endif
+}
+
+extern "C" void litedram_set_wb(unsigned char *req)
+{
+       unsigned char *orig = req;
+
+       check_init(false);
+       
+       v->wb_ctrl_cti   = get_bits(&req, 3);
+       v->wb_ctrl_bte   = get_bits(&req, 2);
+       v->wb_ctrl_sel   = get_bits(&req, 4);
+       v->wb_ctrl_we    = get_bit(&req);
+       v->wb_ctrl_stb   = get_bit(&req);
+       v->wb_ctrl_cyc   = get_bit(&req);
+       v->wb_ctrl_adr   = get_bits(&req, 30);
+       v->wb_ctrl_dat_w = get_bits(&req, 32);
+
+       check_size(req - orig, 74);
+
+       do_eval();
+}
+
+extern "C" void litedram_get_wb(unsigned char *req)
+{
+       unsigned char *orig = req;
+
+       check_init(false);
+
+       set_bit(&req, v->init_error);
+       set_bit(&req, v->init_done);
+       set_bit(&req, v->wb_ctrl_err);
+       set_bit(&req, v->wb_ctrl_ack);
+       set_bits(&req, v->wb_ctrl_dat_r, 32);
+
+       check_size(req - orig, 36);
+}
+
+extern "C" void litedram_set_user(unsigned char *req)
+{
+       unsigned char *orig = req;
+
+       check_init(false);
+
+       v->user_port_native_0_cmd_valid     = get_bit(&req);
+       v->user_port_native_0_cmd_we        = get_bit(&req);
+       v->user_port_native_0_wdata_valid   = get_bit(&req);
+       v->user_port_native_0_rdata_ready   = get_bit(&req);
+       v->user_port_native_0_cmd_addr      = get_bits(&req, 24);
+       v->user_port_native_0_wdata_we      = get_bits(&req, 16);
+       v->user_port_native_0_wdata_data[3] = get_bits(&req, 32);
+       v->user_port_native_0_wdata_data[2] = get_bits(&req, 32);
+       v->user_port_native_0_wdata_data[1] = get_bits(&req, 32);
+       v->user_port_native_0_wdata_data[0] = get_bits(&req, 32);
+
+       check_size(req - orig, 172);
+
+       do_eval();
+}
+
+extern "C" void litedram_get_user(unsigned char *req)
+{
+       unsigned char *orig = req;
+
+       check_init(false);
+
+       set_bit(&req, v->user_port_native_0_cmd_ready);
+       set_bit(&req, v->user_port_native_0_wdata_ready);
+       set_bit(&req, v->user_port_native_0_rdata_valid);
+       set_bits(&req, v->user_port_native_0_rdata_data[3], 32);
+       set_bits(&req, v->user_port_native_0_rdata_data[2], 32);
+       set_bits(&req, v->user_port_native_0_rdata_data[1], 32);
+       set_bits(&req, v->user_port_native_0_rdata_data[0], 32);
+
+       check_size(req - orig, 131);
+}
+
+extern "C" void litedram_clock(void)
+{
+       check_init(false);
+
+       v->clk = 1;
+       do_eval();
+       main_time++;
+       v->clk = 0;
+       do_eval();
+       main_time++;
+}
+
+extern "C" void litedram_init(int trace_on)
+{
+       check_init(!!trace_on);
+}
+
+       

diff --git a/litedram/extras/wrapper-mw-init.vhdl b/litedram/extras/wrapper-mw-init.vhdl
new file mode 100644 (file)
index 0000000..be4da1e
--- /dev/null
+++ b/litedram/extras/wrapper-mw-init.vhdl
@@ -0,0 +1,293 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity litedram_wrapper is
+    generic (
+       DRAM_ABITS     : positive;
+       DRAM_ALINES    : positive;
+        -- Debug
+        LITEDRAM_TRACE    : boolean  := false
+       );
+    port(
+       -- LiteDRAM generates the system clock and reset
+       -- from the input clkin
+       clk_in          : in std_ulogic;
+       rst             : in std_ulogic;
+       system_clk      : out std_ulogic;
+       system_reset    : out std_ulogic;
+       core_alt_reset  : out std_ulogic;
+       pll_locked      : out std_ulogic;
+
+       -- Wishbone ports:
+       wb_in           : in wishbone_master_out;
+       wb_out          : out wishbone_slave_out;
+       wb_ctrl_in      : in wb_io_master_out;
+       wb_ctrl_out     : out wb_io_slave_out;
+       wb_ctrl_is_csr  : in std_ulogic;
+       wb_ctrl_is_init : in std_ulogic;
+
+       -- Init core serial debug
+       serial_tx     : out std_ulogic;
+       serial_rx     : in std_ulogic;
+
+       -- Misc
+       init_done     : out std_ulogic;
+       init_error    : out std_ulogic;
+
+       -- DRAM wires
+       ddram_a       : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+       ddram_ba      : out std_ulogic_vector(2 downto 0);
+       ddram_ras_n   : out std_ulogic;
+       ddram_cas_n   : out std_ulogic;
+       ddram_we_n    : out std_ulogic;
+       ddram_cs_n    : out std_ulogic;
+       ddram_dm      : out std_ulogic_vector(1 downto 0);
+       ddram_dq      : inout std_ulogic_vector(15 downto 0);
+       ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
+       ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
+       ddram_clk_p   : out std_ulogic;
+       ddram_clk_n   : out std_ulogic;
+       ddram_cke     : out std_ulogic;
+       ddram_odt     : out std_ulogic;
+       ddram_reset_n : out std_ulogic
+       );
+end entity litedram_wrapper;
+
+architecture behaviour of litedram_wrapper is
+
+    component litedram_core port (
+       clk                            : in std_ulogic;
+       rst                            : in std_ulogic;
+       pll_locked                     : out std_ulogic;
+       ddram_a                        : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+       ddram_ba                       : out std_ulogic_vector(2 downto 0);
+       ddram_ras_n                    : out std_ulogic;
+       ddram_cas_n                    : out std_ulogic;
+       ddram_we_n                     : out std_ulogic;
+       ddram_cs_n                     : out std_ulogic;
+       ddram_dm                       : out std_ulogic_vector(1 downto 0);
+       ddram_dq                       : inout std_ulogic_vector(15 downto 0);
+       ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
+       ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
+       ddram_clk_p                    : out std_ulogic;
+       ddram_clk_n                    : out std_ulogic;
+       ddram_cke                      : out std_ulogic;
+       ddram_odt                      : out std_ulogic;
+       ddram_reset_n                  : out std_ulogic;
+       init_done                      : out std_ulogic;
+       init_error                     : out std_ulogic;
+       user_clk                       : out std_ulogic;
+       user_rst                       : out std_ulogic;
+       wb_ctrl_adr                    : in std_ulogic_vector(29 downto 0);
+       wb_ctrl_dat_w                  : in std_ulogic_vector(31 downto 0);
+       wb_ctrl_dat_r                  : out std_ulogic_vector(31 downto 0);
+       wb_ctrl_sel                    : in std_ulogic_vector(3 downto 0);
+       wb_ctrl_cyc                    : in std_ulogic;
+       wb_ctrl_stb                    : in std_ulogic;
+       wb_ctrl_ack                    : out std_ulogic;
+       wb_ctrl_we                     : in std_ulogic;
+       wb_ctrl_cti                    : in std_ulogic_vector(2 downto 0);
+       wb_ctrl_bte                    : in std_ulogic_vector(1 downto 0);
+       wb_ctrl_err                    : out std_ulogic;
+       user_port_native_0_cmd_valid   : in std_ulogic;
+       user_port_native_0_cmd_ready   : out std_ulogic;
+       user_port_native_0_cmd_we      : in std_ulogic;
+       user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
+       user_port_native_0_wdata_valid : in std_ulogic;
+       user_port_native_0_wdata_ready : out std_ulogic;
+       user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
+       user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
+       user_port_native_0_rdata_valid : out std_ulogic;
+       user_port_native_0_rdata_ready : in std_ulogic;
+       user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
+       );
+    end component;
+    
+    signal user_port0_cmd_valid                : std_ulogic;
+    signal user_port0_cmd_ready                : std_ulogic;
+    signal user_port0_cmd_we           : std_ulogic;
+    signal user_port0_cmd_addr         : std_ulogic_vector(DRAM_ABITS-1 downto 0);
+    signal user_port0_wdata_valid      : std_ulogic;
+    signal user_port0_wdata_ready      : std_ulogic;
+    signal user_port0_wdata_we         : std_ulogic_vector(15 downto 0);
+    signal user_port0_wdata_data       : std_ulogic_vector(127 downto 0);
+    signal user_port0_rdata_valid      : std_ulogic;
+    signal user_port0_rdata_ready      : std_ulogic;
+    signal user_port0_rdata_data       : std_ulogic_vector(127 downto 0);
+
+    signal ad3                          : std_ulogic;
+
+    signal wb_ctrl_adr                  : std_ulogic_vector(29 downto 0);
+    signal wb_ctrl_dat_w                : std_ulogic_vector(31 downto 0);
+    signal wb_ctrl_dat_r                : std_ulogic_vector(31 downto 0);
+    signal wb_ctrl_sel                  : std_ulogic_vector(3 downto 0);
+    signal wb_ctrl_cyc                  : std_ulogic;
+    signal wb_ctrl_stb                  : std_ulogic;
+    signal wb_ctrl_ack                  : std_ulogic;
+    signal wb_ctrl_we                   : std_ulogic;
+
+    signal wb_init_in                   : wb_io_master_out;
+    signal wb_init_out                  : wb_io_slave_out;
+
+    type state_t is (CMD, MWRITE, MREAD);
+    signal state : state_t;
+
+begin
+
+    -- alternate core reset address set when DRAM is not initialized.
+    core_alt_reset <= not init_done;
+
+    -- Init code BRAM memory slave 
+    init_ram_0: entity work.dram_init_mem
+        port map(
+            clk => system_clk,
+            wb_in => wb_init_in,
+            wb_out => wb_init_out
+            );
+
+    --
+    -- Control bus wishbone: This muxes the wishbone to the CSRs
+    -- and an internal small one to the init BRAM
+    --
+
+    -- Init DRAM wishbone IN signals
+    wb_init_in.adr <= wb_ctrl_in.adr;
+    wb_init_in.dat <= wb_ctrl_in.dat;
+    wb_init_in.sel <= wb_ctrl_in.sel;
+    wb_init_in.we  <= wb_ctrl_in.we;
+    wb_init_in.stb <= wb_ctrl_in.stb;
+    wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init;
+
+    -- DRAM CSR IN signals
+    wb_ctrl_adr   <= x"0000" & wb_ctrl_in.adr(15 downto 2);
+    wb_ctrl_dat_w <= wb_ctrl_in.dat;
+    wb_ctrl_sel   <= wb_ctrl_in.sel;
+    wb_ctrl_we    <= wb_ctrl_in.we;
+    wb_ctrl_cyc   <= wb_ctrl_in.cyc and wb_ctrl_is_csr;
+    wb_ctrl_stb   <= wb_ctrl_in.stb and wb_ctrl_is_csr;
+
+    -- Ctrl bus wishbone OUT signals
+    wb_ctrl_out.ack   <= wb_ctrl_ack when wb_ctrl_is_csr = '1'
+                         else wb_init_out.ack;
+    wb_ctrl_out.dat   <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1'
+                         else wb_init_out.dat;
+    wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else
+                         '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack;
+
+    --
+    -- Data bus wishbone to LiteDRAM native port
+    --
+    -- Address bit 3 selects the top or bottom half of the data
+    -- bus (64-bit wishbone vs. 128-bit DRAM interface)
+    --
+    -- XXX TODO: Figure out how to pipeline this
+    --
+    ad3 <= wb_in.adr(3);
+
+    -- Wishbone port IN signals
+    user_port0_cmd_valid   <= wb_in.cyc and wb_in.stb when state = CMD else '0';
+    user_port0_cmd_we      <= wb_in.we when state = CMD else '0';
+    user_port0_wdata_valid <= '1' when state = MWRITE else '0';
+    user_port0_rdata_ready <= '1' when state = MREAD else '0';
+    user_port0_cmd_addr    <= wb_in.adr(DRAM_ABITS+3 downto 4);
+    user_port0_wdata_data  <= wb_in.dat & wb_in.dat;
+    user_port0_wdata_we    <= wb_in.sel & "00000000" when ad3 = '1' else
+                              "00000000" & wb_in.sel;
+
+    -- Wishbone OUT signals
+    wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
+                 user_port0_rdata_valid when state = MREAD else '0';
+
+    wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
+                 user_port0_rdata_data(63 downto 0);
+
+    -- We don't do pipelining yet.
+    wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
+
+    -- DRAM user port State machine
+    sm: process(system_clk)
+    begin
+       
+       if rising_edge(system_clk) then
+           if system_reset = '1' then
+               state <= CMD;
+           else
+               case state is
+               when CMD =>
+                    if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
+                       state <= MWRITE when wb_in.we = '1' else MREAD;
+                   end if;
+               when MWRITE =>
+                   if user_port0_wdata_ready = '1' then
+                       state <= CMD;
+                   end if;
+               when MREAD =>
+                   if user_port0_rdata_valid = '1' then
+                       state <= CMD;
+                   end if;
+                end case;
+           end if;
+       end if;
+    end process;
+
+    may_trace: if LITEDRAM_TRACE generate
+        component litedram_trace_stub
+        end component;
+    begin
+        litedram_trace: litedram_trace_stub;
+    end generate;
+    
+    litedram: litedram_core
+       port map(
+           clk => clk_in,
+           rst => rst,
+           pll_locked => pll_locked,
+           ddram_a => ddram_a,
+           ddram_ba => ddram_ba,
+           ddram_ras_n => ddram_ras_n,
+           ddram_cas_n => ddram_cas_n,
+           ddram_we_n => ddram_we_n,
+           ddram_cs_n => ddram_cs_n,
+           ddram_dm => ddram_dm,
+           ddram_dq => ddram_dq,
+           ddram_dqs_p => ddram_dqs_p,
+           ddram_dqs_n => ddram_dqs_n,
+           ddram_clk_p => ddram_clk_p,
+           ddram_clk_n => ddram_clk_n,
+           ddram_cke => ddram_cke,
+           ddram_odt => ddram_odt,
+           ddram_reset_n => ddram_reset_n,
+           init_done => init_done,
+           init_error => init_error,
+           user_clk => system_clk,
+           user_rst => system_reset,
+            wb_ctrl_adr => wb_ctrl_adr,
+            wb_ctrl_dat_w => wb_ctrl_dat_w,
+            wb_ctrl_dat_r => wb_ctrl_dat_r,
+            wb_ctrl_sel => wb_ctrl_sel,
+            wb_ctrl_cyc => wb_ctrl_cyc,
+            wb_ctrl_stb => wb_ctrl_stb,
+            wb_ctrl_ack => wb_ctrl_ack,
+            wb_ctrl_we => wb_ctrl_we,
+            wb_ctrl_cti => "000",
+            wb_ctrl_bte => "00",
+            wb_ctrl_err => open,
+           user_port_native_0_cmd_valid => user_port0_cmd_valid,
+           user_port_native_0_cmd_ready => user_port0_cmd_ready,
+           user_port_native_0_cmd_we => user_port0_cmd_we,
+           user_port_native_0_cmd_addr => user_port0_cmd_addr,
+           user_port_native_0_wdata_valid => user_port0_wdata_valid,
+           user_port_native_0_wdata_ready => user_port0_wdata_ready,
+           user_port_native_0_wdata_we => user_port0_wdata_we,
+           user_port_native_0_wdata_data => user_port0_wdata_data,
+           user_port_native_0_rdata_valid => user_port0_rdata_valid,
+           user_port_native_0_rdata_ready => user_port0_rdata_ready,
+           user_port_native_0_rdata_data => user_port0_rdata_data
+           );
+
+end architecture behaviour;

diff --git a/litedram/extras/wrapper-self-init.vhdl b/litedram/extras/wrapper-self-init.vhdl
new file mode 100644 (file)
index 0000000..d57c99b
--- /dev/null
+++ b/litedram/extras/wrapper-self-init.vhdl
@@ -0,0 +1,225 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity litedram_wrapper is
+    generic (
+       DRAM_ABITS     : positive;
+       DRAM_ALINES    : positive
+       );
+    port(
+       -- LiteDRAM generates the system clock and reset
+       -- from the input clkin
+       clk_in          : in std_ulogic;
+       rst             : in std_ulogic;
+       system_clk      : out std_ulogic;
+       system_reset    : out std_ulogic;
+       core_alt_reset  : out std_ulogic;
+       pll_locked      : out std_ulogic;
+
+       -- Wishbone ports:
+       wb_in           : in wishbone_master_out;
+       wb_out          : out wishbone_slave_out;
+       wb_ctrl_in      : in wb_io_master_out;
+       wb_ctrl_out     : out wb_io_slave_out;
+       wb_ctrl_is_csr  : in std_ulogic;
+       wb_ctrl_is_init : in std_ulogic;
+
+       -- Init core serial debug
+       serial_tx     : out std_ulogic;
+       serial_rx     : in std_ulogic;
+
+       -- Misc
+       init_done     : out std_ulogic;
+       init_error    : out std_ulogic;
+
+       -- DRAM wires
+       ddram_a       : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+       ddram_ba      : out std_ulogic_vector(2 downto 0);
+       ddram_ras_n   : out std_ulogic;
+       ddram_cas_n   : out std_ulogic;
+       ddram_we_n    : out std_ulogic;
+       ddram_cs_n    : out std_ulogic;
+       ddram_dm      : out std_ulogic_vector(1 downto 0);
+       ddram_dq      : inout std_ulogic_vector(15 downto 0);
+       ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
+       ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
+       ddram_clk_p   : out std_ulogic;
+       ddram_clk_n   : out std_ulogic;
+       ddram_cke     : out std_ulogic;
+       ddram_odt     : out std_ulogic;
+       ddram_reset_n : out std_ulogic
+end entity litedram_wrapper;
+
+architecture behaviour of litedram_wrapper is
+
+    component litedram_core port (
+       clk                    : in std_ulogic;
+       rst                    : in std_ulogic;
+       serial_tx              : out std_ulogic;
+       serial_rx              : in std_ulogic;
+       pll_locked             : out std_ulogic;
+       ddram_a                : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
+       ddram_ba               : out std_ulogic_vector(2 downto 0);
+       ddram_ras_n            : out std_ulogic;
+       ddram_cas_n            : out std_ulogic;
+       ddram_we_n             : out std_ulogic;
+       ddram_cs_n             : out std_ulogic;
+       ddram_dm               : out std_ulogic_vector(1 downto 0);
+       ddram_dq               : inout std_ulogic_vector(15 downto 0);
+       ddram_dqs_p            : inout std_ulogic_vector(1 downto 0);
+       ddram_dqs_n            : inout std_ulogic_vector(1 downto 0);
+       ddram_clk_p            : out std_ulogic;
+       ddram_clk_n            : out std_ulogic;
+       ddram_cke              : out std_ulogic;
+       ddram_odt              : out std_ulogic;
+       ddram_reset_n          : out std_ulogic;
+       init_done              : out std_ulogic;
+       init_error             : out std_ulogic;
+       user_clk               : out std_ulogic;
+       user_rst               : out std_ulogic;
+       user_port_native_0_cmd_valid   : in std_ulogic;
+       user_port_native_0_cmd_ready   : out std_ulogic;
+       user_port_native_0_cmd_we      : in std_ulogic;
+       user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
+       user_port_native_0_wdata_valid : in std_ulogic;
+       user_port_native_0_wdata_ready : out std_ulogic;
+       user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
+       user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
+       user_port_native_0_rdata_valid : out std_ulogic;
+       user_port_native_0_rdata_ready : in std_ulogic;
+       user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
+       );
+    end component;
+    
+    signal user_port0_cmd_valid                : std_ulogic;
+    signal user_port0_cmd_ready                : std_ulogic;
+    signal user_port0_cmd_we           : std_ulogic;
+    signal user_port0_cmd_addr         : std_ulogic_vector(DRAM_ABITS-1 downto 0);
+    signal user_port0_wdata_valid      : std_ulogic;
+    signal user_port0_wdata_ready      : std_ulogic;
+    signal user_port0_wdata_we         : std_ulogic_vector(15 downto 0);
+    signal user_port0_wdata_data       : std_ulogic_vector(127 downto 0);
+    signal user_port0_rdata_valid      : std_ulogic;
+    signal user_port0_rdata_ready      : std_ulogic;
+    signal user_port0_rdata_data       : std_ulogic_vector(127 downto 0);
+
+    signal ad3                          : std_ulogic;
+
+    signal dram_user_reset              : std_ulogic;
+
+    type state_t is (CMD, MWRITE, MREAD);
+    signal state : state_t;
+
+begin
+
+    -- Reset, lift it when init done, no alt core reset
+    system_reset <= dram_user_reset or not init_done;
+    core_alt_reset <= '0';
+
+    -- Control bus is unused
+    wb_ctrl_out.ack   <= (wb_is_ctrl = '1' or wb_is_init = '1') and wb_ctrl_in.cyc;
+                         else wb_init_out.ack;
+    wb_ctrl_out.dat   <= (others => '0');
+    wb_ctrl_out.stall <= '0';
+
+    --
+    -- Data bus wishbone to LiteDRAM native port
+    --
+    -- Address bit 3 selects the top or bottom half of the data
+    -- bus (64-bit wishbone vs. 128-bit DRAM interface)
+    --
+    -- XXX TODO: Figure out how to pipeline this
+    --
+    ad3 <= wb_in.adr(3);
+
+    -- Wishbone port IN signals
+    user_port0_cmd_valid   <= wb_in.cyc and wb_in.stb when state = CMD else '0';
+    user_port0_cmd_we      <= wb_in.we when state = CMD else '0';
+    user_port0_wdata_valid <= '1' when state = MWRITE else '0';
+    user_port0_rdata_ready <= '1' when state = MREAD else '0';
+    user_port0_cmd_addr    <= wb_in.adr(DRAM_ABITS+3 downto 4);
+    user_port0_wdata_data  <= wb_in.dat & wb_in.dat;
+    user_port0_wdata_we    <= wb_in.sel & "00000000" when ad3 = '1' else
+                              "00000000" & wb_in.sel;
+
+    -- Wishbone OUT signals
+    wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
+                 user_port0_rdata_valid when state = MREAD else '0';
+
+    wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
+                 user_port0_rdata_data(63 downto 0);
+
+    -- We don't do pipelining yet.
+    wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
+
+    -- DRAM user port State machine
+    sm: process(system_clk)
+    begin
+       
+       if rising_edge(system_clk) then
+           if dram_user_reset = '1' then
+               state <= CMD;
+           else
+               case state is
+               when CMD =>
+                   if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
+                       state <= MWRITE when wb_in.we = '1' else MREAD;
+                   end if;
+               when MWRITE =>
+                   if user_port0_wdata_ready = '1' then
+                       state <= CMD;
+                   end if;
+               when MREAD =>
+                   if user_port0_rdata_valid = '1' then
+                       state <= CMD;
+                   end if;
+               end case;
+           end if;
+       end if;
+    end process;
+
+    litedram: litedram_core
+       port map(
+           clk => clk_in,
+           rst => rst,
+           serial_tx => serial_tx,
+           serial_rx => serial_rx,
+           pll_locked => pll_locked,
+           ddram_a => ddram_a,
+           ddram_ba => ddram_ba,
+           ddram_ras_n => ddram_ras_n,
+           ddram_cas_n => ddram_cas_n,
+           ddram_we_n => ddram_we_n,
+           ddram_cs_n => ddram_cs_n,
+           ddram_dm => ddram_dm,
+           ddram_dq => ddram_dq,
+           ddram_dqs_p => ddram_dqs_p,
+           ddram_dqs_n => ddram_dqs_n,
+           ddram_clk_p => ddram_clk_p,
+           ddram_clk_n => ddram_clk_n,
+           ddram_cke => ddram_cke,
+           ddram_odt => ddram_odt,
+           ddram_reset_n => ddram_reset_n,
+           init_done => init_done,
+           init_error => init_error,
+           user_clk => system_clk,
+           user_rst => dram_user_reset,
+           user_port_native_0_cmd_valid => user_port0_cmd_valid,
+           user_port_native_0_cmd_ready => user_port0_cmd_ready,
+           user_port_native_0_cmd_we => user_port0_cmd_we,
+           user_port_native_0_cmd_addr => user_port0_cmd_addr,
+           user_port_native_0_wdata_valid => user_port0_wdata_valid,
+           user_port_native_0_wdata_ready => user_port0_wdata_ready,
+           user_port_native_0_wdata_we => user_port0_wdata_we,
+           user_port_native_0_wdata_data => user_port0_wdata_data,
+           user_port_native_0_rdata_valid => user_port0_rdata_valid,
+           user_port_native_0_rdata_ready => user_port0_rdata_ready,
+           user_port_native_0_rdata_data => user_port0_rdata_data
+           );
+
+end architecture behaviour;

diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py
index e44cd08893df4ddf07c042857832463dcb4c419c..1c8069cfdc925ba255ac3e6cfb43fb8010eff778 100755 (executable)
--- a/litedram/gen-src/generate.py
+++ b/litedram/gen-src/generate.py
@@ -22,7 +22,7 @@ def make_new_dir(base, added):
     return r
     
 gen_src_dir = os.path.dirname(os.path.realpath(__file__))
-base_dir = os.path.join(gen_src_dir, os.pardir)
+base_dir = os.path.normpath(os.path.join(gen_src_dir, os.pardir))
 build_top_dir = make_new_dir(base_dir, "build")
 gen_src_dir = os.path.join(base_dir, "gen-src")
 gen_dir = make_new_dir(base_dir, "generated")
@@ -31,7 +31,7 @@ gen_dir = make_new_dir(base_dir, "generated")
 #
 # XXX Not working yet
 #
-def build_init_code(build_dir):
+def build_init_code(build_dir, is_sim):
 
     # More path fudging
     sw_dir = os.path.join(build_dir, "software");
@@ -62,6 +62,8 @@ def build_init_code(build_dir):
     add_var("GENINC_DIR", sw_inc_dir)
     add_var("LXSRC_DIR", lxbios_src_dir)
     add_var("LXINC_DIR", lxbios_inc_dir)
+    if is_sim:
+        add_var("EXTRA_CFLAGS", "-D__SIM__")
     write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars))
 
     # Build init code
@@ -76,6 +78,9 @@ def generate_one(t, mw_init):
 
     print("Generating target:", t)
 
+    # Is it a simulation ?
+    is_sim = t is "sim"
+
     # Muck with directory path
     build_dir = make_new_dir(build_top_dir, t)
     t_dir = make_new_dir(gen_dir, t)
@@ -107,14 +112,16 @@ def generate_one(t, mw_init):
         core_config["csr_alignment"] = 64
 
     # Generate core
-    if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
+    if is_sim:
+        platform = SimPlatform("", io=[])
+    elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
         platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis")
     elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
         platform = XilinxPlatform("", io=[], toolchain="vivado")
     else:
         raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"]))
 
-    soc      = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, csr_data_width=32)
+    soc      = LiteDRAMCore(platform, core_config, is_sim = is_sim, integrated_rom_size=0x6000, csr_data_width=32)
 
     # Build into build_dir
     builder  = Builder(soc, output_dir=build_dir, compile_gateware=False)
@@ -123,32 +130,35 @@ def generate_one(t, mw_init):
     # Grab generated gatewar dir
     gw_dir = os.path.join(build_dir, "gateware")
 
-    # Generate init-cpu.txt if any and generate init code if none
+    # Generate init-cpu.txt and generate init code
     cpu = core_config["cpu"]
     if mw_init:
-        src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl")
-        src_init_file = build_init_code(build_dir)
+        write_to_file(os.path.join(t_dir, "init-cpu.txt"), "none")
+        src_init_file = build_init_code(build_dir, is_sim)
         src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
     else:
         write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu)
-        src_wrap_file = os.path.join(gen_src_dir, "wrapper-self-init.vhdl")
         src_init_file = os.path.join(gw_dir, "mem.init")
         src_initram_file = os.path.join(gen_src_dir, "no-init-mem.vhdl")
 
     # Copy generated files to target dir, amend them if necessary
+    initfile_name = "litedram_core.init"
     core_file = os.path.join(gw_dir, "litedram_core.v")
-    dst_init_file = os.path.join(t_dir, "litedram_core.init")
-    dst_wrap_file = os.path.join(t_dir, "litedram-wrapper.vhdl")
+    dst_init_file = os.path.join(t_dir, initfile_name)
     dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl")
-    replace_in_file(core_file, "mem.init", "litedram_core.init")
-    shutil.copy(core_file, t_dir)
+    if not mw_init:
+        replace_in_file(core_file, "mem.init", initfile_name)
     shutil.copyfile(src_init_file, dst_init_file)    
-    shutil.copyfile(src_wrap_file, dst_wrap_file)
     shutil.copyfile(src_initram_file, dst_initram_file)
+    if is_sim:
+        initfile_path = os.path.join("litedram", "generated", "sim", initfile_name)
+        replace_in_file(dst_initram_file, initfile_name, initfile_path)
+    shutil.copy(core_file, t_dir)
 
 def main():
 
-    targets = ['arty','nexys-video']
+    targets = ['arty','nexys-video', 'sim']
+#    targets = ['sim']
 
     # XXX Set mw_init to False to use a local VexRiscV for memory inits
     for t in targets:

diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile
index 420072ec1067f55a6af8d84d0aaf63ec21f1184e..71ca921a13a778c7bb5df82a479ca26a091fffcc 100644 (file)
--- a/litedram/gen-src/sdram_init/Makefile
+++ b/litedram/gen-src/sdram_init/Makefile
@@ -21,7 +21,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
 
 #### Flags
 
-CPPFLAGS = -nostdinc -D__USE_LIBC
+CPPFLAGS = -nostdinc -D__USE_LIBC $(EXTRA_CFLAGS)
 CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include
 CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include)
 CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks 

diff --git a/litedram/gen-src/sdram_init/include/system.h b/litedram/gen-src/sdram_init/include/system.h
index ded9b10334768c86aa6e958ef174f9e205f66502..b980427fd757db9d3ef206e32c6a78249ce31154 100644 (file)
--- a/litedram/gen-src/sdram_init/include/system.h
+++ b/litedram/gen-src/sdram_init/include/system.h
@@ -8,6 +8,13 @@
 #define CSR_BASE               DRAM_CTRL_BASE
 #define CONFIG_CPU_NOP         "nop"
 
+#ifdef __SIM__
+#define MEMTEST_BUS_SIZE       16
+#define MEMTEST_DATA_SIZE      16
+#define MEMTEST_ADDR_SIZE      16
+#define CONFIG_SIM_DISABLE_DELAYS
+#endif
+
 extern void flush_cpu_dcache(void);
 extern void flush_cpu_icache(void);
 static inline void flush_l2_cache(void) { }

diff --git a/litedram/gen-src/sim.yml b/litedram/gen-src/sim.yml
new file mode 100644 (file)
index 0000000..afb0638
--- /dev/null
+++ b/litedram/gen-src/sim.yml
@@ -0,0 +1,39 @@
+# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+{
+    # General ------------------------------------------------------------------
+    "cpu":        "None",  # Type of CPU used for init/calib (vexriscv, lm32)
+    "cpu_variant":"minimal",
+    "speedgrade": -1,          # FPGA speedgrade
+    "memtype":    "DDR3",      # DRAM type
+     "sim" : "True",
+
+    # PHY ----------------------------------------------------------------------
+    "cmd_delay":       0,             # Command additional delay (in taps)
+    "cmd_latency":     0,             # Command additional latency
+    "sdram_module":    "MT41K128M16", # SDRAM modules of the board or SO-DIMM
+    "sdram_module_nb": 2,             # Number of byte groups
+    "sdram_rank_nb":   1,             # Number of ranks
+    "sdram_phy":       "A7DDRPHY",    # Type of FPGA PHY
+
+    # Electrical ---------------------------------------------------------------
+    "rtt_nom": "60ohm",  # Nominal termination
+    "rtt_wr":  "60ohm",  # Write termination
+    "ron":     "34ohm",  # Output driver impedance
+
+    # Frequency ----------------------------------------------------------------
+    "input_clk_freq":   100e6, # Input clock frequency
+    "sys_clk_freq":     100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
+    "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
+
+    # Core ---------------------------------------------------------------------
+    "cmd_buffer_depth": 16,    # Depth of the command buffer
+
+    # User Ports ---------------------------------------------------------------
+    "user_ports": {
+        "native_0": {
+            "type": "native",
+        },
+    },
+}

diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl
deleted file mode 100644 (file)
index f12e3df..0000000
--- a/litedram/gen-src/wrapper-mw-init.vhdl
+++ /dev/null
@@ -1,284 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use std.textio.all;
-
-library work;
-use work.wishbone_types.all;
-
-entity litedram_wrapper is
-    generic (
-       DRAM_ABITS     : positive;
-       DRAM_ALINES    : positive
-       );
-    port(
-       -- LiteDRAM generates the system clock and reset
-       -- from the input clkin
-       clk_in          : in std_ulogic;
-       rst             : in std_ulogic;
-       system_clk      : out std_ulogic;
-       system_reset    : out std_ulogic;
-       core_alt_reset  : out std_ulogic;
-       pll_locked      : out std_ulogic;
-
-       -- Wishbone ports:
-       wb_in           : in wishbone_master_out;
-       wb_out          : out wishbone_slave_out;
-       wb_ctrl_in      : in wb_io_master_out;
-       wb_ctrl_out     : out wb_io_slave_out;
-       wb_ctrl_is_csr  : in std_ulogic;
-       wb_ctrl_is_init : in std_ulogic;
-
-       -- Init core serial debug
-       serial_tx     : out std_ulogic;
-       serial_rx     : in std_ulogic;
-
-       -- Misc
-       init_done     : out std_ulogic;
-       init_error    : out std_ulogic;
-
-       -- DRAM wires
-       ddram_a       : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-       ddram_ba      : out std_ulogic_vector(2 downto 0);
-       ddram_ras_n   : out std_ulogic;
-       ddram_cas_n   : out std_ulogic;
-       ddram_we_n    : out std_ulogic;
-       ddram_cs_n    : out std_ulogic;
-       ddram_dm      : out std_ulogic_vector(1 downto 0);
-       ddram_dq      : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
-       ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
-       ddram_clk_p   : out std_ulogic;
-       ddram_clk_n   : out std_ulogic;
-       ddram_cke     : out std_ulogic;
-       ddram_odt     : out std_ulogic;
-       ddram_reset_n : out std_ulogic
-       );
-end entity litedram_wrapper;
-
-architecture behaviour of litedram_wrapper is
-
-    component litedram_core port (
-       clk                            : in std_ulogic;
-       rst                            : in std_ulogic;
-       pll_locked                     : out std_ulogic;
-       ddram_a                        : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-       ddram_ba                       : out std_ulogic_vector(2 downto 0);
-       ddram_ras_n                    : out std_ulogic;
-       ddram_cas_n                    : out std_ulogic;
-       ddram_we_n                     : out std_ulogic;
-       ddram_cs_n                     : out std_ulogic;
-       ddram_dm                       : out std_ulogic_vector(1 downto 0);
-       ddram_dq                       : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
-       ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
-       ddram_clk_p                    : out std_ulogic;
-       ddram_clk_n                    : out std_ulogic;
-       ddram_cke                      : out std_ulogic;
-       ddram_odt                      : out std_ulogic;
-       ddram_reset_n                  : out std_ulogic;
-       init_done                      : out std_ulogic;
-       init_error                     : out std_ulogic;
-       user_clk                       : out std_ulogic;
-       user_rst                       : out std_ulogic;
-       wb_ctrl_adr                    : in std_ulogic_vector(29 downto 0);
-       wb_ctrl_dat_w                  : in std_ulogic_vector(31 downto 0);
-       wb_ctrl_dat_r                  : out std_ulogic_vector(31 downto 0);
-       wb_ctrl_sel                    : in std_ulogic_vector(3 downto 0);
-       wb_ctrl_cyc                    : in std_ulogic;
-       wb_ctrl_stb                    : in std_ulogic;
-       wb_ctrl_ack                    : out std_ulogic;
-       wb_ctrl_we                     : in std_ulogic;
-       wb_ctrl_cti                    : in std_ulogic_vector(2 downto 0);
-       wb_ctrl_bte                    : in std_ulogic_vector(1 downto 0);
-       wb_ctrl_err                    : out std_ulogic;
-       user_port_native_0_cmd_valid   : in std_ulogic;
-       user_port_native_0_cmd_ready   : out std_ulogic;
-       user_port_native_0_cmd_we      : in std_ulogic;
-       user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
-       user_port_native_0_wdata_valid : in std_ulogic;
-       user_port_native_0_wdata_ready : out std_ulogic;
-       user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
-       user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
-       user_port_native_0_rdata_valid : out std_ulogic;
-       user_port_native_0_rdata_ready : in std_ulogic;
-       user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
-       );
-    end component;
-    
-    signal user_port0_cmd_valid                : std_ulogic;
-    signal user_port0_cmd_ready                : std_ulogic;
-    signal user_port0_cmd_we           : std_ulogic;
-    signal user_port0_cmd_addr         : std_ulogic_vector(DRAM_ABITS-1 downto 0);
-    signal user_port0_wdata_valid      : std_ulogic;
-    signal user_port0_wdata_ready      : std_ulogic;
-    signal user_port0_wdata_we         : std_ulogic_vector(15 downto 0);
-    signal user_port0_wdata_data       : std_ulogic_vector(127 downto 0);
-    signal user_port0_rdata_valid      : std_ulogic;
-    signal user_port0_rdata_ready      : std_ulogic;
-    signal user_port0_rdata_data       : std_ulogic_vector(127 downto 0);
-
-    signal ad3                          : std_ulogic;
-
-    signal wb_ctrl_adr                  : std_ulogic_vector(29 downto 0);
-    signal wb_ctrl_dat_w                : std_ulogic_vector(31 downto 0);
-    signal wb_ctrl_dat_r                : std_ulogic_vector(31 downto 0);
-    signal wb_ctrl_sel                  : std_ulogic_vector(3 downto 0);
-    signal wb_ctrl_cyc                  : std_ulogic;
-    signal wb_ctrl_stb                  : std_ulogic;
-    signal wb_ctrl_ack                  : std_ulogic;
-    signal wb_ctrl_we                   : std_ulogic;
-
-    signal wb_init_in                   : wb_io_master_out;
-    signal wb_init_out                  : wb_io_slave_out;
-
-    type state_t is (CMD, MWRITE, MREAD);
-    signal state : state_t;
-
-begin
-
-    -- alternate core reset address set when DRAM is not initialized.
-    core_alt_reset <= not init_done;
-
-    -- Init code BRAM memory slave 
-    init_ram_0: entity work.dram_init_mem
-        port map(
-            clk => system_clk,
-            wb_in => wb_init_in,
-            wb_out => wb_init_out
-            );
-
-    --
-    -- Control bus wishbone: This muxes the wishbone to the CSRs
-    -- and an internal small one to the init BRAM
-    --
-
-    -- Init DRAM wishbone IN signals
-    wb_init_in.adr <= wb_ctrl_in.adr;
-    wb_init_in.dat <= wb_ctrl_in.dat;
-    wb_init_in.sel <= wb_ctrl_in.sel;
-    wb_init_in.we  <= wb_ctrl_in.we;
-    wb_init_in.stb <= wb_ctrl_in.stb;
-    wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init;
-
-    -- DRAM CSR IN signals
-    wb_ctrl_adr   <= x"0000" & wb_ctrl_in.adr(15 downto 2);
-    wb_ctrl_dat_w <= wb_ctrl_in.dat;
-    wb_ctrl_sel   <= wb_ctrl_in.sel;
-    wb_ctrl_we    <= wb_ctrl_in.we;
-    wb_ctrl_cyc   <= wb_ctrl_in.cyc and wb_ctrl_is_csr;
-    wb_ctrl_stb   <= wb_ctrl_in.stb and wb_ctrl_is_csr;
-
-    -- Ctrl bus wishbone OUT signals
-    wb_ctrl_out.ack   <= wb_ctrl_ack when wb_ctrl_is_csr = '1'
-                         else wb_init_out.ack;
-    wb_ctrl_out.dat   <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1'
-                         else wb_init_out.dat;
-    wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else
-                         '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack;
-
-    --
-    -- Data bus wishbone to LiteDRAM native port
-    --
-    -- Address bit 3 selects the top or bottom half of the data
-    -- bus (64-bit wishbone vs. 128-bit DRAM interface)
-    --
-    -- XXX TODO: Figure out how to pipeline this
-    --
-    ad3 <= wb_in.adr(3);
-
-    -- Wishbone port IN signals
-    user_port0_cmd_valid   <= wb_in.cyc and wb_in.stb when state = CMD else '0';
-    user_port0_cmd_we      <= wb_in.we when state = CMD else '0';
-    user_port0_wdata_valid <= '1' when state = MWRITE else '0';
-    user_port0_rdata_ready <= '1' when state = MREAD else '0';
-    user_port0_cmd_addr    <= wb_in.adr(DRAM_ABITS+3 downto 4);
-    user_port0_wdata_data  <= wb_in.dat & wb_in.dat;
-    user_port0_wdata_we    <= wb_in.sel & "00000000" when ad3 = '1' else
-                              "00000000" & wb_in.sel;
-
-    -- Wishbone OUT signals
-    wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
-                 user_port0_rdata_valid when state = MREAD else '0';
-
-    wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
-                 user_port0_rdata_data(63 downto 0);
-
-    -- We don't do pipelining yet.
-    wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
-
-    -- DRAM user port State machine
-    sm: process(system_clk)
-    begin
-       
-       if rising_edge(system_clk) then
-           if system_reset = '1' then
-               state <= CMD;
-           else
-               case state is
-               when CMD =>
-                    if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
-                       state <= MWRITE when wb_in.we = '1' else MREAD;
-                   end if;
-               when MWRITE =>
-                   if user_port0_wdata_ready = '1' then
-                       state <= CMD;
-                   end if;
-               when MREAD =>
-                   if user_port0_rdata_valid = '1' then
-                       state <= CMD;
-                   end if;
-                end case;
-           end if;
-       end if;
-    end process;
-
-    litedram: litedram_core
-       port map(
-           clk => clk_in,
-           rst => rst,
-           pll_locked => pll_locked,
-           ddram_a => ddram_a,
-           ddram_ba => ddram_ba,
-           ddram_ras_n => ddram_ras_n,
-           ddram_cas_n => ddram_cas_n,
-           ddram_we_n => ddram_we_n,
-           ddram_cs_n => ddram_cs_n,
-           ddram_dm => ddram_dm,
-           ddram_dq => ddram_dq,
-           ddram_dqs_p => ddram_dqs_p,
-           ddram_dqs_n => ddram_dqs_n,
-           ddram_clk_p => ddram_clk_p,
-           ddram_clk_n => ddram_clk_n,
-           ddram_cke => ddram_cke,
-           ddram_odt => ddram_odt,
-           ddram_reset_n => ddram_reset_n,
-           init_done => init_done,
-           init_error => init_error,
-           user_clk => system_clk,
-           user_rst => system_reset,
-            wb_ctrl_adr => wb_ctrl_adr,
-            wb_ctrl_dat_w => wb_ctrl_dat_w,
-            wb_ctrl_dat_r => wb_ctrl_dat_r,
-            wb_ctrl_sel => wb_ctrl_sel,
-            wb_ctrl_cyc => wb_ctrl_cyc,
-            wb_ctrl_stb => wb_ctrl_stb,
-            wb_ctrl_ack => wb_ctrl_ack,
-            wb_ctrl_we => wb_ctrl_we,
-            wb_ctrl_cti => "000",
-            wb_ctrl_bte => "00",
-            wb_ctrl_err => open,
-           user_port_native_0_cmd_valid => user_port0_cmd_valid,
-           user_port_native_0_cmd_ready => user_port0_cmd_ready,
-           user_port_native_0_cmd_we => user_port0_cmd_we,
-           user_port_native_0_cmd_addr => user_port0_cmd_addr,
-           user_port_native_0_wdata_valid => user_port0_wdata_valid,
-           user_port_native_0_wdata_ready => user_port0_wdata_ready,
-           user_port_native_0_wdata_we => user_port0_wdata_we,
-           user_port_native_0_wdata_data => user_port0_wdata_data,
-           user_port_native_0_rdata_valid => user_port0_rdata_valid,
-           user_port_native_0_rdata_ready => user_port0_rdata_ready,
-           user_port_native_0_rdata_data => user_port0_rdata_data
-           );
-
-end architecture behaviour;

diff --git a/litedram/gen-src/wrapper-self-init.vhdl b/litedram/gen-src/wrapper-self-init.vhdl
deleted file mode 100644 (file)
index d57c99b..0000000
--- a/litedram/gen-src/wrapper-self-init.vhdl
+++ /dev/null
@@ -1,225 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use std.textio.all;
-
-library work;
-use work.wishbone_types.all;
-
-entity litedram_wrapper is
-    generic (
-       DRAM_ABITS     : positive;
-       DRAM_ALINES    : positive
-       );
-    port(
-       -- LiteDRAM generates the system clock and reset
-       -- from the input clkin
-       clk_in          : in std_ulogic;
-       rst             : in std_ulogic;
-       system_clk      : out std_ulogic;
-       system_reset    : out std_ulogic;
-       core_alt_reset  : out std_ulogic;
-       pll_locked      : out std_ulogic;
-
-       -- Wishbone ports:
-       wb_in           : in wishbone_master_out;
-       wb_out          : out wishbone_slave_out;
-       wb_ctrl_in      : in wb_io_master_out;
-       wb_ctrl_out     : out wb_io_slave_out;
-       wb_ctrl_is_csr  : in std_ulogic;
-       wb_ctrl_is_init : in std_ulogic;
-
-       -- Init core serial debug
-       serial_tx     : out std_ulogic;
-       serial_rx     : in std_ulogic;
-
-       -- Misc
-       init_done     : out std_ulogic;
-       init_error    : out std_ulogic;
-
-       -- DRAM wires
-       ddram_a       : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-       ddram_ba      : out std_ulogic_vector(2 downto 0);
-       ddram_ras_n   : out std_ulogic;
-       ddram_cas_n   : out std_ulogic;
-       ddram_we_n    : out std_ulogic;
-       ddram_cs_n    : out std_ulogic;
-       ddram_dm      : out std_ulogic_vector(1 downto 0);
-       ddram_dq      : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
-       ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
-       ddram_clk_p   : out std_ulogic;
-       ddram_clk_n   : out std_ulogic;
-       ddram_cke     : out std_ulogic;
-       ddram_odt     : out std_ulogic;
-       ddram_reset_n : out std_ulogic
-end entity litedram_wrapper;
-
-architecture behaviour of litedram_wrapper is
-
-    component litedram_core port (
-       clk                    : in std_ulogic;
-       rst                    : in std_ulogic;
-       serial_tx              : out std_ulogic;
-       serial_rx              : in std_ulogic;
-       pll_locked             : out std_ulogic;
-       ddram_a                : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-       ddram_ba               : out std_ulogic_vector(2 downto 0);
-       ddram_ras_n            : out std_ulogic;
-       ddram_cas_n            : out std_ulogic;
-       ddram_we_n             : out std_ulogic;
-       ddram_cs_n             : out std_ulogic;
-       ddram_dm               : out std_ulogic_vector(1 downto 0);
-       ddram_dq               : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p            : inout std_ulogic_vector(1 downto 0);
-       ddram_dqs_n            : inout std_ulogic_vector(1 downto 0);
-       ddram_clk_p            : out std_ulogic;
-       ddram_clk_n            : out std_ulogic;
-       ddram_cke              : out std_ulogic;
-       ddram_odt              : out std_ulogic;
-       ddram_reset_n          : out std_ulogic;
-       init_done              : out std_ulogic;
-       init_error             : out std_ulogic;
-       user_clk               : out std_ulogic;
-       user_rst               : out std_ulogic;
-       user_port_native_0_cmd_valid   : in std_ulogic;
-       user_port_native_0_cmd_ready   : out std_ulogic;
-       user_port_native_0_cmd_we      : in std_ulogic;
-       user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
-       user_port_native_0_wdata_valid : in std_ulogic;
-       user_port_native_0_wdata_ready : out std_ulogic;
-       user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
-       user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
-       user_port_native_0_rdata_valid : out std_ulogic;
-       user_port_native_0_rdata_ready : in std_ulogic;
-       user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
-       );
-    end component;
-    
-    signal user_port0_cmd_valid                : std_ulogic;
-    signal user_port0_cmd_ready                : std_ulogic;
-    signal user_port0_cmd_we           : std_ulogic;
-    signal user_port0_cmd_addr         : std_ulogic_vector(DRAM_ABITS-1 downto 0);
-    signal user_port0_wdata_valid      : std_ulogic;
-    signal user_port0_wdata_ready      : std_ulogic;
-    signal user_port0_wdata_we         : std_ulogic_vector(15 downto 0);
-    signal user_port0_wdata_data       : std_ulogic_vector(127 downto 0);
-    signal user_port0_rdata_valid      : std_ulogic;
-    signal user_port0_rdata_ready      : std_ulogic;
-    signal user_port0_rdata_data       : std_ulogic_vector(127 downto 0);
-
-    signal ad3                          : std_ulogic;
-
-    signal dram_user_reset              : std_ulogic;
-
-    type state_t is (CMD, MWRITE, MREAD);
-    signal state : state_t;
-
-begin
-
-    -- Reset, lift it when init done, no alt core reset
-    system_reset <= dram_user_reset or not init_done;
-    core_alt_reset <= '0';
-
-    -- Control bus is unused
-    wb_ctrl_out.ack   <= (wb_is_ctrl = '1' or wb_is_init = '1') and wb_ctrl_in.cyc;
-                         else wb_init_out.ack;
-    wb_ctrl_out.dat   <= (others => '0');
-    wb_ctrl_out.stall <= '0';
-
-    --
-    -- Data bus wishbone to LiteDRAM native port
-    --
-    -- Address bit 3 selects the top or bottom half of the data
-    -- bus (64-bit wishbone vs. 128-bit DRAM interface)
-    --
-    -- XXX TODO: Figure out how to pipeline this
-    --
-    ad3 <= wb_in.adr(3);
-
-    -- Wishbone port IN signals
-    user_port0_cmd_valid   <= wb_in.cyc and wb_in.stb when state = CMD else '0';
-    user_port0_cmd_we      <= wb_in.we when state = CMD else '0';
-    user_port0_wdata_valid <= '1' when state = MWRITE else '0';
-    user_port0_rdata_ready <= '1' when state = MREAD else '0';
-    user_port0_cmd_addr    <= wb_in.adr(DRAM_ABITS+3 downto 4);
-    user_port0_wdata_data  <= wb_in.dat & wb_in.dat;
-    user_port0_wdata_we    <= wb_in.sel & "00000000" when ad3 = '1' else
-                              "00000000" & wb_in.sel;
-
-    -- Wishbone OUT signals
-    wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
-                 user_port0_rdata_valid when state = MREAD else '0';
-
-    wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
-                 user_port0_rdata_data(63 downto 0);
-
-    -- We don't do pipelining yet.
-    wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
-
-    -- DRAM user port State machine
-    sm: process(system_clk)
-    begin
-       
-       if rising_edge(system_clk) then
-           if dram_user_reset = '1' then
-               state <= CMD;
-           else
-               case state is
-               when CMD =>
-                   if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
-                       state <= MWRITE when wb_in.we = '1' else MREAD;
-                   end if;
-               when MWRITE =>
-                   if user_port0_wdata_ready = '1' then
-                       state <= CMD;
-                   end if;
-               when MREAD =>
-                   if user_port0_rdata_valid = '1' then
-                       state <= CMD;
-                   end if;
-               end case;
-           end if;
-       end if;
-    end process;
-
-    litedram: litedram_core
-       port map(
-           clk => clk_in,
-           rst => rst,
-           serial_tx => serial_tx,
-           serial_rx => serial_rx,
-           pll_locked => pll_locked,
-           ddram_a => ddram_a,
-           ddram_ba => ddram_ba,
-           ddram_ras_n => ddram_ras_n,
-           ddram_cas_n => ddram_cas_n,
-           ddram_we_n => ddram_we_n,
-           ddram_cs_n => ddram_cs_n,
-           ddram_dm => ddram_dm,
-           ddram_dq => ddram_dq,
-           ddram_dqs_p => ddram_dqs_p,
-           ddram_dqs_n => ddram_dqs_n,
-           ddram_clk_p => ddram_clk_p,
-           ddram_clk_n => ddram_clk_n,
-           ddram_cke => ddram_cke,
-           ddram_odt => ddram_odt,
-           ddram_reset_n => ddram_reset_n,
-           init_done => init_done,
-           init_error => init_error,
-           user_clk => system_clk,
-           user_rst => dram_user_reset,
-           user_port_native_0_cmd_valid => user_port0_cmd_valid,
-           user_port_native_0_cmd_ready => user_port0_cmd_ready,
-           user_port_native_0_cmd_we => user_port0_cmd_we,
-           user_port_native_0_cmd_addr => user_port0_cmd_addr,
-           user_port_native_0_wdata_valid => user_port0_wdata_valid,
-           user_port_native_0_wdata_ready => user_port0_wdata_ready,
-           user_port_native_0_wdata_we => user_port0_wdata_we,
-           user_port_native_0_wdata_data => user_port0_wdata_data,
-           user_port_native_0_rdata_valid => user_port0_rdata_valid,
-           user_port_native_0_rdata_ready => user_port0_rdata_ready,
-           user_port_native_0_rdata_data => user_port0_rdata_data
-           );
-
-end architecture behaviour;

diff --git a/litedram/generated/arty/init-cpu.txt b/litedram/generated/arty/init-cpu.txt
new file mode 100644 (file)
index 0000000..c86c3f3
--- /dev/null
+++ b/litedram/generated/arty/init-cpu.txt
@@ -0,0 +1 @@
+none
\ No newline at end of file

diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl
deleted file mode 100644 (file)
index f12e3df..0000000
--- a/litedram/generated/arty/litedram-wrapper.vhdl
+++ /dev/null
@@ -1,284 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use std.textio.all;
-
-library work;
-use work.wishbone_types.all;
-
-entity litedram_wrapper is
-    generic (
-       DRAM_ABITS     : positive;
-       DRAM_ALINES    : positive
-       );
-    port(
-       -- LiteDRAM generates the system clock and reset
-       -- from the input clkin
-       clk_in          : in std_ulogic;
-       rst             : in std_ulogic;
-       system_clk      : out std_ulogic;
-       system_reset    : out std_ulogic;
-       core_alt_reset  : out std_ulogic;
-       pll_locked      : out std_ulogic;
-
-       -- Wishbone ports:
-       wb_in           : in wishbone_master_out;
-       wb_out          : out wishbone_slave_out;
-       wb_ctrl_in      : in wb_io_master_out;
-       wb_ctrl_out     : out wb_io_slave_out;
-       wb_ctrl_is_csr  : in std_ulogic;
-       wb_ctrl_is_init : in std_ulogic;
-
-       -- Init core serial debug
-       serial_tx     : out std_ulogic;
-       serial_rx     : in std_ulogic;
-
-       -- Misc
-       init_done     : out std_ulogic;
-       init_error    : out std_ulogic;
-
-       -- DRAM wires
-       ddram_a       : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-       ddram_ba      : out std_ulogic_vector(2 downto 0);
-       ddram_ras_n   : out std_ulogic;
-       ddram_cas_n   : out std_ulogic;
-       ddram_we_n    : out std_ulogic;
-       ddram_cs_n    : out std_ulogic;
-       ddram_dm      : out std_ulogic_vector(1 downto 0);
-       ddram_dq      : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
-       ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
-       ddram_clk_p   : out std_ulogic;
-       ddram_clk_n   : out std_ulogic;
-       ddram_cke     : out std_ulogic;
-       ddram_odt     : out std_ulogic;
-       ddram_reset_n : out std_ulogic
-       );
-end entity litedram_wrapper;
-
-architecture behaviour of litedram_wrapper is
-
-    component litedram_core port (
-       clk                            : in std_ulogic;
-       rst                            : in std_ulogic;
-       pll_locked                     : out std_ulogic;
-       ddram_a                        : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-       ddram_ba                       : out std_ulogic_vector(2 downto 0);
-       ddram_ras_n                    : out std_ulogic;
-       ddram_cas_n                    : out std_ulogic;
-       ddram_we_n                     : out std_ulogic;
-       ddram_cs_n                     : out std_ulogic;
-       ddram_dm                       : out std_ulogic_vector(1 downto 0);
-       ddram_dq                       : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
-       ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
-       ddram_clk_p                    : out std_ulogic;
-       ddram_clk_n                    : out std_ulogic;
-       ddram_cke                      : out std_ulogic;
-       ddram_odt                      : out std_ulogic;
-       ddram_reset_n                  : out std_ulogic;
-       init_done                      : out std_ulogic;
-       init_error                     : out std_ulogic;
-       user_clk                       : out std_ulogic;
-       user_rst                       : out std_ulogic;
-       wb_ctrl_adr                    : in std_ulogic_vector(29 downto 0);
-       wb_ctrl_dat_w                  : in std_ulogic_vector(31 downto 0);
-       wb_ctrl_dat_r                  : out std_ulogic_vector(31 downto 0);
-       wb_ctrl_sel                    : in std_ulogic_vector(3 downto 0);
-       wb_ctrl_cyc                    : in std_ulogic;
-       wb_ctrl_stb                    : in std_ulogic;
-       wb_ctrl_ack                    : out std_ulogic;
-       wb_ctrl_we                     : in std_ulogic;
-       wb_ctrl_cti                    : in std_ulogic_vector(2 downto 0);
-       wb_ctrl_bte                    : in std_ulogic_vector(1 downto 0);
-       wb_ctrl_err                    : out std_ulogic;
-       user_port_native_0_cmd_valid   : in std_ulogic;
-       user_port_native_0_cmd_ready   : out std_ulogic;
-       user_port_native_0_cmd_we      : in std_ulogic;
-       user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
-       user_port_native_0_wdata_valid : in std_ulogic;
-       user_port_native_0_wdata_ready : out std_ulogic;
-       user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
-       user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
-       user_port_native_0_rdata_valid : out std_ulogic;
-       user_port_native_0_rdata_ready : in std_ulogic;
-       user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
-       );
-    end component;
-    
-    signal user_port0_cmd_valid                : std_ulogic;
-    signal user_port0_cmd_ready                : std_ulogic;
-    signal user_port0_cmd_we           : std_ulogic;
-    signal user_port0_cmd_addr         : std_ulogic_vector(DRAM_ABITS-1 downto 0);
-    signal user_port0_wdata_valid      : std_ulogic;
-    signal user_port0_wdata_ready      : std_ulogic;
-    signal user_port0_wdata_we         : std_ulogic_vector(15 downto 0);
-    signal user_port0_wdata_data       : std_ulogic_vector(127 downto 0);
-    signal user_port0_rdata_valid      : std_ulogic;
-    signal user_port0_rdata_ready      : std_ulogic;
-    signal user_port0_rdata_data       : std_ulogic_vector(127 downto 0);
-
-    signal ad3                          : std_ulogic;
-
-    signal wb_ctrl_adr                  : std_ulogic_vector(29 downto 0);
-    signal wb_ctrl_dat_w                : std_ulogic_vector(31 downto 0);
-    signal wb_ctrl_dat_r                : std_ulogic_vector(31 downto 0);
-    signal wb_ctrl_sel                  : std_ulogic_vector(3 downto 0);
-    signal wb_ctrl_cyc                  : std_ulogic;
-    signal wb_ctrl_stb                  : std_ulogic;
-    signal wb_ctrl_ack                  : std_ulogic;
-    signal wb_ctrl_we                   : std_ulogic;
-
-    signal wb_init_in                   : wb_io_master_out;
-    signal wb_init_out                  : wb_io_slave_out;
-
-    type state_t is (CMD, MWRITE, MREAD);
-    signal state : state_t;
-
-begin
-
-    -- alternate core reset address set when DRAM is not initialized.
-    core_alt_reset <= not init_done;
-
-    -- Init code BRAM memory slave 
-    init_ram_0: entity work.dram_init_mem
-        port map(
-            clk => system_clk,
-            wb_in => wb_init_in,
-            wb_out => wb_init_out
-            );
-
-    --
-    -- Control bus wishbone: This muxes the wishbone to the CSRs
-    -- and an internal small one to the init BRAM
-    --
-
-    -- Init DRAM wishbone IN signals
-    wb_init_in.adr <= wb_ctrl_in.adr;
-    wb_init_in.dat <= wb_ctrl_in.dat;
-    wb_init_in.sel <= wb_ctrl_in.sel;
-    wb_init_in.we  <= wb_ctrl_in.we;
-    wb_init_in.stb <= wb_ctrl_in.stb;
-    wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init;
-
-    -- DRAM CSR IN signals
-    wb_ctrl_adr   <= x"0000" & wb_ctrl_in.adr(15 downto 2);
-    wb_ctrl_dat_w <= wb_ctrl_in.dat;
-    wb_ctrl_sel   <= wb_ctrl_in.sel;
-    wb_ctrl_we    <= wb_ctrl_in.we;
-    wb_ctrl_cyc   <= wb_ctrl_in.cyc and wb_ctrl_is_csr;
-    wb_ctrl_stb   <= wb_ctrl_in.stb and wb_ctrl_is_csr;
-
-    -- Ctrl bus wishbone OUT signals
-    wb_ctrl_out.ack   <= wb_ctrl_ack when wb_ctrl_is_csr = '1'
-                         else wb_init_out.ack;
-    wb_ctrl_out.dat   <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1'
-                         else wb_init_out.dat;
-    wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else
-                         '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack;
-
-    --
-    -- Data bus wishbone to LiteDRAM native port
-    --
-    -- Address bit 3 selects the top or bottom half of the data
-    -- bus (64-bit wishbone vs. 128-bit DRAM interface)
-    --
-    -- XXX TODO: Figure out how to pipeline this
-    --
-    ad3 <= wb_in.adr(3);
-
-    -- Wishbone port IN signals
-    user_port0_cmd_valid   <= wb_in.cyc and wb_in.stb when state = CMD else '0';
-    user_port0_cmd_we      <= wb_in.we when state = CMD else '0';
-    user_port0_wdata_valid <= '1' when state = MWRITE else '0';
-    user_port0_rdata_ready <= '1' when state = MREAD else '0';
-    user_port0_cmd_addr    <= wb_in.adr(DRAM_ABITS+3 downto 4);
-    user_port0_wdata_data  <= wb_in.dat & wb_in.dat;
-    user_port0_wdata_we    <= wb_in.sel & "00000000" when ad3 = '1' else
-                              "00000000" & wb_in.sel;
-
-    -- Wishbone OUT signals
-    wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
-                 user_port0_rdata_valid when state = MREAD else '0';
-
-    wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
-                 user_port0_rdata_data(63 downto 0);
-
-    -- We don't do pipelining yet.
-    wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
-
-    -- DRAM user port State machine
-    sm: process(system_clk)
-    begin
-       
-       if rising_edge(system_clk) then
-           if system_reset = '1' then
-               state <= CMD;
-           else
-               case state is
-               when CMD =>
-                    if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
-                       state <= MWRITE when wb_in.we = '1' else MREAD;
-                   end if;
-               when MWRITE =>
-                   if user_port0_wdata_ready = '1' then
-                       state <= CMD;
-                   end if;
-               when MREAD =>
-                   if user_port0_rdata_valid = '1' then
-                       state <= CMD;
-                   end if;
-                end case;
-           end if;
-       end if;
-    end process;
-
-    litedram: litedram_core
-       port map(
-           clk => clk_in,
-           rst => rst,
-           pll_locked => pll_locked,
-           ddram_a => ddram_a,
-           ddram_ba => ddram_ba,
-           ddram_ras_n => ddram_ras_n,
-           ddram_cas_n => ddram_cas_n,
-           ddram_we_n => ddram_we_n,
-           ddram_cs_n => ddram_cs_n,
-           ddram_dm => ddram_dm,
-           ddram_dq => ddram_dq,
-           ddram_dqs_p => ddram_dqs_p,
-           ddram_dqs_n => ddram_dqs_n,
-           ddram_clk_p => ddram_clk_p,
-           ddram_clk_n => ddram_clk_n,
-           ddram_cke => ddram_cke,
-           ddram_odt => ddram_odt,
-           ddram_reset_n => ddram_reset_n,
-           init_done => init_done,
-           init_error => init_error,
-           user_clk => system_clk,
-           user_rst => system_reset,
-            wb_ctrl_adr => wb_ctrl_adr,
-            wb_ctrl_dat_w => wb_ctrl_dat_w,
-            wb_ctrl_dat_r => wb_ctrl_dat_r,
-            wb_ctrl_sel => wb_ctrl_sel,
-            wb_ctrl_cyc => wb_ctrl_cyc,
-            wb_ctrl_stb => wb_ctrl_stb,
-            wb_ctrl_ack => wb_ctrl_ack,
-            wb_ctrl_we => wb_ctrl_we,
-            wb_ctrl_cti => "000",
-            wb_ctrl_bte => "00",
-            wb_ctrl_err => open,
-           user_port_native_0_cmd_valid => user_port0_cmd_valid,
-           user_port_native_0_cmd_ready => user_port0_cmd_ready,
-           user_port_native_0_cmd_we => user_port0_cmd_we,
-           user_port_native_0_cmd_addr => user_port0_cmd_addr,
-           user_port_native_0_wdata_valid => user_port0_wdata_valid,
-           user_port_native_0_wdata_ready => user_port0_wdata_ready,
-           user_port_native_0_wdata_we => user_port0_wdata_we,
-           user_port_native_0_wdata_data => user_port0_wdata_data,
-           user_port_native_0_rdata_valid => user_port0_rdata_valid,
-           user_port_native_0_rdata_ready => user_port0_rdata_ready,
-           user_port_native_0_rdata_data => user_port0_rdata_data
-           );
-
-end architecture behaviour;

diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init
index 22485ac0736cd820be61cd27ced17d0890abd4ca..3c81a1a4b0f4cb11716a8a90abfe598546dfe75d 100644 (file)
--- a/litedram/generated/arty/litedram_core.init
+++ b/litedram/generated/arty/litedram_core.init
@@ -1443,7 +1443,7 @@ e8010010ebc1fff0
 203a4b4c43202020
 7a484d20646c6c25
 000000000000000a
-6138393331393333
+6131333764343635
 0000000000000000
 0033306536316430
 4d4152446574694c

diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v
index 48dc091fd98998d7d66589c337f8a23980c1834b..6cb2c1e9a2aa114e1c435957b316e435f3332603 100644 (file)
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-21 19:21:27
+// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-22 17:57:16
 //--------------------------------------------------------------------------------
 module litedram_core(
        input wire clk,

diff --git a/litedram/generated/nexys-video/init-cpu.txt b/litedram/generated/nexys-video/init-cpu.txt
new file mode 100644 (file)
index 0000000..c86c3f3
--- /dev/null
+++ b/litedram/generated/nexys-video/init-cpu.txt
@@ -0,0 +1 @@
+none
\ No newline at end of file

diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl
deleted file mode 100644 (file)
index f12e3df..0000000
--- a/litedram/generated/nexys-video/litedram-wrapper.vhdl
+++ /dev/null
@@ -1,284 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use std.textio.all;
-
-library work;
-use work.wishbone_types.all;
-
-entity litedram_wrapper is
-    generic (
-       DRAM_ABITS     : positive;
-       DRAM_ALINES    : positive
-       );
-    port(
-       -- LiteDRAM generates the system clock and reset
-       -- from the input clkin
-       clk_in          : in std_ulogic;
-       rst             : in std_ulogic;
-       system_clk      : out std_ulogic;
-       system_reset    : out std_ulogic;
-       core_alt_reset  : out std_ulogic;
-       pll_locked      : out std_ulogic;
-
-       -- Wishbone ports:
-       wb_in           : in wishbone_master_out;
-       wb_out          : out wishbone_slave_out;
-       wb_ctrl_in      : in wb_io_master_out;
-       wb_ctrl_out     : out wb_io_slave_out;
-       wb_ctrl_is_csr  : in std_ulogic;
-       wb_ctrl_is_init : in std_ulogic;
-
-       -- Init core serial debug
-       serial_tx     : out std_ulogic;
-       serial_rx     : in std_ulogic;
-
-       -- Misc
-       init_done     : out std_ulogic;
-       init_error    : out std_ulogic;
-
-       -- DRAM wires
-       ddram_a       : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-       ddram_ba      : out std_ulogic_vector(2 downto 0);
-       ddram_ras_n   : out std_ulogic;
-       ddram_cas_n   : out std_ulogic;
-       ddram_we_n    : out std_ulogic;
-       ddram_cs_n    : out std_ulogic;
-       ddram_dm      : out std_ulogic_vector(1 downto 0);
-       ddram_dq      : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
-       ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
-       ddram_clk_p   : out std_ulogic;
-       ddram_clk_n   : out std_ulogic;
-       ddram_cke     : out std_ulogic;
-       ddram_odt     : out std_ulogic;
-       ddram_reset_n : out std_ulogic
-       );
-end entity litedram_wrapper;
-
-architecture behaviour of litedram_wrapper is
-
-    component litedram_core port (
-       clk                            : in std_ulogic;
-       rst                            : in std_ulogic;
-       pll_locked                     : out std_ulogic;
-       ddram_a                        : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
-       ddram_ba                       : out std_ulogic_vector(2 downto 0);
-       ddram_ras_n                    : out std_ulogic;
-       ddram_cas_n                    : out std_ulogic;
-       ddram_we_n                     : out std_ulogic;
-       ddram_cs_n                     : out std_ulogic;
-       ddram_dm                       : out std_ulogic_vector(1 downto 0);
-       ddram_dq                       : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p                    : inout std_ulogic_vector(1 downto 0);
-       ddram_dqs_n                    : inout std_ulogic_vector(1 downto 0);
-       ddram_clk_p                    : out std_ulogic;
-       ddram_clk_n                    : out std_ulogic;
-       ddram_cke                      : out std_ulogic;
-       ddram_odt                      : out std_ulogic;
-       ddram_reset_n                  : out std_ulogic;
-       init_done                      : out std_ulogic;
-       init_error                     : out std_ulogic;
-       user_clk                       : out std_ulogic;
-       user_rst                       : out std_ulogic;
-       wb_ctrl_adr                    : in std_ulogic_vector(29 downto 0);
-       wb_ctrl_dat_w                  : in std_ulogic_vector(31 downto 0);
-       wb_ctrl_dat_r                  : out std_ulogic_vector(31 downto 0);
-       wb_ctrl_sel                    : in std_ulogic_vector(3 downto 0);
-       wb_ctrl_cyc                    : in std_ulogic;
-       wb_ctrl_stb                    : in std_ulogic;
-       wb_ctrl_ack                    : out std_ulogic;
-       wb_ctrl_we                     : in std_ulogic;
-       wb_ctrl_cti                    : in std_ulogic_vector(2 downto 0);
-       wb_ctrl_bte                    : in std_ulogic_vector(1 downto 0);
-       wb_ctrl_err                    : out std_ulogic;
-       user_port_native_0_cmd_valid   : in std_ulogic;
-       user_port_native_0_cmd_ready   : out std_ulogic;
-       user_port_native_0_cmd_we      : in std_ulogic;
-       user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
-       user_port_native_0_wdata_valid : in std_ulogic;
-       user_port_native_0_wdata_ready : out std_ulogic;
-       user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
-       user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
-       user_port_native_0_rdata_valid : out std_ulogic;
-       user_port_native_0_rdata_ready : in std_ulogic;
-       user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
-       );
-    end component;
-    
-    signal user_port0_cmd_valid                : std_ulogic;
-    signal user_port0_cmd_ready                : std_ulogic;
-    signal user_port0_cmd_we           : std_ulogic;
-    signal user_port0_cmd_addr         : std_ulogic_vector(DRAM_ABITS-1 downto 0);
-    signal user_port0_wdata_valid      : std_ulogic;
-    signal user_port0_wdata_ready      : std_ulogic;
-    signal user_port0_wdata_we         : std_ulogic_vector(15 downto 0);
-    signal user_port0_wdata_data       : std_ulogic_vector(127 downto 0);
-    signal user_port0_rdata_valid      : std_ulogic;
-    signal user_port0_rdata_ready      : std_ulogic;
-    signal user_port0_rdata_data       : std_ulogic_vector(127 downto 0);
-
-    signal ad3                          : std_ulogic;
-
-    signal wb_ctrl_adr                  : std_ulogic_vector(29 downto 0);
-    signal wb_ctrl_dat_w                : std_ulogic_vector(31 downto 0);
-    signal wb_ctrl_dat_r                : std_ulogic_vector(31 downto 0);
-    signal wb_ctrl_sel                  : std_ulogic_vector(3 downto 0);
-    signal wb_ctrl_cyc                  : std_ulogic;
-    signal wb_ctrl_stb                  : std_ulogic;
-    signal wb_ctrl_ack                  : std_ulogic;
-    signal wb_ctrl_we                   : std_ulogic;
-
-    signal wb_init_in                   : wb_io_master_out;
-    signal wb_init_out                  : wb_io_slave_out;
-
-    type state_t is (CMD, MWRITE, MREAD);
-    signal state : state_t;
-
-begin
-
-    -- alternate core reset address set when DRAM is not initialized.
-    core_alt_reset <= not init_done;
-
-    -- Init code BRAM memory slave 
-    init_ram_0: entity work.dram_init_mem
-        port map(
-            clk => system_clk,
-            wb_in => wb_init_in,
-            wb_out => wb_init_out
-            );
-
-    --
-    -- Control bus wishbone: This muxes the wishbone to the CSRs
-    -- and an internal small one to the init BRAM
-    --
-
-    -- Init DRAM wishbone IN signals
-    wb_init_in.adr <= wb_ctrl_in.adr;
-    wb_init_in.dat <= wb_ctrl_in.dat;
-    wb_init_in.sel <= wb_ctrl_in.sel;
-    wb_init_in.we  <= wb_ctrl_in.we;
-    wb_init_in.stb <= wb_ctrl_in.stb;
-    wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init;
-
-    -- DRAM CSR IN signals
-    wb_ctrl_adr   <= x"0000" & wb_ctrl_in.adr(15 downto 2);
-    wb_ctrl_dat_w <= wb_ctrl_in.dat;
-    wb_ctrl_sel   <= wb_ctrl_in.sel;
-    wb_ctrl_we    <= wb_ctrl_in.we;
-    wb_ctrl_cyc   <= wb_ctrl_in.cyc and wb_ctrl_is_csr;
-    wb_ctrl_stb   <= wb_ctrl_in.stb and wb_ctrl_is_csr;
-
-    -- Ctrl bus wishbone OUT signals
-    wb_ctrl_out.ack   <= wb_ctrl_ack when wb_ctrl_is_csr = '1'
-                         else wb_init_out.ack;
-    wb_ctrl_out.dat   <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1'
-                         else wb_init_out.dat;
-    wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else
-                         '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack;
-
-    --
-    -- Data bus wishbone to LiteDRAM native port
-    --
-    -- Address bit 3 selects the top or bottom half of the data
-    -- bus (64-bit wishbone vs. 128-bit DRAM interface)
-    --
-    -- XXX TODO: Figure out how to pipeline this
-    --
-    ad3 <= wb_in.adr(3);
-
-    -- Wishbone port IN signals
-    user_port0_cmd_valid   <= wb_in.cyc and wb_in.stb when state = CMD else '0';
-    user_port0_cmd_we      <= wb_in.we when state = CMD else '0';
-    user_port0_wdata_valid <= '1' when state = MWRITE else '0';
-    user_port0_rdata_ready <= '1' when state = MREAD else '0';
-    user_port0_cmd_addr    <= wb_in.adr(DRAM_ABITS+3 downto 4);
-    user_port0_wdata_data  <= wb_in.dat & wb_in.dat;
-    user_port0_wdata_we    <= wb_in.sel & "00000000" when ad3 = '1' else
-                              "00000000" & wb_in.sel;
-
-    -- Wishbone OUT signals
-    wb_out.ack <= user_port0_wdata_ready when state = MWRITE else
-                 user_port0_rdata_valid when state = MREAD else '0';
-
-    wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else
-                 user_port0_rdata_data(63 downto 0);
-
-    -- We don't do pipelining yet.
-    wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
-
-    -- DRAM user port State machine
-    sm: process(system_clk)
-    begin
-       
-       if rising_edge(system_clk) then
-           if system_reset = '1' then
-               state <= CMD;
-           else
-               case state is
-               when CMD =>
-                    if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
-                       state <= MWRITE when wb_in.we = '1' else MREAD;
-                   end if;
-               when MWRITE =>
-                   if user_port0_wdata_ready = '1' then
-                       state <= CMD;
-                   end if;
-               when MREAD =>
-                   if user_port0_rdata_valid = '1' then
-                       state <= CMD;
-                   end if;
-                end case;
-           end if;
-       end if;
-    end process;
-
-    litedram: litedram_core
-       port map(
-           clk => clk_in,
-           rst => rst,
-           pll_locked => pll_locked,
-           ddram_a => ddram_a,
-           ddram_ba => ddram_ba,
-           ddram_ras_n => ddram_ras_n,
-           ddram_cas_n => ddram_cas_n,
-           ddram_we_n => ddram_we_n,
-           ddram_cs_n => ddram_cs_n,
-           ddram_dm => ddram_dm,
-           ddram_dq => ddram_dq,
-           ddram_dqs_p => ddram_dqs_p,
-           ddram_dqs_n => ddram_dqs_n,
-           ddram_clk_p => ddram_clk_p,
-           ddram_clk_n => ddram_clk_n,
-           ddram_cke => ddram_cke,
-           ddram_odt => ddram_odt,
-           ddram_reset_n => ddram_reset_n,
-           init_done => init_done,
-           init_error => init_error,
-           user_clk => system_clk,
-           user_rst => system_reset,
-            wb_ctrl_adr => wb_ctrl_adr,
-            wb_ctrl_dat_w => wb_ctrl_dat_w,
-            wb_ctrl_dat_r => wb_ctrl_dat_r,
-            wb_ctrl_sel => wb_ctrl_sel,
-            wb_ctrl_cyc => wb_ctrl_cyc,
-            wb_ctrl_stb => wb_ctrl_stb,
-            wb_ctrl_ack => wb_ctrl_ack,
-            wb_ctrl_we => wb_ctrl_we,
-            wb_ctrl_cti => "000",
-            wb_ctrl_bte => "00",
-            wb_ctrl_err => open,
-           user_port_native_0_cmd_valid => user_port0_cmd_valid,
-           user_port_native_0_cmd_ready => user_port0_cmd_ready,
-           user_port_native_0_cmd_we => user_port0_cmd_we,
-           user_port_native_0_cmd_addr => user_port0_cmd_addr,
-           user_port_native_0_wdata_valid => user_port0_wdata_valid,
-           user_port_native_0_wdata_ready => user_port0_wdata_ready,
-           user_port_native_0_wdata_we => user_port0_wdata_we,
-           user_port_native_0_wdata_data => user_port0_wdata_data,
-           user_port_native_0_rdata_valid => user_port0_rdata_valid,
-           user_port_native_0_rdata_ready => user_port0_rdata_ready,
-           user_port_native_0_rdata_data => user_port0_rdata_data
-           );
-
-end architecture behaviour;

diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init
index 22485ac0736cd820be61cd27ced17d0890abd4ca..3c81a1a4b0f4cb11716a8a90abfe598546dfe75d 100644 (file)
--- a/litedram/generated/nexys-video/litedram_core.init
+++ b/litedram/generated/nexys-video/litedram_core.init
@@ -1443,7 +1443,7 @@ e8010010ebc1fff0
 203a4b4c43202020
 7a484d20646c6c25
 000000000000000a
-6138393331393333
+6131333764343635
 0000000000000000
 0033306536316430
 4d4152446574694c

diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v
index 5a34a367cc0134d13b56770b2c43778df8fb38e3..23640678148476b41fc01335acf716871d1156d8 100644 (file)
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-21 19:21:29
+// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-22 17:57:18
 //--------------------------------------------------------------------------------
 module litedram_core(
        input wire clk,

diff --git a/litedram/generated/sim/init-cpu.txt b/litedram/generated/sim/init-cpu.txt
new file mode 100644 (file)
index 0000000..c86c3f3
--- /dev/null
+++ b/litedram/generated/sim/init-cpu.txt
@@ -0,0 +1 @@
+none
\ No newline at end of file

diff --git a/litedram/generated/sim/litedram-initmem.vhdl b/litedram/generated/sim/litedram-initmem.vhdl
new file mode 100644 (file)
index 0000000..614f19b
--- /dev/null
+++ b/litedram/generated/sim/litedram-initmem.vhdl
@@ -0,0 +1,72 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity dram_init_mem is
+    port (
+        clk     : in std_ulogic;
+        wb_in  : in wb_io_master_out;
+        wb_out : out wb_io_slave_out
+      );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+    constant INIT_RAM_SIZE : integer := 16384;
+    constant INIT_RAM_ABITS :integer := 14;
+    constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init";
+
+    type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
+
+    impure function init_load_ram(name : string) return ram_t is
+       file ram_file : text open read_mode is name;
+       variable temp_word : std_logic_vector(63 downto 0);
+       variable temp_ram : ram_t := (others => (others => '0'));
+       variable ram_line : line;
+    begin
+       for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+           exit when endfile(ram_file);
+           readline(ram_file, ram_line);
+           hread(ram_line, temp_word);
+           temp_ram(i*2) := temp_word(31 downto 0);
+           temp_ram(i*2+1) := temp_word(63 downto 32);
+       end loop;
+       return temp_ram;
+    end function;
+
+    signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
+
+    attribute ram_style : string;
+    attribute ram_style of init_ram: signal is "block";
+
+begin
+
+    init_ram_0: process(clk)
+       variable adr : integer;
+    begin
+       if rising_edge(clk) then
+           wb_out.ack <= '0';
+           if (wb_in.cyc and wb_in.stb) = '1' then
+               adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+               if wb_in.we = '0' then
+                   wb_out.dat <= init_ram(adr);
+               else
+                   for i in 0 to 3 loop
+                       if wb_in.sel(i) = '1' then
+                           init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+                               wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
+                       end if;
+                   end loop;
+               end if;
+               wb_out.ack <= '1';
+           end if;
+       end if;
+    end process;
+
+    wb_out.stall <= '0';
+
+end architecture rtl;

diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init
new file mode 100644 (file)
index 0000000..11e61fa
--- /dev/null
+++ b/litedram/generated/sim/litedram_core.init
@@ -0,0 +1,1191 @@
+4800002408000048
+01006b69a600607d
+a602487d05009f42
+a64b5a7d14004a39
+2402004ca64b7b7d
+602100003c200000
+6421f000782107c6
+3d80000060213f00
+798c07c6618c0000
+618c108c658cf000
+4e8004217d8903a6
+0000000048000002
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000048000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+0000000000000000
+384295003c4c0001
+fbc1fff07c0802a6
+f8010010fbe1fff8
+3be10020f821fe91
+f8a101a0f8810198
+f8c101a838800140
+38c101987c651b78
+7fe3fb78f8e101b0
+f92101c0f90101b8
+48000c89f94101c8
+7c7e1b7860000000
+4800080d7fe3fb78
+3821017060000000
+480012487fc3f378
+0100000000000000
+4e80002000000280
+0000000000000000
+3c4c000100000000
+7c0802a638429474
+7d908026fbe1fff8
+f801001091810008
+48000719f821ff91
+3c62ffff60000000
+4bffff4d38637dc8
+548400023880ffff
+7c8026ea7c0004ac
+3fe0c0003c62ffff
+63ff000838637de8
+3c62ffff4bffff29
+38637e087bff0020
+7c0004ac4bffff19
+73e900017fe0feea
+3c62ffff41820010
+4bfffefd38637e20
+4e00000073e90002
+3c62ffff41820010
+4bfffee538637e28
+3bff7fc83fe2ffff
+4bfffed57fe3fb78
+608400103c80c000
+7c0004ac78840020
+3c62ffff7c8026ea
+38637e307884b282
+419200284bfffeb1
+608400183c80c000
+7c0004ac78840020
+3c62ffff7c8026ea
+38637e5078846502
+3d20c0004bfffe89
+7929002061290020
+7d204eea7c0004ac
+3c62ffff3c80000f
+38637e7060844240
+4bfffe5d7c892392
+4bfffe557fe3fb78
+3ca2ffff41920028
+3c62ffff3c82ffff
+38847ea038a57e90
+4bfffe3538637ea8
+6000000048000469
+38637ed83c62ffff
+382100704bfffe21
+7d90812081810008
+00000000480010c0
+0000018003000000
+612908083d20c010
+7c0004ac79290020
+3d40c0107c604f2a
+614a081039200001
+7c0004ac794a0020
+4e8000207d20572a
+0000000000000000
+3c4c000100000000
+7c0802a6384292bc
+614a08003d40c010
+794a002039200001
+f821ffa1f8010010
+7d20572a7c0004ac
+38637fa83c62ffff
+600000004bfffd91
+e801001038210060
+4e8000207c0803a6
+0100000000000000
+3c4c000100000080
+7c0802a638429264
+6129000c3d204000
+3fc0aaaa48000f91
+f821ff713f804000
+63deaaaa3fa04000
+639c00043fe04000
+93df000063bd0008
+93dd000093dc0000
+4bfffd9993c90000
+813f000060000000
+7d29f278815c0000
+7d2900347f8af000
+692900015529d97e
+7fff07b43be90001
+7d3f07b4409e0008
+7f89f000813d0000
+3bff0001419e000c
+3d2040007fff07b4
+812900006129000c
+2f8aaaaa6d2a5555
+3bff0001419e000c
+3fc055557fff07b4
+3d2040003fa04000
+3f80400063de5555
+63bd000461290008
+93dd000093dc0000
+3d20400093c90000
+93c900006129000c
+600000004bfffcfd
+7f89f000813c0000
+3bff0001419e000c
+813d00007fff07b4
+2f8a55556d2a5555
+3bff0001419e000c
+3d2040007fff07b4
+8129000061290008
+2f8a55556d2a5555
+3bff0001419e000c
+3d2040007fff07b4
+812900006129000c
+2f8a55556d2a5555
+3bff0001419e0028
+3c62ffff7fff07b4
+7fe4fb7838a00100
+4bfffc0538637ef0
+4800000c60000000
+409effe02fbf0000
+3ce0802039000004
+60e700037d0903a6
+392000013d404000
+7928f84278e70020
+7d2900d0792907e0
+7d293838394a0004
+912afffc7d294278
+4bfffc294200ffe4
+3900000460000000
+7d0903a63ce08020
+3d40400060e70003
+392000013bc00000
+7928f84278e70020
+7d2900d0792907e0
+7d2942787d293838
+7f884840810a0000
+3bde0001419e000c
+394a00047fde07b4
+2fbe00004200ffd4
+3c62ffff419e001c
+7fc4f37838a00004
+4bfffb4538637f18
+3d20400060000000
+6129000839400000
+914900003ba00000
+394000013d204000
+914900006129000c
+394000023d204000
+9149000061290010
+394000033d204000
+9149000061290014
+600000004bfffb6d
+3940000039200004
+3d2a10007d2903a6
+8129000879291764
+7f8950005529043e
+3bbd0001419e000c
+394a00017fbd07b4
+2fbd00004200ffdc
+3c62ffff419e001c
+7fa4eb7838a00004
+4bfffaa538637f40
+7ffefa1460000000
+7fffea143bc00000
+409e00a42f9f0000
+38637f683c62ffff
+600000004bfffa81
+3f8040007f5602a6
+639c00043f604000
+3fa0400039200001
+3fc0400093db0000
+63bd0008913c0000
+63de000c39200002
+39200003913d0000
+7ff602a6913e0000
+600000004bfffaad
+815b00007d3602a6
+815d0000815c0000
+7cb602a6815e0000
+7ca5485038803200
+7ca42b967d3fd050
+3c62ffff7c844b96
+788404a078a504a0
+3bc0000138637f78
+600000004bfff9f1
+7fc3f37838210090
+0000000048000c68
+0000068001000000
+38428ec83c4c0001
+3c62ffff7c0802a6
+48000bf538637fd0
+3f60c010f821ff71
+637b10003be00000
+4bfff9a57b7b0020
+7c0004ac60000000
+3f40c0107fe0df2a
+7b5a0020635a1008
+7fe0d72a7c0004ac
+63bd08183fa0c010
+7c0004ac7bbd0020
+3fc0c0107fe0ef2a
+7bde002063de0820
+7fe0f72a7c0004ac
+3940000c3d20c010
+7929002061290800
+7d404f2a7c0004ac
+7fe0ef2a7c0004ac
+7fe0f72a7c0004ac
+7c0004ac3940000e
+392002007d404f2a
+7d20ef2a7c0004ac
+7c0004ac39200002
+3860000f7d20f72a
+7c0004ac4bfffb09
+392000037fe0ef2a
+7d20f72a7c0004ac
+4bfffaed3860000f
+7c0004ac39200006
+3b8000017d20ef2a
+7f80f72a7c0004ac
+4bfffacd3860000f
+7c0004ac39200920
+7c0004ac7d20ef2a
+3860000f7fe0f72a
+392004004bfffab1
+7d20ef2a7c0004ac
+7fe0f72a7c0004ac
+4bfffa9538600003
+4bfffb294bfffad5
+4082001c2c230000
+7f80df2a7c0004ac
+7f80d72a7c0004ac
+48000af438210090
+7f80df2a7c0004ac
+4bffffec38600001
+0100000000000000
+3c4c000100000680
+3d20c00038428d44
+6129200060000000
+f922803879290020
+612900203d20c000
+7c0004ac79290020
+3d40001c7d204eea
+7d295392614a2000
+394a0018e9428038
+7c0004ac3929ffff
+4e8000207d2057ea
+0000000000000000
+3c4c000100000000
+6000000038428ce4
+39290010e9228038
+7d204eea7c0004ac
+4082ffe871290008
+e94280385469063e
+7d2057ea7c0004ac
+000000004e800020
+0000000000000000
+38428ca03c4c0001
+fbc1fff07c0802a6
+3bc3fffffbe1fff8
+f821ffd1f8010010
+2fbf00008ffe0001
+38210030409e0010
+48000a2038600000
+409e000c2b9f000a
+4bffff813860000d
+4bffff797fe3fb78
+000000004bffffd0
+0000028001000000
+408200082c240000
+2b8500243881fff0
+38600000f8640000
+3cc000014d9d0020
+60c6260078c683e4
+89490000e9240000
+419d002c2b8a0020
+70e800017cc75436
+2fa5000040820014
+38a0000a409e0054
+392900014800005c
+4bffffccf9240000
+409e00382fa50000
+38a0000a2b8a0030
+89490001409e003c
+409e00302f8a0078
+38a0001089490001
+409e00202f8a0078
+f924000039290002
+2f85001048000014
+2b8a0030409e000c
+38600000419effd8
+38c9ffd048000030
+2b8a000954ca063e
+7cc90734419d0034
+4c9c00207f892800
+7c6519d238e70001
+7c691a14f8e40000
+89270000e8e40000
+409effc82fa90000
+3949ff9f4e800020
+2b8a0019554a063e
+3929ffa9419d0010
+4bffffbc7d290734
+554a063e3949ffbf
+4d9d00202b8a0019
+4bffffe43929ffc9
+0000000000000000
+3920000000000000
+2f8a00007d4348ae
+7d234b78409e000c
+392900014e800020
+000000004bffffe8
+0000000000000000
+2b8900193923ff9f
+3863ffe04d9d0020
+4e8000207c6307b4
+0000000000000000
+3c4c000100000000
+7c0802a638428abc
+7d9080263d203736
+792907c661293534
+9181000865293332
+480007d961293130
+7c7d1b78f821ffa1
+3be000007cde3378
+3d206665f9210020
+792907c661296463
+6129393865296261
+7ca92b78f9210028
+409e00802fa90000
+409e00082fbf0000
+7fbf20403be00001
+419d005838600000
+3b9fffff2e270000
+7d3bf1d27f65f392
+7ca12a147ca92850
+4192001088650020
+600000004bffff41
+2fbb00005463063e
+7f65db78e93d0000
+3b9cffff7c69e1ae
+e93d0000409effc8
+7fe9fa1438600001
+38210060fbfd0000
+7d90812081810008
+2b9e001048000774
+7929e102409e0014
+7fff07b43bff0001
+7d29f3924bffff68
+000000004bfffff0
+0000058003000000
+384289b03c4c0001
+480006e97c0802a6
+eb630000f821ffb1
+7c9c23787c7f1b78
+3bc000007cbd2b78
+4bfffe797fa3eb78
+7fa3f04060000000
+e95f0000409d0014
+7fa9e0407d3b5050
+38210050419c0010
+480006f038600001
+3bde00017d3df0ae
+e93f0000992a0000
+f93f000039290001
+000000004bffffb8
+0000058001000000
+384289303c4c0001
+480006617c0802a6
+7c7d1b78f821ffa1
+7ca32b787c9b2378
+38a0000a38800000
+eb5d00007cde3378
+7d1943787cfc3b78
+4bfffcb57d3f4b78
+3940000060000000
+2fbe00007c6307b4
+2faa0000409e006c
+39400001409e0008
+7f8348007d3f5214
+409d00447d2a07b4
+2f8300007c6a1850
+3929000178690020
+3d408000419c0010
+409e00087f835000
+2c29000139200001
+418200143929ffff
+7d5a3850e8fd0000
+419c00307faad840
+3860000038210060
+2b9c001048000604
+7bdee102409e0014
+7d4a07b4394a0001
+7fdee3924bffff7c
+9b2700004bfffff0
+394a0001e95d0000
+4bffffa8f95d0000
+0100000000000000
+3c4c000100000780
+7c0802a638428834
+f821fed148000539
+f86100607c741b79
+4182006838600000
+419e00602fa40000
+3e42ffff39210040
+3b4100203ac4ffff
+60000000f9210070
+392280303ae00000
+3ba100603a527fe8
+89250000f9210078
+2fa90000ebc10060
+7ff4f050419e0010
+419c00207fbfb040
+993e000039200000
+7e941850e8610060
+382101307e8307b4
+2b89002548000508
+409e048839450001
+8925000038e00000
+f8a10068e9010070
+7d2741ae7cea07b4
+8d25000139070001
+2b8900647d0807b4
+2b890069419e0058
+2b890075419e0050
+2b890078419e0048
+2b890058419e0040
+2b890070419e0038
+2b890063419e0030
+2b890073419e0028
+2b890025419e0020
+2b89004f419e0018
+2b89006f419e0010
+409eff8838e70001
+2b890025394a0002
+7d1a42147d4a07b4
+992800207d5a5214
+409e00209aea0020
+f9210060393e0001
+993e000039200025
+38a90002e9210068
+892100414bffff04
+3a2600087fffb050
+3a600030eb660000
+3929ffd23b010042
+4082039c712900fd
+3b2000043aa00000
+3a0000013b800000
+7ddb00d039e0002d
+2b89006c48000108
+88f8000138d80001
+419d0118419e033c
+419e02402b890063
+2b89004f419d0038
+2b890058419e01e8
+3949ffd0419e0188
+2b8a0009554a063e
+395c0001419d00c4
+993c00207f81e214
+480000b0795c0020
+419e03042b890068
+419e000c2b890069
+409effc82b890064
+7d41e2142b890075
+7f6adb789aea0020
+57291838419e0034
+7e0948363929ffff
+418200207f694839
+e921006099e80000
+f921006039290001
+7d52482a7b291f24
+e88100607dca5038
+38e0000a7d465378
+7f45d378f9410080
+7e689b7839200000
+7c9e20507fa3eb78
+4bfffc9d7c84f850
+e9410080e8810060
+38c0000a7ea7ab78
+7d4553787c9e2050
+7fa3eb787c84f850
+3b1800014bfffaed
+e901006089380000
+419e00102fa90000
+7fbf50407d5e4050
+7e268b78419dfee4
+2b8900734bfffe90
+419d006c419e016c
+419e00d42b89006f
+409efef02b890070
+38e000107d21e214
+7c8af8507f66db78
+390000209ae90020
+7f45d37839200002
+4bfffc0d7fa3eb78
+e8a10078e8810060
+7c9e20507fa3eb78
+4bfffb757c84f850
+7ea7ab78e8810060
+7f65db7838c00010
+4bffff5c7c9e2050
+419e00182b890078
+419e01cc2b89007a
+4bfffeb82b890075
+7d21e2143aa00001
+7c8af85038e00010
+9ae900207e689b78
+7f45d3787b291f24
+7d72482a7fa3eb78
+7f6b583839200000
+f96100807d665b78
+e88100604bfffb89
+38c000107ea7ab78
+e96100807c9e2050
+4bfffeec7d655b78
+38e000087d21e214
+7e689b787c8af850
+7b291f249ae90020
+7fa3eb787f45d378
+392000007d72482a
+7d665b787f6b5838
+4bfffb35f9610080
+7ea7ab78e8810060
+7c9e205038c00008
+7d21e2144bffffac
+38e0000a39000020
+9ae9002038c00001
+392000007f45d378
+7fa3eb787c8af850
+e92100604bfffaf9
+e92100609b690000
+f921006039290001
+7d21e2144bfffe6c
+f901009038a0000a
+38800000f9410088
+9ae900207f43d378
+600000004bfff7a9
+7f63db78f8610080
+600000004bfff8cd
+7fa91840e9210080
+7c634850409d0040
+e9010090e9410088
+392300012fa30000
+409e00087d4af850
+2c29000139200001
+3929ffffe8c10060
+7ce8305041820010
+419d00207faa3840
+7f65db78e8810060
+7c9e20507fa3eb78
+4bfff9cd7c84f850
+38e000204bfffdd4
+e8e1006098e60000
+f8e1006038e70001
+2b87006c4bffffb4
+409efdb03b200008
+4bfffda87cd83378
+3b2000022b870068
+7cd83378409efd9c
+4bfffd903b200001
+4bfffd883b200008
+3b0100413a600020
+993e00004bfffc60
+e92100607d455378
+f921006039290001
+000000004bfffb24
+0000128001000000
+f9e1ff78f9c1ff70
+fa21ff88fa01ff80
+fa61ff98fa41ff90
+faa1ffa8fa81ffa0
+fae1ffb8fac1ffb0
+fb21ffc8fb01ffc0
+fb61ffd8fb41ffd0
+fba1ffe8fb81ffe0
+fbe1fff8fbc1fff0
+4e800020f8010010
+e9e1ff78e9c1ff70
+ea21ff88ea01ff80
+ea61ff98ea41ff90
+eaa1ffa8ea81ffa0
+eae1ffb8eac1ffb0
+eb21ffc8eb01ffc0
+eb61ffd8eb41ffd0
+e8010010eb81ffe0
+7c0803a6eba1ffe8
+ebe1fff8ebc1fff0
+ebc1fff04e800020
+ebe1fff8e8010010
+4e8000207c0803a6
+6d6f636c65570a0a
+63694d206f742065
+2120747461776f72
+0000000000000a0a
+67697320636f5320
+203a65727574616e
+0a786c6c36313025
+0000000000000000
+656620636f532020
+203a736572757461
+0000000000000000
+0000002054524155
+000000204d415244
+2020202020202020
+203a4d4152422020
+0a424b20646c6c25
+0000000000000000
+2020202020202020
+203a4d4152442020
+0a424d20646c6c25
+0000000000000000
+2020202020202020
+203a4b4c43202020
+7a484d20646c6c25
+000000000000000a
+6131333764343635
+0000000000000000
+0033306536316430
+4d4152446574694c
+6620746c69756220
+6567694d206d6f72
+646e61207325206e
+2520586574694c20
+0000000000000a73
+20676e69746f6f42
+415242206d6f7266
+0000000a2e2e2e4d
+20747365746d654d
+6c69616620737562
+252f6425203a6465
+73726f7272652064
+000000000000000a
+20747365746d654d
+6961662061746164
+2f6425203a64656c
+726f727265206425
+0000000000000a73
+20747365746d654d
+6961662072646461
+2f6425203a64656c
+726f727265206425
+0000000000000a73
+20747365746d654d
+00000000000a4b4f
+64656570736d654d
+3a73657469725720
+7370624d646c2520
+203a736461655220
+0a7370624d646c25
+0000000000000000
+6f6e204d41524453
+207265646e752077
+6572617764726168
+6c6f72746e6f6320
+000000000000000a
+696c616974696e49
+52445320676e697a
+00000a2e2e2e4d41
+0000000000000000
+00000000000000ff
+000000000000ffff
+0000000000ffffff
+00000000ffffffff
+000000ffffffffff
+0000ffffffffffff
+00ffffffffffffff
+ffffffffffffffff
+0000000000007830

diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v
new file mode 100644 (file)
index 0000000..10f9ecb
--- /dev/null
+++ b/litedram/generated/sim/litedram_core.v
@@ -0,0 +1,18236 @@
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-22 17:57:20
+//--------------------------------------------------------------------------------
+module litedram_core(
+       input wire clk,
+       output wire init_done,
+       output wire init_error,
+       input wire [29:0] wb_ctrl_adr,
+       input wire [31:0] wb_ctrl_dat_w,
+       output wire [31:0] wb_ctrl_dat_r,
+       input wire [3:0] wb_ctrl_sel,
+       input wire wb_ctrl_cyc,
+       input wire wb_ctrl_stb,
+       output wire wb_ctrl_ack,
+       input wire wb_ctrl_we,
+       input wire [2:0] wb_ctrl_cti,
+       input wire [1:0] wb_ctrl_bte,
+       output wire wb_ctrl_err,
+       output wire user_clk,
+       output wire user_rst,
+       input wire user_port_native_0_cmd_valid,
+       output wire user_port_native_0_cmd_ready,
+       input wire user_port_native_0_cmd_we,
+       input wire [23:0] user_port_native_0_cmd_addr,
+       input wire user_port_native_0_wdata_valid,
+       output wire user_port_native_0_wdata_ready,
+       input wire [15:0] user_port_native_0_wdata_we,
+       input wire [127:0] user_port_native_0_wdata_data,
+       output wire user_port_native_0_rdata_valid,
+       input wire user_port_native_0_rdata_ready,
+       output wire [127:0] user_port_native_0_rdata_data
+);
+
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+wire [31:0] litedramcore_dat_w;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+wire [31:0] litedramcore_wishbone_dat_r;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
+wire sys_clk;
+wire sys_rst;
+wire por_clk;
+reg int_rst = 1'd1;
+wire [13:0] ddrphy_dfi_p0_address;
+wire [2:0] ddrphy_dfi_p0_bank;
+wire ddrphy_dfi_p0_cas_n;
+wire ddrphy_dfi_p0_cs_n;
+wire ddrphy_dfi_p0_ras_n;
+wire ddrphy_dfi_p0_we_n;
+wire ddrphy_dfi_p0_cke;
+wire ddrphy_dfi_p0_odt;
+wire ddrphy_dfi_p0_reset_n;
+wire ddrphy_dfi_p0_act_n;
+wire [31:0] ddrphy_dfi_p0_wrdata;
+wire ddrphy_dfi_p0_wrdata_en;
+wire [3:0] ddrphy_dfi_p0_wrdata_mask;
+wire ddrphy_dfi_p0_rddata_en;
+wire [31:0] ddrphy_dfi_p0_rddata;
+wire ddrphy_dfi_p0_rddata_valid;
+wire [13:0] ddrphy_dfi_p1_address;
+wire [2:0] ddrphy_dfi_p1_bank;
+wire ddrphy_dfi_p1_cas_n;
+wire ddrphy_dfi_p1_cs_n;
+wire ddrphy_dfi_p1_ras_n;
+wire ddrphy_dfi_p1_we_n;
+wire ddrphy_dfi_p1_cke;
+wire ddrphy_dfi_p1_odt;
+wire ddrphy_dfi_p1_reset_n;
+wire ddrphy_dfi_p1_act_n;
+wire [31:0] ddrphy_dfi_p1_wrdata;
+wire ddrphy_dfi_p1_wrdata_en;
+wire [3:0] ddrphy_dfi_p1_wrdata_mask;
+wire ddrphy_dfi_p1_rddata_en;
+wire [31:0] ddrphy_dfi_p1_rddata;
+wire ddrphy_dfi_p1_rddata_valid;
+wire [13:0] ddrphy_dfi_p2_address;
+wire [2:0] ddrphy_dfi_p2_bank;
+wire ddrphy_dfi_p2_cas_n;
+wire ddrphy_dfi_p2_cs_n;
+wire ddrphy_dfi_p2_ras_n;
+wire ddrphy_dfi_p2_we_n;
+wire ddrphy_dfi_p2_cke;
+wire ddrphy_dfi_p2_odt;
+wire ddrphy_dfi_p2_reset_n;
+wire ddrphy_dfi_p2_act_n;
+wire [31:0] ddrphy_dfi_p2_wrdata;
+wire ddrphy_dfi_p2_wrdata_en;
+wire [3:0] ddrphy_dfi_p2_wrdata_mask;
+wire ddrphy_dfi_p2_rddata_en;
+wire [31:0] ddrphy_dfi_p2_rddata;
+wire ddrphy_dfi_p2_rddata_valid;
+wire [13:0] ddrphy_dfi_p3_address;
+wire [2:0] ddrphy_dfi_p3_bank;
+wire ddrphy_dfi_p3_cas_n;
+wire ddrphy_dfi_p3_cs_n;
+wire ddrphy_dfi_p3_ras_n;
+wire ddrphy_dfi_p3_we_n;
+wire ddrphy_dfi_p3_cke;
+wire ddrphy_dfi_p3_odt;
+wire ddrphy_dfi_p3_reset_n;
+wire ddrphy_dfi_p3_act_n;
+wire [31:0] ddrphy_dfi_p3_wrdata;
+wire ddrphy_dfi_p3_wrdata_en;
+wire [3:0] ddrphy_dfi_p3_wrdata_mask;
+wire ddrphy_dfi_p3_rddata_en;
+wire [31:0] ddrphy_dfi_p3_rddata;
+wire ddrphy_dfi_p3_rddata_valid;
+reg ddrphy_dfiphasemodel0_activate = 1'd0;
+reg ddrphy_dfiphasemodel0_precharge = 1'd0;
+reg ddrphy_dfiphasemodel0_write = 1'd0;
+reg ddrphy_dfiphasemodel0_read = 1'd0;
+reg ddrphy_dfiphasemodel1_activate = 1'd0;
+reg ddrphy_dfiphasemodel1_precharge = 1'd0;
+reg ddrphy_dfiphasemodel1_write = 1'd0;
+reg ddrphy_dfiphasemodel1_read = 1'd0;
+reg ddrphy_dfiphasemodel2_activate = 1'd0;
+reg ddrphy_dfiphasemodel2_precharge = 1'd0;
+reg ddrphy_dfiphasemodel2_write = 1'd0;
+reg ddrphy_dfiphasemodel2_read = 1'd0;
+reg ddrphy_dfiphasemodel3_activate = 1'd0;
+reg ddrphy_dfiphasemodel3_precharge = 1'd0;
+reg ddrphy_dfiphasemodel3_write = 1'd0;
+reg ddrphy_dfiphasemodel3_read = 1'd0;
+reg [63:0] ddrphy_dfitimingschecker_cnt = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker0 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker1 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker2 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker3 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker4 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker5 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker6 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker7 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker8 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker9 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker10 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker11 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker12 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker13 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker14 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker15 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker16 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker17 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker18 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker19 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker20 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker21 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker22 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker23 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker24 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker25 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker26 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker27 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker28 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker29 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker30 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker31 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker32 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker33 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker34 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker35 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker36 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker37 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker38 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker39 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker40 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker41 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker42 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker43 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker44 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker45 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker46 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker47 = 64'd0;
+reg [3:0] ddrphy_dfitimingschecker_last_cmd0 = 4'd0;
+reg [3:0] ddrphy_dfitimingschecker_last_cmd1 = 4'd0;
+reg [3:0] ddrphy_dfitimingschecker_last_cmd2 = 4'd0;
+reg [3:0] ddrphy_dfitimingschecker_last_cmd3 = 4'd0;
+reg [3:0] ddrphy_dfitimingschecker_last_cmd4 = 4'd0;
+reg [3:0] ddrphy_dfitimingschecker_last_cmd5 = 4'd0;
+reg [3:0] ddrphy_dfitimingschecker_last_cmd6 = 4'd0;
+reg [3:0] ddrphy_dfitimingschecker_last_cmd7 = 4'd0;
+reg [63:0] ddrphy_dfitimingschecker0 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker1 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker2 = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker3 = 64'd0;
+reg [1:0] ddrphy_dfitimingschecker_act_curr = 2'd0;
+reg [3:0] ddrphy_dfitimingschecker_ref_issued = 4'd0;
+wire [63:0] ddrphy_dfitimingschecker_ps0;
+wire [3:0] ddrphy_dfitimingschecker_state0;
+wire ddrphy_dfitimingschecker_all_banks0;
+wire ddrphy_dfitimingschecker_cmd_recv0;
+wire ddrphy_dfitimingschecker_cmd_recv1;
+wire ddrphy_dfitimingschecker_cmd_recv2;
+wire [1:0] ddrphy_dfitimingschecker_act_next0;
+wire ddrphy_dfitimingschecker_cmd_recv3;
+wire ddrphy_dfitimingschecker_cmd_recv4;
+wire ddrphy_dfitimingschecker_cmd_recv5;
+wire ddrphy_dfitimingschecker_cmd_recv6;
+wire ddrphy_dfitimingschecker_cmd_recv7;
+wire ddrphy_dfitimingschecker_cmd_recv8;
+wire [1:0] ddrphy_dfitimingschecker_act_next1;
+wire ddrphy_dfitimingschecker_cmd_recv9;
+wire ddrphy_dfitimingschecker_cmd_recv10;
+wire ddrphy_dfitimingschecker_cmd_recv11;
+wire ddrphy_dfitimingschecker_cmd_recv12;
+wire ddrphy_dfitimingschecker_cmd_recv13;
+wire ddrphy_dfitimingschecker_cmd_recv14;
+wire [1:0] ddrphy_dfitimingschecker_act_next2;
+wire ddrphy_dfitimingschecker_cmd_recv15;
+wire ddrphy_dfitimingschecker_cmd_recv16;
+wire ddrphy_dfitimingschecker_cmd_recv17;
+wire ddrphy_dfitimingschecker_cmd_recv18;
+wire ddrphy_dfitimingschecker_cmd_recv19;
+wire ddrphy_dfitimingschecker_cmd_recv20;
+wire [1:0] ddrphy_dfitimingschecker_act_next3;
+wire ddrphy_dfitimingschecker_cmd_recv21;
+wire ddrphy_dfitimingschecker_cmd_recv22;
+wire ddrphy_dfitimingschecker_cmd_recv23;
+wire ddrphy_dfitimingschecker_cmd_recv24;
+wire ddrphy_dfitimingschecker_cmd_recv25;
+wire ddrphy_dfitimingschecker_cmd_recv26;
+wire [1:0] ddrphy_dfitimingschecker_act_next4;
+wire ddrphy_dfitimingschecker_cmd_recv27;
+wire ddrphy_dfitimingschecker_cmd_recv28;
+wire ddrphy_dfitimingschecker_cmd_recv29;
+wire ddrphy_dfitimingschecker_cmd_recv30;
+wire ddrphy_dfitimingschecker_cmd_recv31;
+wire ddrphy_dfitimingschecker_cmd_recv32;
+wire [1:0] ddrphy_dfitimingschecker_act_next5;
+wire ddrphy_dfitimingschecker_cmd_recv33;
+wire ddrphy_dfitimingschecker_cmd_recv34;
+wire ddrphy_dfitimingschecker_cmd_recv35;
+wire ddrphy_dfitimingschecker_cmd_recv36;
+wire ddrphy_dfitimingschecker_cmd_recv37;
+wire ddrphy_dfitimingschecker_cmd_recv38;
+wire [1:0] ddrphy_dfitimingschecker_act_next6;
+wire ddrphy_dfitimingschecker_cmd_recv39;
+wire ddrphy_dfitimingschecker_cmd_recv40;
+wire ddrphy_dfitimingschecker_cmd_recv41;
+wire ddrphy_dfitimingschecker_cmd_recv42;
+wire ddrphy_dfitimingschecker_cmd_recv43;
+wire ddrphy_dfitimingschecker_cmd_recv44;
+wire [1:0] ddrphy_dfitimingschecker_act_next7;
+wire ddrphy_dfitimingschecker_cmd_recv45;
+wire ddrphy_dfitimingschecker_cmd_recv46;
+wire ddrphy_dfitimingschecker_cmd_recv47;
+wire [63:0] ddrphy_dfitimingschecker_ps1;
+wire [3:0] ddrphy_dfitimingschecker_state1;
+wire ddrphy_dfitimingschecker_all_banks1;
+wire ddrphy_dfitimingschecker_cmd_recv48;
+wire ddrphy_dfitimingschecker_cmd_recv49;
+wire ddrphy_dfitimingschecker_cmd_recv50;
+wire [1:0] ddrphy_dfitimingschecker_act_next8;
+wire ddrphy_dfitimingschecker_cmd_recv51;
+wire ddrphy_dfitimingschecker_cmd_recv52;
+wire ddrphy_dfitimingschecker_cmd_recv53;
+wire ddrphy_dfitimingschecker_cmd_recv54;
+wire ddrphy_dfitimingschecker_cmd_recv55;
+wire ddrphy_dfitimingschecker_cmd_recv56;
+wire [1:0] ddrphy_dfitimingschecker_act_next9;
+wire ddrphy_dfitimingschecker_cmd_recv57;
+wire ddrphy_dfitimingschecker_cmd_recv58;
+wire ddrphy_dfitimingschecker_cmd_recv59;
+wire ddrphy_dfitimingschecker_cmd_recv60;
+wire ddrphy_dfitimingschecker_cmd_recv61;
+wire ddrphy_dfitimingschecker_cmd_recv62;
+wire [1:0] ddrphy_dfitimingschecker_act_next10;
+wire ddrphy_dfitimingschecker_cmd_recv63;
+wire ddrphy_dfitimingschecker_cmd_recv64;
+wire ddrphy_dfitimingschecker_cmd_recv65;
+wire ddrphy_dfitimingschecker_cmd_recv66;
+wire ddrphy_dfitimingschecker_cmd_recv67;
+wire ddrphy_dfitimingschecker_cmd_recv68;
+wire [1:0] ddrphy_dfitimingschecker_act_next11;
+wire ddrphy_dfitimingschecker_cmd_recv69;
+wire ddrphy_dfitimingschecker_cmd_recv70;
+wire ddrphy_dfitimingschecker_cmd_recv71;
+wire ddrphy_dfitimingschecker_cmd_recv72;
+wire ddrphy_dfitimingschecker_cmd_recv73;
+wire ddrphy_dfitimingschecker_cmd_recv74;
+wire [1:0] ddrphy_dfitimingschecker_act_next12;
+wire ddrphy_dfitimingschecker_cmd_recv75;
+wire ddrphy_dfitimingschecker_cmd_recv76;
+wire ddrphy_dfitimingschecker_cmd_recv77;
+wire ddrphy_dfitimingschecker_cmd_recv78;
+wire ddrphy_dfitimingschecker_cmd_recv79;
+wire ddrphy_dfitimingschecker_cmd_recv80;
+wire [1:0] ddrphy_dfitimingschecker_act_next13;
+wire ddrphy_dfitimingschecker_cmd_recv81;
+wire ddrphy_dfitimingschecker_cmd_recv82;
+wire ddrphy_dfitimingschecker_cmd_recv83;
+wire ddrphy_dfitimingschecker_cmd_recv84;
+wire ddrphy_dfitimingschecker_cmd_recv85;
+wire ddrphy_dfitimingschecker_cmd_recv86;
+wire [1:0] ddrphy_dfitimingschecker_act_next14;
+wire ddrphy_dfitimingschecker_cmd_recv87;
+wire ddrphy_dfitimingschecker_cmd_recv88;
+wire ddrphy_dfitimingschecker_cmd_recv89;
+wire ddrphy_dfitimingschecker_cmd_recv90;
+wire ddrphy_dfitimingschecker_cmd_recv91;
+wire ddrphy_dfitimingschecker_cmd_recv92;
+wire [1:0] ddrphy_dfitimingschecker_act_next15;
+wire ddrphy_dfitimingschecker_cmd_recv93;
+wire ddrphy_dfitimingschecker_cmd_recv94;
+wire ddrphy_dfitimingschecker_cmd_recv95;
+wire [63:0] ddrphy_dfitimingschecker_ps2;
+wire [3:0] ddrphy_dfitimingschecker_state2;
+wire ddrphy_dfitimingschecker_all_banks2;
+wire ddrphy_dfitimingschecker_cmd_recv96;
+wire ddrphy_dfitimingschecker_cmd_recv97;
+wire ddrphy_dfitimingschecker_cmd_recv98;
+wire [1:0] ddrphy_dfitimingschecker_act_next16;
+wire ddrphy_dfitimingschecker_cmd_recv99;
+wire ddrphy_dfitimingschecker_cmd_recv100;
+wire ddrphy_dfitimingschecker_cmd_recv101;
+wire ddrphy_dfitimingschecker_cmd_recv102;
+wire ddrphy_dfitimingschecker_cmd_recv103;
+wire ddrphy_dfitimingschecker_cmd_recv104;
+wire [1:0] ddrphy_dfitimingschecker_act_next17;
+wire ddrphy_dfitimingschecker_cmd_recv105;
+wire ddrphy_dfitimingschecker_cmd_recv106;
+wire ddrphy_dfitimingschecker_cmd_recv107;
+wire ddrphy_dfitimingschecker_cmd_recv108;
+wire ddrphy_dfitimingschecker_cmd_recv109;
+wire ddrphy_dfitimingschecker_cmd_recv110;
+wire [1:0] ddrphy_dfitimingschecker_act_next18;
+wire ddrphy_dfitimingschecker_cmd_recv111;
+wire ddrphy_dfitimingschecker_cmd_recv112;
+wire ddrphy_dfitimingschecker_cmd_recv113;
+wire ddrphy_dfitimingschecker_cmd_recv114;
+wire ddrphy_dfitimingschecker_cmd_recv115;
+wire ddrphy_dfitimingschecker_cmd_recv116;
+wire [1:0] ddrphy_dfitimingschecker_act_next19;
+wire ddrphy_dfitimingschecker_cmd_recv117;
+wire ddrphy_dfitimingschecker_cmd_recv118;
+wire ddrphy_dfitimingschecker_cmd_recv119;
+wire ddrphy_dfitimingschecker_cmd_recv120;
+wire ddrphy_dfitimingschecker_cmd_recv121;
+wire ddrphy_dfitimingschecker_cmd_recv122;
+wire [1:0] ddrphy_dfitimingschecker_act_next20;
+wire ddrphy_dfitimingschecker_cmd_recv123;
+wire ddrphy_dfitimingschecker_cmd_recv124;
+wire ddrphy_dfitimingschecker_cmd_recv125;
+wire ddrphy_dfitimingschecker_cmd_recv126;
+wire ddrphy_dfitimingschecker_cmd_recv127;
+wire ddrphy_dfitimingschecker_cmd_recv128;
+wire [1:0] ddrphy_dfitimingschecker_act_next21;
+wire ddrphy_dfitimingschecker_cmd_recv129;
+wire ddrphy_dfitimingschecker_cmd_recv130;
+wire ddrphy_dfitimingschecker_cmd_recv131;
+wire ddrphy_dfitimingschecker_cmd_recv132;
+wire ddrphy_dfitimingschecker_cmd_recv133;
+wire ddrphy_dfitimingschecker_cmd_recv134;
+wire [1:0] ddrphy_dfitimingschecker_act_next22;
+wire ddrphy_dfitimingschecker_cmd_recv135;
+wire ddrphy_dfitimingschecker_cmd_recv136;
+wire ddrphy_dfitimingschecker_cmd_recv137;
+wire ddrphy_dfitimingschecker_cmd_recv138;
+wire ddrphy_dfitimingschecker_cmd_recv139;
+wire ddrphy_dfitimingschecker_cmd_recv140;
+wire [1:0] ddrphy_dfitimingschecker_act_next23;
+wire ddrphy_dfitimingschecker_cmd_recv141;
+wire ddrphy_dfitimingschecker_cmd_recv142;
+wire ddrphy_dfitimingschecker_cmd_recv143;
+wire [63:0] ddrphy_dfitimingschecker_ps3;
+wire [3:0] ddrphy_dfitimingschecker_state3;
+wire ddrphy_dfitimingschecker_all_banks3;
+wire ddrphy_dfitimingschecker_cmd_recv144;
+wire ddrphy_dfitimingschecker_cmd_recv145;
+wire ddrphy_dfitimingschecker_cmd_recv146;
+wire [1:0] ddrphy_dfitimingschecker_act_next24;
+wire ddrphy_dfitimingschecker_cmd_recv147;
+wire ddrphy_dfitimingschecker_cmd_recv148;
+wire ddrphy_dfitimingschecker_cmd_recv149;
+wire ddrphy_dfitimingschecker_cmd_recv150;
+wire ddrphy_dfitimingschecker_cmd_recv151;
+wire ddrphy_dfitimingschecker_cmd_recv152;
+wire [1:0] ddrphy_dfitimingschecker_act_next25;
+wire ddrphy_dfitimingschecker_cmd_recv153;
+wire ddrphy_dfitimingschecker_cmd_recv154;
+wire ddrphy_dfitimingschecker_cmd_recv155;
+wire ddrphy_dfitimingschecker_cmd_recv156;
+wire ddrphy_dfitimingschecker_cmd_recv157;
+wire ddrphy_dfitimingschecker_cmd_recv158;
+wire [1:0] ddrphy_dfitimingschecker_act_next26;
+wire ddrphy_dfitimingschecker_cmd_recv159;
+wire ddrphy_dfitimingschecker_cmd_recv160;
+wire ddrphy_dfitimingschecker_cmd_recv161;
+wire ddrphy_dfitimingschecker_cmd_recv162;
+wire ddrphy_dfitimingschecker_cmd_recv163;
+wire ddrphy_dfitimingschecker_cmd_recv164;
+wire [1:0] ddrphy_dfitimingschecker_act_next27;
+wire ddrphy_dfitimingschecker_cmd_recv165;
+wire ddrphy_dfitimingschecker_cmd_recv166;
+wire ddrphy_dfitimingschecker_cmd_recv167;
+wire ddrphy_dfitimingschecker_cmd_recv168;
+wire ddrphy_dfitimingschecker_cmd_recv169;
+wire ddrphy_dfitimingschecker_cmd_recv170;
+wire [1:0] ddrphy_dfitimingschecker_act_next28;
+wire ddrphy_dfitimingschecker_cmd_recv171;
+wire ddrphy_dfitimingschecker_cmd_recv172;
+wire ddrphy_dfitimingschecker_cmd_recv173;
+wire ddrphy_dfitimingschecker_cmd_recv174;
+wire ddrphy_dfitimingschecker_cmd_recv175;
+wire ddrphy_dfitimingschecker_cmd_recv176;
+wire [1:0] ddrphy_dfitimingschecker_act_next29;
+wire ddrphy_dfitimingschecker_cmd_recv177;
+wire ddrphy_dfitimingschecker_cmd_recv178;
+wire ddrphy_dfitimingschecker_cmd_recv179;
+wire ddrphy_dfitimingschecker_cmd_recv180;
+wire ddrphy_dfitimingschecker_cmd_recv181;
+wire ddrphy_dfitimingschecker_cmd_recv182;
+wire [1:0] ddrphy_dfitimingschecker_act_next30;
+wire ddrphy_dfitimingschecker_cmd_recv183;
+wire ddrphy_dfitimingschecker_cmd_recv184;
+wire ddrphy_dfitimingschecker_cmd_recv185;
+wire ddrphy_dfitimingschecker_cmd_recv186;
+wire ddrphy_dfitimingschecker_cmd_recv187;
+wire ddrphy_dfitimingschecker_cmd_recv188;
+wire [1:0] ddrphy_dfitimingschecker_act_next31;
+wire ddrphy_dfitimingschecker_cmd_recv189;
+wire ddrphy_dfitimingschecker_cmd_recv190;
+wire ddrphy_dfitimingschecker_cmd_recv191;
+reg [63:0] ddrphy_dfitimingschecker_ref_ps = 64'd0;
+reg [63:0] ddrphy_dfitimingschecker_ref_ps_mod = 64'd0;
+reg signed [63:0] ddrphy_dfitimingschecker_ref_ps_diff = 64'd0;
+wire signed [63:0] ddrphy_dfitimingschecker_curr_diff;
+reg ddrphy_dfitimingschecker_ref_done = 1'd0;
+reg ddrphy_bankmodel0_activate = 1'd0;
+reg [13:0] ddrphy_bankmodel0_activate_row = 14'd0;
+reg ddrphy_bankmodel0_precharge = 1'd0;
+wire ddrphy_bankmodel0_write;
+wire [9:0] ddrphy_bankmodel0_write_col;
+wire [127:0] ddrphy_bankmodel0_write_data;
+wire [15:0] ddrphy_bankmodel0_write_mask;
+reg ddrphy_bankmodel0_read = 1'd0;
+reg [9:0] ddrphy_bankmodel0_read_col = 10'd0;
+reg [127:0] ddrphy_bankmodel0_read_data = 128'd0;
+reg ddrphy_bankmodel0_active = 1'd0;
+reg [13:0] ddrphy_bankmodel0_row = 14'd0;
+reg [20:0] ddrphy_bankmodel0_write_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel0_write_port_dat_r;
+reg [15:0] ddrphy_bankmodel0_write_port_we = 16'd0;
+reg [127:0] ddrphy_bankmodel0_write_port_dat_w = 128'd0;
+reg [20:0] ddrphy_bankmodel0_read_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel0_read_port_dat_r;
+wire [20:0] ddrphy_bankmodel0_wraddr;
+wire [20:0] ddrphy_bankmodel0_rdaddr;
+reg ddrphy_bankmodel1_activate = 1'd0;
+reg [13:0] ddrphy_bankmodel1_activate_row = 14'd0;
+reg ddrphy_bankmodel1_precharge = 1'd0;
+wire ddrphy_bankmodel1_write;
+wire [9:0] ddrphy_bankmodel1_write_col;
+wire [127:0] ddrphy_bankmodel1_write_data;
+wire [15:0] ddrphy_bankmodel1_write_mask;
+reg ddrphy_bankmodel1_read = 1'd0;
+reg [9:0] ddrphy_bankmodel1_read_col = 10'd0;
+reg [127:0] ddrphy_bankmodel1_read_data = 128'd0;
+reg ddrphy_bankmodel1_active = 1'd0;
+reg [13:0] ddrphy_bankmodel1_row = 14'd0;
+reg [20:0] ddrphy_bankmodel1_write_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel1_write_port_dat_r;
+reg [15:0] ddrphy_bankmodel1_write_port_we = 16'd0;
+reg [127:0] ddrphy_bankmodel1_write_port_dat_w = 128'd0;
+reg [20:0] ddrphy_bankmodel1_read_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel1_read_port_dat_r;
+wire [20:0] ddrphy_bankmodel1_wraddr;
+wire [20:0] ddrphy_bankmodel1_rdaddr;
+reg ddrphy_bankmodel2_activate = 1'd0;
+reg [13:0] ddrphy_bankmodel2_activate_row = 14'd0;
+reg ddrphy_bankmodel2_precharge = 1'd0;
+wire ddrphy_bankmodel2_write;
+wire [9:0] ddrphy_bankmodel2_write_col;
+wire [127:0] ddrphy_bankmodel2_write_data;
+wire [15:0] ddrphy_bankmodel2_write_mask;
+reg ddrphy_bankmodel2_read = 1'd0;
+reg [9:0] ddrphy_bankmodel2_read_col = 10'd0;
+reg [127:0] ddrphy_bankmodel2_read_data = 128'd0;
+reg ddrphy_bankmodel2_active = 1'd0;
+reg [13:0] ddrphy_bankmodel2_row = 14'd0;
+reg [20:0] ddrphy_bankmodel2_write_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel2_write_port_dat_r;
+reg [15:0] ddrphy_bankmodel2_write_port_we = 16'd0;
+reg [127:0] ddrphy_bankmodel2_write_port_dat_w = 128'd0;
+reg [20:0] ddrphy_bankmodel2_read_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel2_read_port_dat_r;
+wire [20:0] ddrphy_bankmodel2_wraddr;
+wire [20:0] ddrphy_bankmodel2_rdaddr;
+reg ddrphy_bankmodel3_activate = 1'd0;
+reg [13:0] ddrphy_bankmodel3_activate_row = 14'd0;
+reg ddrphy_bankmodel3_precharge = 1'd0;
+wire ddrphy_bankmodel3_write;
+wire [9:0] ddrphy_bankmodel3_write_col;
+wire [127:0] ddrphy_bankmodel3_write_data;
+wire [15:0] ddrphy_bankmodel3_write_mask;
+reg ddrphy_bankmodel3_read = 1'd0;
+reg [9:0] ddrphy_bankmodel3_read_col = 10'd0;
+reg [127:0] ddrphy_bankmodel3_read_data = 128'd0;
+reg ddrphy_bankmodel3_active = 1'd0;
+reg [13:0] ddrphy_bankmodel3_row = 14'd0;
+reg [20:0] ddrphy_bankmodel3_write_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel3_write_port_dat_r;
+reg [15:0] ddrphy_bankmodel3_write_port_we = 16'd0;
+reg [127:0] ddrphy_bankmodel3_write_port_dat_w = 128'd0;
+reg [20:0] ddrphy_bankmodel3_read_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel3_read_port_dat_r;
+wire [20:0] ddrphy_bankmodel3_wraddr;
+wire [20:0] ddrphy_bankmodel3_rdaddr;
+reg ddrphy_bankmodel4_activate = 1'd0;
+reg [13:0] ddrphy_bankmodel4_activate_row = 14'd0;
+reg ddrphy_bankmodel4_precharge = 1'd0;
+wire ddrphy_bankmodel4_write;
+wire [9:0] ddrphy_bankmodel4_write_col;
+wire [127:0] ddrphy_bankmodel4_write_data;
+wire [15:0] ddrphy_bankmodel4_write_mask;
+reg ddrphy_bankmodel4_read = 1'd0;
+reg [9:0] ddrphy_bankmodel4_read_col = 10'd0;
+reg [127:0] ddrphy_bankmodel4_read_data = 128'd0;
+reg ddrphy_bankmodel4_active = 1'd0;
+reg [13:0] ddrphy_bankmodel4_row = 14'd0;
+reg [20:0] ddrphy_bankmodel4_write_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel4_write_port_dat_r;
+reg [15:0] ddrphy_bankmodel4_write_port_we = 16'd0;
+reg [127:0] ddrphy_bankmodel4_write_port_dat_w = 128'd0;
+reg [20:0] ddrphy_bankmodel4_read_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel4_read_port_dat_r;
+wire [20:0] ddrphy_bankmodel4_wraddr;
+wire [20:0] ddrphy_bankmodel4_rdaddr;
+reg ddrphy_bankmodel5_activate = 1'd0;
+reg [13:0] ddrphy_bankmodel5_activate_row = 14'd0;
+reg ddrphy_bankmodel5_precharge = 1'd0;
+wire ddrphy_bankmodel5_write;
+wire [9:0] ddrphy_bankmodel5_write_col;
+wire [127:0] ddrphy_bankmodel5_write_data;
+wire [15:0] ddrphy_bankmodel5_write_mask;
+reg ddrphy_bankmodel5_read = 1'd0;
+reg [9:0] ddrphy_bankmodel5_read_col = 10'd0;
+reg [127:0] ddrphy_bankmodel5_read_data = 128'd0;
+reg ddrphy_bankmodel5_active = 1'd0;
+reg [13:0] ddrphy_bankmodel5_row = 14'd0;
+reg [20:0] ddrphy_bankmodel5_write_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel5_write_port_dat_r;
+reg [15:0] ddrphy_bankmodel5_write_port_we = 16'd0;
+reg [127:0] ddrphy_bankmodel5_write_port_dat_w = 128'd0;
+reg [20:0] ddrphy_bankmodel5_read_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel5_read_port_dat_r;
+wire [20:0] ddrphy_bankmodel5_wraddr;
+wire [20:0] ddrphy_bankmodel5_rdaddr;
+reg ddrphy_bankmodel6_activate = 1'd0;
+reg [13:0] ddrphy_bankmodel6_activate_row = 14'd0;
+reg ddrphy_bankmodel6_precharge = 1'd0;
+wire ddrphy_bankmodel6_write;
+wire [9:0] ddrphy_bankmodel6_write_col;
+wire [127:0] ddrphy_bankmodel6_write_data;
+wire [15:0] ddrphy_bankmodel6_write_mask;
+reg ddrphy_bankmodel6_read = 1'd0;
+reg [9:0] ddrphy_bankmodel6_read_col = 10'd0;
+reg [127:0] ddrphy_bankmodel6_read_data = 128'd0;
+reg ddrphy_bankmodel6_active = 1'd0;
+reg [13:0] ddrphy_bankmodel6_row = 14'd0;
+reg [20:0] ddrphy_bankmodel6_write_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel6_write_port_dat_r;
+reg [15:0] ddrphy_bankmodel6_write_port_we = 16'd0;
+reg [127:0] ddrphy_bankmodel6_write_port_dat_w = 128'd0;
+reg [20:0] ddrphy_bankmodel6_read_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel6_read_port_dat_r;
+wire [20:0] ddrphy_bankmodel6_wraddr;
+wire [20:0] ddrphy_bankmodel6_rdaddr;
+reg ddrphy_bankmodel7_activate = 1'd0;
+reg [13:0] ddrphy_bankmodel7_activate_row = 14'd0;
+reg ddrphy_bankmodel7_precharge = 1'd0;
+wire ddrphy_bankmodel7_write;
+wire [9:0] ddrphy_bankmodel7_write_col;
+wire [127:0] ddrphy_bankmodel7_write_data;
+wire [15:0] ddrphy_bankmodel7_write_mask;
+reg ddrphy_bankmodel7_read = 1'd0;
+reg [9:0] ddrphy_bankmodel7_read_col = 10'd0;
+reg [127:0] ddrphy_bankmodel7_read_data = 128'd0;
+reg ddrphy_bankmodel7_active = 1'd0;
+reg [13:0] ddrphy_bankmodel7_row = 14'd0;
+reg [20:0] ddrphy_bankmodel7_write_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel7_write_port_dat_r;
+reg [15:0] ddrphy_bankmodel7_write_port_we = 16'd0;
+reg [127:0] ddrphy_bankmodel7_write_port_dat_w = 128'd0;
+reg [20:0] ddrphy_bankmodel7_read_port_adr = 21'd0;
+wire [127:0] ddrphy_bankmodel7_read_port_dat_r;
+wire [20:0] ddrphy_bankmodel7_wraddr;
+wire [20:0] ddrphy_bankmodel7_rdaddr;
+reg [3:0] ddrphy_activates0 = 4'd0;
+reg [3:0] ddrphy_precharges0 = 4'd0;
+reg ddrphy_bank_write0 = 1'd0;
+reg [9:0] ddrphy_bank_write_col0 = 10'd0;
+reg [3:0] ddrphy_writes0 = 4'd0;
+reg ddrphy_new_bank_write0 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col0 = 10'd0;
+reg ddrphy_new_bank_write1 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col1 = 10'd0;
+reg [3:0] ddrphy_reads0 = 4'd0;
+reg [3:0] ddrphy_activates1 = 4'd0;
+reg [3:0] ddrphy_precharges1 = 4'd0;
+reg ddrphy_bank_write1 = 1'd0;
+reg [9:0] ddrphy_bank_write_col1 = 10'd0;
+reg [3:0] ddrphy_writes1 = 4'd0;
+reg ddrphy_new_bank_write2 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col2 = 10'd0;
+reg ddrphy_new_bank_write3 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col3 = 10'd0;
+reg [3:0] ddrphy_reads1 = 4'd0;
+reg [3:0] ddrphy_activates2 = 4'd0;
+reg [3:0] ddrphy_precharges2 = 4'd0;
+reg ddrphy_bank_write2 = 1'd0;
+reg [9:0] ddrphy_bank_write_col2 = 10'd0;
+reg [3:0] ddrphy_writes2 = 4'd0;
+reg ddrphy_new_bank_write4 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col4 = 10'd0;
+reg ddrphy_new_bank_write5 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col5 = 10'd0;
+reg [3:0] ddrphy_reads2 = 4'd0;
+reg [3:0] ddrphy_activates3 = 4'd0;
+reg [3:0] ddrphy_precharges3 = 4'd0;
+reg ddrphy_bank_write3 = 1'd0;
+reg [9:0] ddrphy_bank_write_col3 = 10'd0;
+reg [3:0] ddrphy_writes3 = 4'd0;
+reg ddrphy_new_bank_write6 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col6 = 10'd0;
+reg ddrphy_new_bank_write7 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col7 = 10'd0;
+reg [3:0] ddrphy_reads3 = 4'd0;
+reg [3:0] ddrphy_activates4 = 4'd0;
+reg [3:0] ddrphy_precharges4 = 4'd0;
+reg ddrphy_bank_write4 = 1'd0;
+reg [9:0] ddrphy_bank_write_col4 = 10'd0;
+reg [3:0] ddrphy_writes4 = 4'd0;
+reg ddrphy_new_bank_write8 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col8 = 10'd0;
+reg ddrphy_new_bank_write9 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col9 = 10'd0;
+reg [3:0] ddrphy_reads4 = 4'd0;
+reg [3:0] ddrphy_activates5 = 4'd0;
+reg [3:0] ddrphy_precharges5 = 4'd0;
+reg ddrphy_bank_write5 = 1'd0;
+reg [9:0] ddrphy_bank_write_col5 = 10'd0;
+reg [3:0] ddrphy_writes5 = 4'd0;
+reg ddrphy_new_bank_write10 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col10 = 10'd0;
+reg ddrphy_new_bank_write11 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col11 = 10'd0;
+reg [3:0] ddrphy_reads5 = 4'd0;
+reg [3:0] ddrphy_activates6 = 4'd0;
+reg [3:0] ddrphy_precharges6 = 4'd0;
+reg ddrphy_bank_write6 = 1'd0;
+reg [9:0] ddrphy_bank_write_col6 = 10'd0;
+reg [3:0] ddrphy_writes6 = 4'd0;
+reg ddrphy_new_bank_write12 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col12 = 10'd0;
+reg ddrphy_new_bank_write13 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col13 = 10'd0;
+reg [3:0] ddrphy_reads6 = 4'd0;
+reg [3:0] ddrphy_activates7 = 4'd0;
+reg [3:0] ddrphy_precharges7 = 4'd0;
+reg ddrphy_bank_write7 = 1'd0;
+reg [9:0] ddrphy_bank_write_col7 = 10'd0;
+reg [3:0] ddrphy_writes7 = 4'd0;
+reg ddrphy_new_bank_write14 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col14 = 10'd0;
+reg ddrphy_new_bank_write15 = 1'd0;
+reg [9:0] ddrphy_new_bank_write_col15 = 10'd0;
+reg [3:0] ddrphy_reads7 = 4'd0;
+wire ddrphy_banks_read;
+wire [127:0] ddrphy_banks_read_data;
+reg ddrphy_new_banks_read0 = 1'd0;
+reg [127:0] ddrphy_new_banks_read_data0 = 128'd0;
+reg ddrphy_new_banks_read1 = 1'd0;
+reg [127:0] ddrphy_new_banks_read_data1 = 128'd0;
+reg ddrphy_new_banks_read2 = 1'd0;
+reg [127:0] ddrphy_new_banks_read_data2 = 128'd0;
+reg ddrphy_new_banks_read3 = 1'd0;
+reg [127:0] ddrphy_new_banks_read_data3 = 128'd0;
+reg ddrphy_new_banks_read4 = 1'd0;
+reg [127:0] ddrphy_new_banks_read_data4 = 128'd0;
+reg ddrphy_new_banks_read5 = 1'd0;
+reg [127:0] ddrphy_new_banks_read_data5 = 128'd0;
+reg ddrphy_new_banks_read6 = 1'd0;
+reg [127:0] ddrphy_new_banks_read_data6 = 128'd0;
+reg ddrphy_new_banks_read7 = 1'd0;
+reg [127:0] ddrphy_new_banks_read_data7 = 128'd0;
+reg ddrphy_new_banks_read8 = 1'd0;
+reg [127:0] ddrphy_new_banks_read_data8 = 128'd0;
+wire [13:0] litedramcore_inti_p0_address;
+wire [2:0] litedramcore_inti_p0_bank;
+reg litedramcore_inti_p0_cas_n = 1'd1;
+reg litedramcore_inti_p0_cs_n = 1'd1;
+reg litedramcore_inti_p0_ras_n = 1'd1;
+reg litedramcore_inti_p0_we_n = 1'd1;
+wire litedramcore_inti_p0_cke;
+wire litedramcore_inti_p0_odt;
+wire litedramcore_inti_p0_reset_n;
+reg litedramcore_inti_p0_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p0_wrdata;
+wire litedramcore_inti_p0_wrdata_en;
+wire [3:0] litedramcore_inti_p0_wrdata_mask;
+wire litedramcore_inti_p0_rddata_en;
+reg [31:0] litedramcore_inti_p0_rddata = 32'd0;
+reg litedramcore_inti_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_inti_p1_address;
+wire [2:0] litedramcore_inti_p1_bank;
+reg litedramcore_inti_p1_cas_n = 1'd1;
+reg litedramcore_inti_p1_cs_n = 1'd1;
+reg litedramcore_inti_p1_ras_n = 1'd1;
+reg litedramcore_inti_p1_we_n = 1'd1;
+wire litedramcore_inti_p1_cke;
+wire litedramcore_inti_p1_odt;
+wire litedramcore_inti_p1_reset_n;
+reg litedramcore_inti_p1_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p1_wrdata;
+wire litedramcore_inti_p1_wrdata_en;
+wire [3:0] litedramcore_inti_p1_wrdata_mask;
+wire litedramcore_inti_p1_rddata_en;
+reg [31:0] litedramcore_inti_p1_rddata = 32'd0;
+reg litedramcore_inti_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_inti_p2_address;
+wire [2:0] litedramcore_inti_p2_bank;
+reg litedramcore_inti_p2_cas_n = 1'd1;
+reg litedramcore_inti_p2_cs_n = 1'd1;
+reg litedramcore_inti_p2_ras_n = 1'd1;
+reg litedramcore_inti_p2_we_n = 1'd1;
+wire litedramcore_inti_p2_cke;
+wire litedramcore_inti_p2_odt;
+wire litedramcore_inti_p2_reset_n;
+reg litedramcore_inti_p2_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p2_wrdata;
+wire litedramcore_inti_p2_wrdata_en;
+wire [3:0] litedramcore_inti_p2_wrdata_mask;
+wire litedramcore_inti_p2_rddata_en;
+reg [31:0] litedramcore_inti_p2_rddata = 32'd0;
+reg litedramcore_inti_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_inti_p3_address;
+wire [2:0] litedramcore_inti_p3_bank;
+reg litedramcore_inti_p3_cas_n = 1'd1;
+reg litedramcore_inti_p3_cs_n = 1'd1;
+reg litedramcore_inti_p3_ras_n = 1'd1;
+reg litedramcore_inti_p3_we_n = 1'd1;
+wire litedramcore_inti_p3_cke;
+wire litedramcore_inti_p3_odt;
+wire litedramcore_inti_p3_reset_n;
+reg litedramcore_inti_p3_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p3_wrdata;
+wire litedramcore_inti_p3_wrdata_en;
+wire [3:0] litedramcore_inti_p3_wrdata_mask;
+wire litedramcore_inti_p3_rddata_en;
+reg [31:0] litedramcore_inti_p3_rddata = 32'd0;
+reg litedramcore_inti_p3_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [13:0] litedramcore_master_p0_address = 14'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [13:0] litedramcore_master_p1_address = 14'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg [13:0] litedramcore_master_p2_address = 14'd0;
+reg [2:0] litedramcore_master_p2_bank = 3'd0;
+reg litedramcore_master_p2_cas_n = 1'd1;
+reg litedramcore_master_p2_cs_n = 1'd1;
+reg litedramcore_master_p2_ras_n = 1'd1;
+reg litedramcore_master_p2_we_n = 1'd1;
+reg litedramcore_master_p2_cke = 1'd0;
+reg litedramcore_master_p2_odt = 1'd0;
+reg litedramcore_master_p2_reset_n = 1'd0;
+reg litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg [13:0] litedramcore_master_p3_address = 14'd0;
+reg [2:0] litedramcore_master_p3_bank = 3'd0;
+reg litedramcore_master_p3_cas_n = 1'd1;
+reg litedramcore_master_p3_cs_n = 1'd1;
+reg litedramcore_master_p3_ras_n = 1'd1;
+reg litedramcore_master_p3_we_n = 1'd1;
+reg litedramcore_master_p3_cke = 1'd0;
+reg litedramcore_master_p3_odt = 1'd0;
+reg litedramcore_master_p3_reset_n = 1'd0;
+reg litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+reg [3:0] litedramcore_storage = 4'd0;
+reg litedramcore_re = 1'd0;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_re;
+wire litedramcore_phaseinjector0_command_issue_r;
+wire litedramcore_phaseinjector0_command_issue_we;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_status = 32'd0;
+wire litedramcore_phaseinjector0_we;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_re;
+wire litedramcore_phaseinjector1_command_issue_r;
+wire litedramcore_phaseinjector1_command_issue_we;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_status = 32'd0;
+wire litedramcore_phaseinjector1_we;
+reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg litedramcore_phaseinjector2_command_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_re;
+wire litedramcore_phaseinjector2_command_issue_r;
+wire litedramcore_phaseinjector2_command_issue_we;
+reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
+reg litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_status = 32'd0;
+wire litedramcore_phaseinjector2_we;
+reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg litedramcore_phaseinjector3_command_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_re;
+wire litedramcore_phaseinjector3_command_issue_r;
+wire litedramcore_phaseinjector3_command_issue_we;
+reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
+reg litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_status = 32'd0;
+wire litedramcore_phaseinjector3_we;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [20:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [20:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [20:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [20:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [20:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [20:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [20:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [20:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [127:0] litedramcore_interface_wdata = 128'd0;
+reg [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg [13:0] litedramcore_dfi_p0_address = 14'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [13:0] litedramcore_dfi_p1_address = 14'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg [13:0] litedramcore_dfi_p2_address = 14'd0;
+reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg litedramcore_dfi_p2_cas_n = 1'd1;
+reg litedramcore_dfi_p2_cs_n = 1'd1;
+reg litedramcore_dfi_p2_ras_n = 1'd1;
+reg litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg [13:0] litedramcore_dfi_p3_address = 14'd0;
+reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg litedramcore_dfi_p3_cas_n = 1'd1;
+reg litedramcore_dfi_p3_cs_n = 1'd1;
+reg litedramcore_dfi_p3_ras_n = 1'd1;
+reg litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [13:0] litedramcore_cmd_payload_a = 14'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] litedramcore_sequencer_counter = 6'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [20:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine0_row = 14'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [20:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine1_row = 14'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [20:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine2_row = 14'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [20:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine3_row = 14'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [20:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine4_row = 14'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [20:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine5_row = 14'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [20:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine6_row = 14'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [20:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine7_row = 14'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* no_retiming = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [13:0] litedramcore_nop_a = 14'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+reg litedramcore_steerer4 = 1'd1;
+reg litedramcore_steerer5 = 1'd1;
+reg litedramcore_steerer6 = 1'd1;
+reg litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* no_retiming = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* no_retiming = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* no_retiming = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* no_retiming = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [23:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg state = 1'd0;
+reg next_state = 1'd0;
+reg [1:0] refresher_state = 2'd0;
+reg [1:0] refresher_next_state = 2'd0;
+reg [3:0] bankmachine0_state = 4'd0;
+reg [3:0] bankmachine0_next_state = 4'd0;
+reg [3:0] bankmachine1_state = 4'd0;
+reg [3:0] bankmachine1_next_state = 4'd0;
+reg [3:0] bankmachine2_state = 4'd0;
+reg [3:0] bankmachine2_next_state = 4'd0;
+reg [3:0] bankmachine3_state = 4'd0;
+reg [3:0] bankmachine3_next_state = 4'd0;
+reg [3:0] bankmachine4_state = 4'd0;
+reg [3:0] bankmachine4_next_state = 4'd0;
+reg [3:0] bankmachine5_state = 4'd0;
+reg [3:0] bankmachine5_next_state = 4'd0;
+reg [3:0] bankmachine6_state = 4'd0;
+reg [3:0] bankmachine6_next_state = 4'd0;
+reg [3:0] bankmachine7_state = 4'd0;
+reg [3:0] bankmachine7_next_state = 4'd0;
+reg [3:0] multiplexer_state = 4'd0;
+reg [3:0] multiplexer_next_state = 4'd0;
+wire roundrobin0_request;
+wire roundrobin0_grant;
+wire roundrobin0_ce;
+wire roundrobin1_request;
+wire roundrobin1_grant;
+wire roundrobin1_ce;
+wire roundrobin2_request;
+wire roundrobin2_grant;
+wire roundrobin2_ce;
+wire roundrobin3_request;
+wire roundrobin3_grant;
+wire roundrobin3_ce;
+wire roundrobin4_request;
+wire roundrobin4_grant;
+wire roundrobin4_ce;
+wire roundrobin5_request;
+wire roundrobin5_grant;
+wire roundrobin5_ce;
+wire roundrobin6_request;
+wire roundrobin6_grant;
+wire roundrobin6_ce;
+wire roundrobin7_request;
+wire roundrobin7_grant;
+wire roundrobin7_ce;
+reg locked0 = 1'd0;
+reg locked1 = 1'd0;
+reg locked2 = 1'd0;
+reg locked3 = 1'd0;
+reg locked4 = 1'd0;
+reg locked5 = 1'd0;
+reg locked6 = 1'd0;
+reg locked7 = 1'd0;
+reg new_master_wdata_ready0 = 1'd0;
+reg new_master_wdata_ready1 = 1'd0;
+reg new_master_wdata_ready2 = 1'd0;
+reg new_master_rdata_valid0 = 1'd0;
+reg new_master_rdata_valid1 = 1'd0;
+reg new_master_rdata_valid2 = 1'd0;
+reg new_master_rdata_valid3 = 1'd0;
+reg new_master_rdata_valid4 = 1'd0;
+reg new_master_rdata_valid5 = 1'd0;
+reg new_master_rdata_valid6 = 1'd0;
+reg new_master_rdata_valid7 = 1'd0;
+reg new_master_rdata_valid8 = 1'd0;
+reg new_master_rdata_valid9 = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+wire csrbank0_init_done0_re;
+wire csrbank0_init_done0_r;
+wire csrbank0_init_done0_we;
+wire csrbank0_init_done0_w;
+wire csrbank0_init_error0_re;
+wire csrbank0_init_error0_r;
+wire csrbank0_init_error0_we;
+wire csrbank0_init_error0_w;
+reg csrbank0_sel = 1'd0;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+wire csrbank1_dfii_control0_re;
+wire [3:0] csrbank1_dfii_control0_r;
+wire csrbank1_dfii_control0_we;
+wire [3:0] csrbank1_dfii_control0_w;
+wire csrbank1_dfii_pi0_command0_re;
+wire [5:0] csrbank1_dfii_pi0_command0_r;
+wire csrbank1_dfii_pi0_command0_we;
+wire [5:0] csrbank1_dfii_pi0_command0_w;
+wire csrbank1_dfii_pi0_address0_re;
+wire [13:0] csrbank1_dfii_pi0_address0_r;
+wire csrbank1_dfii_pi0_address0_we;
+wire [13:0] csrbank1_dfii_pi0_address0_w;
+wire csrbank1_dfii_pi0_baddress0_re;
+wire [2:0] csrbank1_dfii_pi0_baddress0_r;
+wire csrbank1_dfii_pi0_baddress0_we;
+wire [2:0] csrbank1_dfii_pi0_baddress0_w;
+wire csrbank1_dfii_pi0_wrdata0_re;
+wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
+wire csrbank1_dfii_pi0_wrdata0_we;
+wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
+wire csrbank1_dfii_pi0_rddata_re;
+wire [31:0] csrbank1_dfii_pi0_rddata_r;
+wire csrbank1_dfii_pi0_rddata_we;
+wire [31:0] csrbank1_dfii_pi0_rddata_w;
+wire csrbank1_dfii_pi1_command0_re;
+wire [5:0] csrbank1_dfii_pi1_command0_r;
+wire csrbank1_dfii_pi1_command0_we;
+wire [5:0] csrbank1_dfii_pi1_command0_w;
+wire csrbank1_dfii_pi1_address0_re;
+wire [13:0] csrbank1_dfii_pi1_address0_r;
+wire csrbank1_dfii_pi1_address0_we;
+wire [13:0] csrbank1_dfii_pi1_address0_w;
+wire csrbank1_dfii_pi1_baddress0_re;
+wire [2:0] csrbank1_dfii_pi1_baddress0_r;
+wire csrbank1_dfii_pi1_baddress0_we;
+wire [2:0] csrbank1_dfii_pi1_baddress0_w;
+wire csrbank1_dfii_pi1_wrdata0_re;
+wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
+wire csrbank1_dfii_pi1_wrdata0_we;
+wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
+wire csrbank1_dfii_pi1_rddata_re;
+wire [31:0] csrbank1_dfii_pi1_rddata_r;
+wire csrbank1_dfii_pi1_rddata_we;
+wire [31:0] csrbank1_dfii_pi1_rddata_w;
+wire csrbank1_dfii_pi2_command0_re;
+wire [5:0] csrbank1_dfii_pi2_command0_r;
+wire csrbank1_dfii_pi2_command0_we;
+wire [5:0] csrbank1_dfii_pi2_command0_w;
+wire csrbank1_dfii_pi2_address0_re;
+wire [13:0] csrbank1_dfii_pi2_address0_r;
+wire csrbank1_dfii_pi2_address0_we;
+wire [13:0] csrbank1_dfii_pi2_address0_w;
+wire csrbank1_dfii_pi2_baddress0_re;
+wire [2:0] csrbank1_dfii_pi2_baddress0_r;
+wire csrbank1_dfii_pi2_baddress0_we;
+wire [2:0] csrbank1_dfii_pi2_baddress0_w;
+wire csrbank1_dfii_pi2_wrdata0_re;
+wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
+wire csrbank1_dfii_pi2_wrdata0_we;
+wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
+wire csrbank1_dfii_pi2_rddata_re;
+wire [31:0] csrbank1_dfii_pi2_rddata_r;
+wire csrbank1_dfii_pi2_rddata_we;
+wire [31:0] csrbank1_dfii_pi2_rddata_w;
+wire csrbank1_dfii_pi3_command0_re;
+wire [5:0] csrbank1_dfii_pi3_command0_r;
+wire csrbank1_dfii_pi3_command0_we;
+wire [5:0] csrbank1_dfii_pi3_command0_w;
+wire csrbank1_dfii_pi3_address0_re;
+wire [13:0] csrbank1_dfii_pi3_address0_r;
+wire csrbank1_dfii_pi3_address0_we;
+wire [13:0] csrbank1_dfii_pi3_address0_w;
+wire csrbank1_dfii_pi3_baddress0_re;
+wire [2:0] csrbank1_dfii_pi3_baddress0_r;
+wire csrbank1_dfii_pi3_baddress0_we;
+wire [2:0] csrbank1_dfii_pi3_baddress0_w;
+wire csrbank1_dfii_pi3_wrdata0_re;
+wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
+wire csrbank1_dfii_pi3_wrdata0_we;
+wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
+wire csrbank1_dfii_pi3_rddata_re;
+wire [31:0] csrbank1_dfii_pi3_rddata_r;
+wire csrbank1_dfii_pi3_rddata_we;
+wire [31:0] csrbank1_dfii_pi3_rddata_w;
+reg csrbank1_sel = 1'd0;
+wire [13:0] adr;
+wire we;
+wire [31:0] dat_w;
+wire [31:0] dat_r;
+wire [24:0] slice_proxy0;
+wire [24:0] slice_proxy1;
+wire [24:0] slice_proxy2;
+wire [24:0] slice_proxy3;
+wire [24:0] slice_proxy4;
+wire [24:0] slice_proxy5;
+wire [24:0] slice_proxy6;
+wire [24:0] slice_proxy7;
+wire [24:0] slice_proxy8;
+wire [24:0] slice_proxy9;
+wire [24:0] slice_proxy10;
+wire [24:0] slice_proxy11;
+wire [24:0] slice_proxy12;
+wire [24:0] slice_proxy13;
+wire [24:0] slice_proxy14;
+wire [24:0] slice_proxy15;
+reg comb_rhs_array_muxed0 = 1'd0;
+reg [13:0] comb_rhs_array_muxed1 = 14'd0;
+reg [2:0] comb_rhs_array_muxed2 = 3'd0;
+reg comb_rhs_array_muxed3 = 1'd0;
+reg comb_rhs_array_muxed4 = 1'd0;
+reg comb_rhs_array_muxed5 = 1'd0;
+reg comb_t_array_muxed0 = 1'd0;
+reg comb_t_array_muxed1 = 1'd0;
+reg comb_t_array_muxed2 = 1'd0;
+reg comb_rhs_array_muxed6 = 1'd0;
+reg [13:0] comb_rhs_array_muxed7 = 14'd0;
+reg [2:0] comb_rhs_array_muxed8 = 3'd0;
+reg comb_rhs_array_muxed9 = 1'd0;
+reg comb_rhs_array_muxed10 = 1'd0;
+reg comb_rhs_array_muxed11 = 1'd0;
+reg comb_t_array_muxed3 = 1'd0;
+reg comb_t_array_muxed4 = 1'd0;
+reg comb_t_array_muxed5 = 1'd0;
+reg [20:0] comb_rhs_array_muxed12 = 21'd0;
+reg comb_rhs_array_muxed13 = 1'd0;
+reg comb_rhs_array_muxed14 = 1'd0;
+reg [20:0] comb_rhs_array_muxed15 = 21'd0;
+reg comb_rhs_array_muxed16 = 1'd0;
+reg comb_rhs_array_muxed17 = 1'd0;
+reg [20:0] comb_rhs_array_muxed18 = 21'd0;
+reg comb_rhs_array_muxed19 = 1'd0;
+reg comb_rhs_array_muxed20 = 1'd0;
+reg [20:0] comb_rhs_array_muxed21 = 21'd0;
+reg comb_rhs_array_muxed22 = 1'd0;
+reg comb_rhs_array_muxed23 = 1'd0;
+reg [20:0] comb_rhs_array_muxed24 = 21'd0;
+reg comb_rhs_array_muxed25 = 1'd0;
+reg comb_rhs_array_muxed26 = 1'd0;
+reg [20:0] comb_rhs_array_muxed27 = 21'd0;
+reg comb_rhs_array_muxed28 = 1'd0;
+reg comb_rhs_array_muxed29 = 1'd0;
+reg [20:0] comb_rhs_array_muxed30 = 21'd0;
+reg comb_rhs_array_muxed31 = 1'd0;
+reg comb_rhs_array_muxed32 = 1'd0;
+reg [20:0] comb_rhs_array_muxed33 = 21'd0;
+reg comb_rhs_array_muxed34 = 1'd0;
+reg comb_rhs_array_muxed35 = 1'd0;
+reg [63:0] sync_basiclowerer_array_muxed0 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed1 = 64'd0;
+reg [63:0] sync_t_array_muxed0 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed2 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed3 = 64'd0;
+reg [63:0] sync_t_array_muxed1 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed4 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed5 = 64'd0;
+reg [63:0] sync_t_array_muxed2 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed6 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed7 = 64'd0;
+reg [63:0] sync_t_array_muxed3 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed8 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed9 = 64'd0;
+reg [63:0] sync_t_array_muxed4 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed10 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed11 = 64'd0;
+reg [63:0] sync_t_array_muxed5 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed12 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed13 = 64'd0;
+reg [63:0] sync_t_array_muxed6 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed14 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed15 = 64'd0;
+reg [63:0] sync_t_array_muxed7 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed16 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed17 = 64'd0;
+reg [63:0] sync_t_array_muxed8 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed18 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed19 = 64'd0;
+reg [63:0] sync_t_array_muxed9 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed20 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed21 = 64'd0;
+reg [63:0] sync_t_array_muxed10 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed22 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed23 = 64'd0;
+reg [63:0] sync_t_array_muxed11 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed24 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed25 = 64'd0;
+reg [63:0] sync_t_array_muxed12 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed26 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed27 = 64'd0;
+reg [63:0] sync_t_array_muxed13 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed28 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed29 = 64'd0;
+reg [63:0] sync_t_array_muxed14 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed30 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed31 = 64'd0;
+reg [63:0] sync_t_array_muxed15 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed32 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed33 = 64'd0;
+reg [63:0] sync_t_array_muxed16 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed34 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed35 = 64'd0;
+reg [63:0] sync_t_array_muxed17 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed36 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed37 = 64'd0;
+reg [63:0] sync_t_array_muxed18 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed38 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed39 = 64'd0;
+reg [63:0] sync_t_array_muxed19 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed40 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed41 = 64'd0;
+reg [63:0] sync_t_array_muxed20 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed42 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed43 = 64'd0;
+reg [63:0] sync_t_array_muxed21 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed44 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed45 = 64'd0;
+reg [63:0] sync_t_array_muxed22 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed46 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed47 = 64'd0;
+reg [63:0] sync_t_array_muxed23 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed48 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed49 = 64'd0;
+reg [63:0] sync_t_array_muxed24 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed50 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed51 = 64'd0;
+reg [63:0] sync_t_array_muxed25 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed52 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed53 = 64'd0;
+reg [63:0] sync_t_array_muxed26 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed54 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed55 = 64'd0;
+reg [63:0] sync_t_array_muxed27 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed56 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed57 = 64'd0;
+reg [63:0] sync_t_array_muxed28 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed58 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed59 = 64'd0;
+reg [63:0] sync_t_array_muxed29 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed60 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed61 = 64'd0;
+reg [63:0] sync_t_array_muxed30 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed62 = 64'd0;
+reg [63:0] sync_basiclowerer_array_muxed63 = 64'd0;
+reg [63:0] sync_t_array_muxed31 = 64'd0;
+reg [2:0] sync_rhs_array_muxed0 = 3'd0;
+reg [13:0] sync_rhs_array_muxed1 = 14'd0;
+reg sync_rhs_array_muxed2 = 1'd0;
+reg sync_rhs_array_muxed3 = 1'd0;
+reg sync_rhs_array_muxed4 = 1'd0;
+reg sync_rhs_array_muxed5 = 1'd0;
+reg sync_rhs_array_muxed6 = 1'd0;
+reg [2:0] sync_rhs_array_muxed7 = 3'd0;
+reg [13:0] sync_rhs_array_muxed8 = 14'd0;
+reg sync_rhs_array_muxed9 = 1'd0;
+reg sync_rhs_array_muxed10 = 1'd0;
+reg sync_rhs_array_muxed11 = 1'd0;
+reg sync_rhs_array_muxed12 = 1'd0;
+reg sync_rhs_array_muxed13 = 1'd0;
+reg [2:0] sync_rhs_array_muxed14 = 3'd0;
+reg [13:0] sync_rhs_array_muxed15 = 14'd0;
+reg sync_rhs_array_muxed16 = 1'd0;
+reg sync_rhs_array_muxed17 = 1'd0;
+reg sync_rhs_array_muxed18 = 1'd0;
+reg sync_rhs_array_muxed19 = 1'd0;
+reg sync_rhs_array_muxed20 = 1'd0;
+reg [2:0] sync_rhs_array_muxed21 = 3'd0;
+reg [13:0] sync_rhs_array_muxed22 = 14'd0;
+reg sync_rhs_array_muxed23 = 1'd0;
+reg sync_rhs_array_muxed24 = 1'd0;
+reg sync_rhs_array_muxed25 = 1'd0;
+reg sync_rhs_array_muxed26 = 1'd0;
+reg sync_rhs_array_muxed27 = 1'd0;
+
+assign init_done = init_done_storage;
+assign init_error = init_error_storage;
+assign wb_bus_adr = wb_ctrl_adr;
+assign wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wb_ctrl_sel;
+assign wb_bus_cyc = wb_ctrl_cyc;
+assign wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = wb_bus_ack;
+assign wb_bus_we = wb_ctrl_we;
+assign wb_bus_cti = wb_ctrl_cti;
+assign wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = wb_bus_err;
+assign user_clk = sys_clk;
+assign user_rst = sys_rst;
+assign user_port_cmd_valid = user_port_native_0_cmd_valid;
+assign user_port_native_0_cmd_ready = user_port_cmd_ready;
+assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign user_port_wdata_valid = user_port_native_0_wdata_valid;
+assign user_port_native_0_wdata_ready = user_port_wdata_ready;
+assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = user_port_rdata_valid;
+assign user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign litedramcore_dat_w = litedramcore_wishbone_dat_w;
+assign litedramcore_wishbone_dat_r = litedramcore_dat_r;
+always @(*) begin
+       next_state = 1'd0;
+       next_state = state;
+       case (state)
+               1'd1: begin
+                       next_state = 1'd0;
+               end
+               default: begin
+                       if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+                               next_state = 1'd1;
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_adr = 14'd0;
+       case (state)
+               1'd1: begin
+               end
+               default: begin
+                       if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+                               litedramcore_adr = litedramcore_wishbone_adr;
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_we = 1'd0;
+       case (state)
+               1'd1: begin
+               end
+               default: begin
+                       if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+                               litedramcore_we = litedramcore_wishbone_we;
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_wishbone_ack = 1'd0;
+       case (state)
+               1'd1: begin
+                       litedramcore_wishbone_ack = 1'd1;
+               end
+               default: begin
+               end
+       endcase
+end
+assign sys_clk = clk;
+assign por_clk = clk;
+assign sys_rst = int_rst;
+always @(*) begin
+       ddrphy_activates0 = 4'd0;
+       ddrphy_activates0[0] = ddrphy_dfiphasemodel0_activate;
+       ddrphy_activates0[1] = ddrphy_dfiphasemodel1_activate;
+       ddrphy_activates0[2] = ddrphy_dfiphasemodel2_activate;
+       ddrphy_activates0[3] = ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+       ddrphy_bankmodel0_activate = 1'd0;
+       case (ddrphy_activates0)
+               1'd1: begin
+                       ddrphy_bankmodel0_activate = (ddrphy_dfi_p0_bank == 1'd0);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel0_activate = (ddrphy_dfi_p1_bank == 1'd0);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel0_activate = (ddrphy_dfi_p2_bank == 1'd0);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel0_activate = (ddrphy_dfi_p3_bank == 1'd0);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel0_activate_row = 14'd0;
+       case (ddrphy_activates0)
+               1'd1: begin
+                       ddrphy_bankmodel0_activate_row = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel0_activate_row = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel0_activate_row = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel0_activate_row = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_precharges0 = 4'd0;
+       ddrphy_precharges0[0] = ddrphy_dfiphasemodel0_precharge;
+       ddrphy_precharges0[1] = ddrphy_dfiphasemodel1_precharge;
+       ddrphy_precharges0[2] = ddrphy_dfiphasemodel2_precharge;
+       ddrphy_precharges0[3] = ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+       ddrphy_bankmodel0_precharge = 1'd0;
+       case (ddrphy_precharges0)
+               1'd1: begin
+                       ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfi_p0_address[10]);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfi_p1_address[10]);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfi_p2_address[10]);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfi_p3_address[10]);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_writes0 = 4'd0;
+       ddrphy_writes0[0] = ddrphy_dfiphasemodel0_write;
+       ddrphy_writes0[1] = ddrphy_dfiphasemodel1_write;
+       ddrphy_writes0[2] = ddrphy_dfiphasemodel2_write;
+       ddrphy_writes0[3] = ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+       ddrphy_bank_write0 = 1'd0;
+       case (ddrphy_writes0)
+               1'd1: begin
+                       ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0);
+               end
+               2'd2: begin
+                       ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0);
+               end
+               3'd4: begin
+                       ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0);
+               end
+               4'd8: begin
+                       ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bank_write_col0 = 10'd0;
+       case (ddrphy_writes0)
+               1'd1: begin
+                       ddrphy_bank_write_col0 = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bank_write_col0 = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bank_write_col0 = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bank_write_col0 = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+assign ddrphy_bankmodel0_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
+assign ddrphy_bankmodel0_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
+assign ddrphy_bankmodel0_write = ddrphy_new_bank_write1;
+assign ddrphy_bankmodel0_write_col = ddrphy_new_bank_write_col1;
+always @(*) begin
+       ddrphy_reads0 = 4'd0;
+       ddrphy_reads0[0] = ddrphy_dfiphasemodel0_read;
+       ddrphy_reads0[1] = ddrphy_dfiphasemodel1_read;
+       ddrphy_reads0[2] = ddrphy_dfiphasemodel2_read;
+       ddrphy_reads0[3] = ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+       ddrphy_bankmodel0_read_col = 10'd0;
+       case (ddrphy_reads0)
+               1'd1: begin
+                       ddrphy_bankmodel0_read_col = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel0_read_col = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel0_read_col = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel0_read_col = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel0_read = 1'd0;
+       case (ddrphy_reads0)
+               1'd1: begin
+                       ddrphy_bankmodel0_read = (ddrphy_dfi_p0_bank == 1'd0);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel0_read = (ddrphy_dfi_p1_bank == 1'd0);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel0_read = (ddrphy_dfi_p2_bank == 1'd0);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel0_read = (ddrphy_dfi_p3_bank == 1'd0);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_activates1 = 4'd0;
+       ddrphy_activates1[0] = ddrphy_dfiphasemodel0_activate;
+       ddrphy_activates1[1] = ddrphy_dfiphasemodel1_activate;
+       ddrphy_activates1[2] = ddrphy_dfiphasemodel2_activate;
+       ddrphy_activates1[3] = ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+       ddrphy_bankmodel1_activate = 1'd0;
+       case (ddrphy_activates1)
+               1'd1: begin
+                       ddrphy_bankmodel1_activate = (ddrphy_dfi_p0_bank == 1'd1);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel1_activate = (ddrphy_dfi_p1_bank == 1'd1);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel1_activate = (ddrphy_dfi_p2_bank == 1'd1);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel1_activate = (ddrphy_dfi_p3_bank == 1'd1);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel1_activate_row = 14'd0;
+       case (ddrphy_activates1)
+               1'd1: begin
+                       ddrphy_bankmodel1_activate_row = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel1_activate_row = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel1_activate_row = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel1_activate_row = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_precharges1 = 4'd0;
+       ddrphy_precharges1[0] = ddrphy_dfiphasemodel0_precharge;
+       ddrphy_precharges1[1] = ddrphy_dfiphasemodel1_precharge;
+       ddrphy_precharges1[2] = ddrphy_dfiphasemodel2_precharge;
+       ddrphy_precharges1[3] = ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+       ddrphy_bankmodel1_precharge = 1'd0;
+       case (ddrphy_precharges1)
+               1'd1: begin
+                       ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfi_p0_address[10]);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfi_p1_address[10]);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfi_p2_address[10]);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfi_p3_address[10]);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_writes1 = 4'd0;
+       ddrphy_writes1[0] = ddrphy_dfiphasemodel0_write;
+       ddrphy_writes1[1] = ddrphy_dfiphasemodel1_write;
+       ddrphy_writes1[2] = ddrphy_dfiphasemodel2_write;
+       ddrphy_writes1[3] = ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+       ddrphy_bank_write1 = 1'd0;
+       case (ddrphy_writes1)
+               1'd1: begin
+                       ddrphy_bank_write1 = (ddrphy_dfi_p0_bank == 1'd1);
+               end
+               2'd2: begin
+                       ddrphy_bank_write1 = (ddrphy_dfi_p1_bank == 1'd1);
+               end
+               3'd4: begin
+                       ddrphy_bank_write1 = (ddrphy_dfi_p2_bank == 1'd1);
+               end
+               4'd8: begin
+                       ddrphy_bank_write1 = (ddrphy_dfi_p3_bank == 1'd1);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bank_write_col1 = 10'd0;
+       case (ddrphy_writes1)
+               1'd1: begin
+                       ddrphy_bank_write_col1 = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bank_write_col1 = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bank_write_col1 = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bank_write_col1 = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+assign ddrphy_bankmodel1_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
+assign ddrphy_bankmodel1_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
+assign ddrphy_bankmodel1_write = ddrphy_new_bank_write3;
+assign ddrphy_bankmodel1_write_col = ddrphy_new_bank_write_col3;
+always @(*) begin
+       ddrphy_reads1 = 4'd0;
+       ddrphy_reads1[0] = ddrphy_dfiphasemodel0_read;
+       ddrphy_reads1[1] = ddrphy_dfiphasemodel1_read;
+       ddrphy_reads1[2] = ddrphy_dfiphasemodel2_read;
+       ddrphy_reads1[3] = ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+       ddrphy_bankmodel1_read = 1'd0;
+       case (ddrphy_reads1)
+               1'd1: begin
+                       ddrphy_bankmodel1_read = (ddrphy_dfi_p0_bank == 1'd1);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel1_read = (ddrphy_dfi_p1_bank == 1'd1);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel1_read = (ddrphy_dfi_p2_bank == 1'd1);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel1_read = (ddrphy_dfi_p3_bank == 1'd1);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel1_read_col = 10'd0;
+       case (ddrphy_reads1)
+               1'd1: begin
+                       ddrphy_bankmodel1_read_col = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel1_read_col = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel1_read_col = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel1_read_col = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_activates2 = 4'd0;
+       ddrphy_activates2[0] = ddrphy_dfiphasemodel0_activate;
+       ddrphy_activates2[1] = ddrphy_dfiphasemodel1_activate;
+       ddrphy_activates2[2] = ddrphy_dfiphasemodel2_activate;
+       ddrphy_activates2[3] = ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+       ddrphy_bankmodel2_activate_row = 14'd0;
+       case (ddrphy_activates2)
+               1'd1: begin
+                       ddrphy_bankmodel2_activate_row = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel2_activate_row = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel2_activate_row = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel2_activate_row = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel2_activate = 1'd0;
+       case (ddrphy_activates2)
+               1'd1: begin
+                       ddrphy_bankmodel2_activate = (ddrphy_dfi_p0_bank == 2'd2);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel2_activate = (ddrphy_dfi_p1_bank == 2'd2);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel2_activate = (ddrphy_dfi_p2_bank == 2'd2);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel2_activate = (ddrphy_dfi_p3_bank == 2'd2);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_precharges2 = 4'd0;
+       ddrphy_precharges2[0] = ddrphy_dfiphasemodel0_precharge;
+       ddrphy_precharges2[1] = ddrphy_dfiphasemodel1_precharge;
+       ddrphy_precharges2[2] = ddrphy_dfiphasemodel2_precharge;
+       ddrphy_precharges2[3] = ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+       ddrphy_bankmodel2_precharge = 1'd0;
+       case (ddrphy_precharges2)
+               1'd1: begin
+                       ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfi_p0_address[10]);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfi_p1_address[10]);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfi_p2_address[10]);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfi_p3_address[10]);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_writes2 = 4'd0;
+       ddrphy_writes2[0] = ddrphy_dfiphasemodel0_write;
+       ddrphy_writes2[1] = ddrphy_dfiphasemodel1_write;
+       ddrphy_writes2[2] = ddrphy_dfiphasemodel2_write;
+       ddrphy_writes2[3] = ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+       ddrphy_bank_write2 = 1'd0;
+       case (ddrphy_writes2)
+               1'd1: begin
+                       ddrphy_bank_write2 = (ddrphy_dfi_p0_bank == 2'd2);
+               end
+               2'd2: begin
+                       ddrphy_bank_write2 = (ddrphy_dfi_p1_bank == 2'd2);
+               end
+               3'd4: begin
+                       ddrphy_bank_write2 = (ddrphy_dfi_p2_bank == 2'd2);
+               end
+               4'd8: begin
+                       ddrphy_bank_write2 = (ddrphy_dfi_p3_bank == 2'd2);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bank_write_col2 = 10'd0;
+       case (ddrphy_writes2)
+               1'd1: begin
+                       ddrphy_bank_write_col2 = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bank_write_col2 = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bank_write_col2 = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bank_write_col2 = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+assign ddrphy_bankmodel2_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
+assign ddrphy_bankmodel2_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
+assign ddrphy_bankmodel2_write = ddrphy_new_bank_write5;
+assign ddrphy_bankmodel2_write_col = ddrphy_new_bank_write_col5;
+always @(*) begin
+       ddrphy_reads2 = 4'd0;
+       ddrphy_reads2[0] = ddrphy_dfiphasemodel0_read;
+       ddrphy_reads2[1] = ddrphy_dfiphasemodel1_read;
+       ddrphy_reads2[2] = ddrphy_dfiphasemodel2_read;
+       ddrphy_reads2[3] = ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+       ddrphy_bankmodel2_read = 1'd0;
+       case (ddrphy_reads2)
+               1'd1: begin
+                       ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel2_read_col = 10'd0;
+       case (ddrphy_reads2)
+               1'd1: begin
+                       ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_activates3 = 4'd0;
+       ddrphy_activates3[0] = ddrphy_dfiphasemodel0_activate;
+       ddrphy_activates3[1] = ddrphy_dfiphasemodel1_activate;
+       ddrphy_activates3[2] = ddrphy_dfiphasemodel2_activate;
+       ddrphy_activates3[3] = ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+       ddrphy_bankmodel3_activate = 1'd0;
+       case (ddrphy_activates3)
+               1'd1: begin
+                       ddrphy_bankmodel3_activate = (ddrphy_dfi_p0_bank == 2'd3);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel3_activate = (ddrphy_dfi_p1_bank == 2'd3);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel3_activate = (ddrphy_dfi_p2_bank == 2'd3);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel3_activate = (ddrphy_dfi_p3_bank == 2'd3);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel3_activate_row = 14'd0;
+       case (ddrphy_activates3)
+               1'd1: begin
+                       ddrphy_bankmodel3_activate_row = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel3_activate_row = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel3_activate_row = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel3_activate_row = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_precharges3 = 4'd0;
+       ddrphy_precharges3[0] = ddrphy_dfiphasemodel0_precharge;
+       ddrphy_precharges3[1] = ddrphy_dfiphasemodel1_precharge;
+       ddrphy_precharges3[2] = ddrphy_dfiphasemodel2_precharge;
+       ddrphy_precharges3[3] = ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+       ddrphy_bankmodel3_precharge = 1'd0;
+       case (ddrphy_precharges3)
+               1'd1: begin
+                       ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfi_p0_address[10]);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfi_p1_address[10]);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfi_p2_address[10]);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfi_p3_address[10]);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_writes3 = 4'd0;
+       ddrphy_writes3[0] = ddrphy_dfiphasemodel0_write;
+       ddrphy_writes3[1] = ddrphy_dfiphasemodel1_write;
+       ddrphy_writes3[2] = ddrphy_dfiphasemodel2_write;
+       ddrphy_writes3[3] = ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+       ddrphy_bank_write_col3 = 10'd0;
+       case (ddrphy_writes3)
+               1'd1: begin
+                       ddrphy_bank_write_col3 = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bank_write_col3 = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bank_write_col3 = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bank_write_col3 = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bank_write3 = 1'd0;
+       case (ddrphy_writes3)
+               1'd1: begin
+                       ddrphy_bank_write3 = (ddrphy_dfi_p0_bank == 2'd3);
+               end
+               2'd2: begin
+                       ddrphy_bank_write3 = (ddrphy_dfi_p1_bank == 2'd3);
+               end
+               3'd4: begin
+                       ddrphy_bank_write3 = (ddrphy_dfi_p2_bank == 2'd3);
+               end
+               4'd8: begin
+                       ddrphy_bank_write3 = (ddrphy_dfi_p3_bank == 2'd3);
+               end
+       endcase
+end
+assign ddrphy_bankmodel3_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
+assign ddrphy_bankmodel3_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
+assign ddrphy_bankmodel3_write = ddrphy_new_bank_write7;
+assign ddrphy_bankmodel3_write_col = ddrphy_new_bank_write_col7;
+always @(*) begin
+       ddrphy_reads3 = 4'd0;
+       ddrphy_reads3[0] = ddrphy_dfiphasemodel0_read;
+       ddrphy_reads3[1] = ddrphy_dfiphasemodel1_read;
+       ddrphy_reads3[2] = ddrphy_dfiphasemodel2_read;
+       ddrphy_reads3[3] = ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+       ddrphy_bankmodel3_read = 1'd0;
+       case (ddrphy_reads3)
+               1'd1: begin
+                       ddrphy_bankmodel3_read = (ddrphy_dfi_p0_bank == 2'd3);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel3_read = (ddrphy_dfi_p1_bank == 2'd3);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel3_read = (ddrphy_dfi_p2_bank == 2'd3);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel3_read = (ddrphy_dfi_p3_bank == 2'd3);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel3_read_col = 10'd0;
+       case (ddrphy_reads3)
+               1'd1: begin
+                       ddrphy_bankmodel3_read_col = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel3_read_col = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel3_read_col = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel3_read_col = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_activates4 = 4'd0;
+       ddrphy_activates4[0] = ddrphy_dfiphasemodel0_activate;
+       ddrphy_activates4[1] = ddrphy_dfiphasemodel1_activate;
+       ddrphy_activates4[2] = ddrphy_dfiphasemodel2_activate;
+       ddrphy_activates4[3] = ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+       ddrphy_bankmodel4_activate = 1'd0;
+       case (ddrphy_activates4)
+               1'd1: begin
+                       ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel4_activate_row = 14'd0;
+       case (ddrphy_activates4)
+               1'd1: begin
+                       ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_precharges4 = 4'd0;
+       ddrphy_precharges4[0] = ddrphy_dfiphasemodel0_precharge;
+       ddrphy_precharges4[1] = ddrphy_dfiphasemodel1_precharge;
+       ddrphy_precharges4[2] = ddrphy_dfiphasemodel2_precharge;
+       ddrphy_precharges4[3] = ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+       ddrphy_bankmodel4_precharge = 1'd0;
+       case (ddrphy_precharges4)
+               1'd1: begin
+                       ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfi_p0_address[10]);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfi_p1_address[10]);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfi_p2_address[10]);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfi_p3_address[10]);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_writes4 = 4'd0;
+       ddrphy_writes4[0] = ddrphy_dfiphasemodel0_write;
+       ddrphy_writes4[1] = ddrphy_dfiphasemodel1_write;
+       ddrphy_writes4[2] = ddrphy_dfiphasemodel2_write;
+       ddrphy_writes4[3] = ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+       ddrphy_bank_write4 = 1'd0;
+       case (ddrphy_writes4)
+               1'd1: begin
+                       ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4);
+               end
+               2'd2: begin
+                       ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4);
+               end
+               3'd4: begin
+                       ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4);
+               end
+               4'd8: begin
+                       ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bank_write_col4 = 10'd0;
+       case (ddrphy_writes4)
+               1'd1: begin
+                       ddrphy_bank_write_col4 = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bank_write_col4 = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bank_write_col4 = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bank_write_col4 = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+assign ddrphy_bankmodel4_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
+assign ddrphy_bankmodel4_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
+assign ddrphy_bankmodel4_write = ddrphy_new_bank_write9;
+assign ddrphy_bankmodel4_write_col = ddrphy_new_bank_write_col9;
+always @(*) begin
+       ddrphy_reads4 = 4'd0;
+       ddrphy_reads4[0] = ddrphy_dfiphasemodel0_read;
+       ddrphy_reads4[1] = ddrphy_dfiphasemodel1_read;
+       ddrphy_reads4[2] = ddrphy_dfiphasemodel2_read;
+       ddrphy_reads4[3] = ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+       ddrphy_bankmodel4_read = 1'd0;
+       case (ddrphy_reads4)
+               1'd1: begin
+                       ddrphy_bankmodel4_read = (ddrphy_dfi_p0_bank == 3'd4);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel4_read = (ddrphy_dfi_p1_bank == 3'd4);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel4_read = (ddrphy_dfi_p2_bank == 3'd4);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel4_read = (ddrphy_dfi_p3_bank == 3'd4);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel4_read_col = 10'd0;
+       case (ddrphy_reads4)
+               1'd1: begin
+                       ddrphy_bankmodel4_read_col = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel4_read_col = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel4_read_col = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel4_read_col = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_activates5 = 4'd0;
+       ddrphy_activates5[0] = ddrphy_dfiphasemodel0_activate;
+       ddrphy_activates5[1] = ddrphy_dfiphasemodel1_activate;
+       ddrphy_activates5[2] = ddrphy_dfiphasemodel2_activate;
+       ddrphy_activates5[3] = ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+       ddrphy_bankmodel5_activate = 1'd0;
+       case (ddrphy_activates5)
+               1'd1: begin
+                       ddrphy_bankmodel5_activate = (ddrphy_dfi_p0_bank == 3'd5);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel5_activate = (ddrphy_dfi_p1_bank == 3'd5);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel5_activate = (ddrphy_dfi_p2_bank == 3'd5);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel5_activate = (ddrphy_dfi_p3_bank == 3'd5);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel5_activate_row = 14'd0;
+       case (ddrphy_activates5)
+               1'd1: begin
+                       ddrphy_bankmodel5_activate_row = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel5_activate_row = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel5_activate_row = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel5_activate_row = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_precharges5 = 4'd0;
+       ddrphy_precharges5[0] = ddrphy_dfiphasemodel0_precharge;
+       ddrphy_precharges5[1] = ddrphy_dfiphasemodel1_precharge;
+       ddrphy_precharges5[2] = ddrphy_dfiphasemodel2_precharge;
+       ddrphy_precharges5[3] = ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+       ddrphy_bankmodel5_precharge = 1'd0;
+       case (ddrphy_precharges5)
+               1'd1: begin
+                       ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfi_p0_address[10]);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfi_p1_address[10]);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfi_p2_address[10]);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfi_p3_address[10]);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_writes5 = 4'd0;
+       ddrphy_writes5[0] = ddrphy_dfiphasemodel0_write;
+       ddrphy_writes5[1] = ddrphy_dfiphasemodel1_write;
+       ddrphy_writes5[2] = ddrphy_dfiphasemodel2_write;
+       ddrphy_writes5[3] = ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+       ddrphy_bank_write5 = 1'd0;
+       case (ddrphy_writes5)
+               1'd1: begin
+                       ddrphy_bank_write5 = (ddrphy_dfi_p0_bank == 3'd5);
+               end
+               2'd2: begin
+                       ddrphy_bank_write5 = (ddrphy_dfi_p1_bank == 3'd5);
+               end
+               3'd4: begin
+                       ddrphy_bank_write5 = (ddrphy_dfi_p2_bank == 3'd5);
+               end
+               4'd8: begin
+                       ddrphy_bank_write5 = (ddrphy_dfi_p3_bank == 3'd5);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bank_write_col5 = 10'd0;
+       case (ddrphy_writes5)
+               1'd1: begin
+                       ddrphy_bank_write_col5 = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bank_write_col5 = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bank_write_col5 = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bank_write_col5 = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+assign ddrphy_bankmodel5_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
+assign ddrphy_bankmodel5_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
+assign ddrphy_bankmodel5_write = ddrphy_new_bank_write11;
+assign ddrphy_bankmodel5_write_col = ddrphy_new_bank_write_col11;
+always @(*) begin
+       ddrphy_reads5 = 4'd0;
+       ddrphy_reads5[0] = ddrphy_dfiphasemodel0_read;
+       ddrphy_reads5[1] = ddrphy_dfiphasemodel1_read;
+       ddrphy_reads5[2] = ddrphy_dfiphasemodel2_read;
+       ddrphy_reads5[3] = ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+       ddrphy_bankmodel5_read_col = 10'd0;
+       case (ddrphy_reads5)
+               1'd1: begin
+                       ddrphy_bankmodel5_read_col = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel5_read_col = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel5_read_col = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel5_read_col = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel5_read = 1'd0;
+       case (ddrphy_reads5)
+               1'd1: begin
+                       ddrphy_bankmodel5_read = (ddrphy_dfi_p0_bank == 3'd5);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel5_read = (ddrphy_dfi_p1_bank == 3'd5);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel5_read = (ddrphy_dfi_p2_bank == 3'd5);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel5_read = (ddrphy_dfi_p3_bank == 3'd5);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_activates6 = 4'd0;
+       ddrphy_activates6[0] = ddrphy_dfiphasemodel0_activate;
+       ddrphy_activates6[1] = ddrphy_dfiphasemodel1_activate;
+       ddrphy_activates6[2] = ddrphy_dfiphasemodel2_activate;
+       ddrphy_activates6[3] = ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+       ddrphy_bankmodel6_activate = 1'd0;
+       case (ddrphy_activates6)
+               1'd1: begin
+                       ddrphy_bankmodel6_activate = (ddrphy_dfi_p0_bank == 3'd6);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel6_activate = (ddrphy_dfi_p1_bank == 3'd6);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel6_activate = (ddrphy_dfi_p2_bank == 3'd6);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel6_activate = (ddrphy_dfi_p3_bank == 3'd6);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel6_activate_row = 14'd0;
+       case (ddrphy_activates6)
+               1'd1: begin
+                       ddrphy_bankmodel6_activate_row = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel6_activate_row = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel6_activate_row = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel6_activate_row = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_precharges6 = 4'd0;
+       ddrphy_precharges6[0] = ddrphy_dfiphasemodel0_precharge;
+       ddrphy_precharges6[1] = ddrphy_dfiphasemodel1_precharge;
+       ddrphy_precharges6[2] = ddrphy_dfiphasemodel2_precharge;
+       ddrphy_precharges6[3] = ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+       ddrphy_bankmodel6_precharge = 1'd0;
+       case (ddrphy_precharges6)
+               1'd1: begin
+                       ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfi_p0_address[10]);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfi_p1_address[10]);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfi_p2_address[10]);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfi_p3_address[10]);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_writes6 = 4'd0;
+       ddrphy_writes6[0] = ddrphy_dfiphasemodel0_write;
+       ddrphy_writes6[1] = ddrphy_dfiphasemodel1_write;
+       ddrphy_writes6[2] = ddrphy_dfiphasemodel2_write;
+       ddrphy_writes6[3] = ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+       ddrphy_bank_write6 = 1'd0;
+       case (ddrphy_writes6)
+               1'd1: begin
+                       ddrphy_bank_write6 = (ddrphy_dfi_p0_bank == 3'd6);
+               end
+               2'd2: begin
+                       ddrphy_bank_write6 = (ddrphy_dfi_p1_bank == 3'd6);
+               end
+               3'd4: begin
+                       ddrphy_bank_write6 = (ddrphy_dfi_p2_bank == 3'd6);
+               end
+               4'd8: begin
+                       ddrphy_bank_write6 = (ddrphy_dfi_p3_bank == 3'd6);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bank_write_col6 = 10'd0;
+       case (ddrphy_writes6)
+               1'd1: begin
+                       ddrphy_bank_write_col6 = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bank_write_col6 = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bank_write_col6 = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bank_write_col6 = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+assign ddrphy_bankmodel6_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
+assign ddrphy_bankmodel6_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
+assign ddrphy_bankmodel6_write = ddrphy_new_bank_write13;
+assign ddrphy_bankmodel6_write_col = ddrphy_new_bank_write_col13;
+always @(*) begin
+       ddrphy_reads6 = 4'd0;
+       ddrphy_reads6[0] = ddrphy_dfiphasemodel0_read;
+       ddrphy_reads6[1] = ddrphy_dfiphasemodel1_read;
+       ddrphy_reads6[2] = ddrphy_dfiphasemodel2_read;
+       ddrphy_reads6[3] = ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+       ddrphy_bankmodel6_read = 1'd0;
+       case (ddrphy_reads6)
+               1'd1: begin
+                       ddrphy_bankmodel6_read = (ddrphy_dfi_p0_bank == 3'd6);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel6_read = (ddrphy_dfi_p1_bank == 3'd6);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel6_read = (ddrphy_dfi_p2_bank == 3'd6);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel6_read = (ddrphy_dfi_p3_bank == 3'd6);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel6_read_col = 10'd0;
+       case (ddrphy_reads6)
+               1'd1: begin
+                       ddrphy_bankmodel6_read_col = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel6_read_col = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel6_read_col = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel6_read_col = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_activates7 = 4'd0;
+       ddrphy_activates7[0] = ddrphy_dfiphasemodel0_activate;
+       ddrphy_activates7[1] = ddrphy_dfiphasemodel1_activate;
+       ddrphy_activates7[2] = ddrphy_dfiphasemodel2_activate;
+       ddrphy_activates7[3] = ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+       ddrphy_bankmodel7_activate_row = 14'd0;
+       case (ddrphy_activates7)
+               1'd1: begin
+                       ddrphy_bankmodel7_activate_row = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel7_activate_row = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel7_activate_row = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel7_activate_row = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel7_activate = 1'd0;
+       case (ddrphy_activates7)
+               1'd1: begin
+                       ddrphy_bankmodel7_activate = (ddrphy_dfi_p0_bank == 3'd7);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel7_activate = (ddrphy_dfi_p1_bank == 3'd7);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel7_activate = (ddrphy_dfi_p2_bank == 3'd7);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel7_activate = (ddrphy_dfi_p3_bank == 3'd7);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_precharges7 = 4'd0;
+       ddrphy_precharges7[0] = ddrphy_dfiphasemodel0_precharge;
+       ddrphy_precharges7[1] = ddrphy_dfiphasemodel1_precharge;
+       ddrphy_precharges7[2] = ddrphy_dfiphasemodel2_precharge;
+       ddrphy_precharges7[3] = ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+       ddrphy_bankmodel7_precharge = 1'd0;
+       case (ddrphy_precharges7)
+               1'd1: begin
+                       ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfi_p0_address[10]);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfi_p1_address[10]);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfi_p2_address[10]);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfi_p3_address[10]);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_writes7 = 4'd0;
+       ddrphy_writes7[0] = ddrphy_dfiphasemodel0_write;
+       ddrphy_writes7[1] = ddrphy_dfiphasemodel1_write;
+       ddrphy_writes7[2] = ddrphy_dfiphasemodel2_write;
+       ddrphy_writes7[3] = ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+       ddrphy_bank_write_col7 = 10'd0;
+       case (ddrphy_writes7)
+               1'd1: begin
+                       ddrphy_bank_write_col7 = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bank_write_col7 = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bank_write_col7 = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bank_write_col7 = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bank_write7 = 1'd0;
+       case (ddrphy_writes7)
+               1'd1: begin
+                       ddrphy_bank_write7 = (ddrphy_dfi_p0_bank == 3'd7);
+               end
+               2'd2: begin
+                       ddrphy_bank_write7 = (ddrphy_dfi_p1_bank == 3'd7);
+               end
+               3'd4: begin
+                       ddrphy_bank_write7 = (ddrphy_dfi_p2_bank == 3'd7);
+               end
+               4'd8: begin
+                       ddrphy_bank_write7 = (ddrphy_dfi_p3_bank == 3'd7);
+               end
+       endcase
+end
+assign ddrphy_bankmodel7_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata};
+assign ddrphy_bankmodel7_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask};
+assign ddrphy_bankmodel7_write = ddrphy_new_bank_write15;
+assign ddrphy_bankmodel7_write_col = ddrphy_new_bank_write_col15;
+always @(*) begin
+       ddrphy_reads7 = 4'd0;
+       ddrphy_reads7[0] = ddrphy_dfiphasemodel0_read;
+       ddrphy_reads7[1] = ddrphy_dfiphasemodel1_read;
+       ddrphy_reads7[2] = ddrphy_dfiphasemodel2_read;
+       ddrphy_reads7[3] = ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+       ddrphy_bankmodel7_read = 1'd0;
+       case (ddrphy_reads7)
+               1'd1: begin
+                       ddrphy_bankmodel7_read = (ddrphy_dfi_p0_bank == 3'd7);
+               end
+               2'd2: begin
+                       ddrphy_bankmodel7_read = (ddrphy_dfi_p1_bank == 3'd7);
+               end
+               3'd4: begin
+                       ddrphy_bankmodel7_read = (ddrphy_dfi_p2_bank == 3'd7);
+               end
+               4'd8: begin
+                       ddrphy_bankmodel7_read = (ddrphy_dfi_p3_bank == 3'd7);
+               end
+       endcase
+end
+always @(*) begin
+       ddrphy_bankmodel7_read_col = 10'd0;
+       case (ddrphy_reads7)
+               1'd1: begin
+                       ddrphy_bankmodel7_read_col = ddrphy_dfi_p0_address;
+               end
+               2'd2: begin
+                       ddrphy_bankmodel7_read_col = ddrphy_dfi_p1_address;
+               end
+               3'd4: begin
+                       ddrphy_bankmodel7_read_col = ddrphy_dfi_p2_address;
+               end
+               4'd8: begin
+                       ddrphy_bankmodel7_read_col = ddrphy_dfi_p3_address;
+               end
+       endcase
+end
+assign ddrphy_banks_read = (((((((ddrphy_bankmodel0_read | ddrphy_bankmodel1_read) | ddrphy_bankmodel2_read) | ddrphy_bankmodel3_read) | ddrphy_bankmodel4_read) | ddrphy_bankmodel5_read) | ddrphy_bankmodel6_read) | ddrphy_bankmodel7_read);
+assign ddrphy_banks_read_data = (((((((ddrphy_bankmodel0_read_data | ddrphy_bankmodel1_read_data) | ddrphy_bankmodel2_read_data) | ddrphy_bankmodel3_read_data) | ddrphy_bankmodel4_read_data) | ddrphy_bankmodel5_read_data) | ddrphy_bankmodel6_read_data) | ddrphy_bankmodel7_read_data);
+assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8;
+assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8;
+assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8;
+assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8;
+assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8;
+assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8;
+assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8;
+assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8;
+always @(*) begin
+       ddrphy_dfiphasemodel0_activate = 1'd0;
+       if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin
+               ddrphy_dfiphasemodel0_activate = ddrphy_dfi_p0_we_n;
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel0_precharge = 1'd0;
+       if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin
+               ddrphy_dfiphasemodel0_precharge = (~ddrphy_dfi_p0_we_n);
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel0_read = 1'd0;
+       if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin
+               ddrphy_dfiphasemodel0_read = ddrphy_dfi_p0_we_n;
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel0_write = 1'd0;
+       if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin
+               ddrphy_dfiphasemodel0_write = (~ddrphy_dfi_p0_we_n);
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel1_activate = 1'd0;
+       if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin
+               ddrphy_dfiphasemodel1_activate = ddrphy_dfi_p1_we_n;
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel1_precharge = 1'd0;
+       if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin
+               ddrphy_dfiphasemodel1_precharge = (~ddrphy_dfi_p1_we_n);
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel1_write = 1'd0;
+       if ((((~ddrphy_dfi_p1_cs_n) & ddrphy_dfi_p1_ras_n) & (~ddrphy_dfi_p1_cas_n))) begin
+               ddrphy_dfiphasemodel1_write = (~ddrphy_dfi_p1_we_n);
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel1_read = 1'd0;
+       if ((((~ddrphy_dfi_p1_cs_n) & ddrphy_dfi_p1_ras_n) & (~ddrphy_dfi_p1_cas_n))) begin
+               ddrphy_dfiphasemodel1_read = ddrphy_dfi_p1_we_n;
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel2_precharge = 1'd0;
+       if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin
+               ddrphy_dfiphasemodel2_precharge = (~ddrphy_dfi_p2_we_n);
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel2_activate = 1'd0;
+       if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin
+               ddrphy_dfiphasemodel2_activate = ddrphy_dfi_p2_we_n;
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel2_write = 1'd0;
+       if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin
+               ddrphy_dfiphasemodel2_write = (~ddrphy_dfi_p2_we_n);
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel2_read = 1'd0;
+       if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin
+               ddrphy_dfiphasemodel2_read = ddrphy_dfi_p2_we_n;
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel3_activate = 1'd0;
+       if ((((~ddrphy_dfi_p3_cs_n) & (~ddrphy_dfi_p3_ras_n)) & ddrphy_dfi_p3_cas_n)) begin
+               ddrphy_dfiphasemodel3_activate = ddrphy_dfi_p3_we_n;
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel3_precharge = 1'd0;
+       if ((((~ddrphy_dfi_p3_cs_n) & (~ddrphy_dfi_p3_ras_n)) & ddrphy_dfi_p3_cas_n)) begin
+               ddrphy_dfiphasemodel3_precharge = (~ddrphy_dfi_p3_we_n);
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel3_write = 1'd0;
+       if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin
+               ddrphy_dfiphasemodel3_write = (~ddrphy_dfi_p3_we_n);
+       end
+end
+always @(*) begin
+       ddrphy_dfiphasemodel3_read = 1'd0;
+       if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin
+               ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n;
+       end
+end
+assign ddrphy_dfitimingschecker_ps0 = ((ddrphy_dfitimingschecker_cnt + 1'd0) * 12'd2500);
+assign ddrphy_dfitimingschecker_state0 = {ddrphy_dfi_p0_cs_n, ddrphy_dfi_p0_ras_n, ddrphy_dfi_p0_cas_n, ddrphy_dfi_p0_we_n};
+assign ddrphy_dfitimingschecker_all_banks0 = ((ddrphy_dfitimingschecker_state0 == 1'd1) | ((ddrphy_dfitimingschecker_state0 == 2'd2) & ddrphy_dfi_p0_address[10]));
+always @(*) begin
+       ddrphy_dfitimingschecker_ref_issued = 4'd0;
+       ddrphy_dfitimingschecker_ref_issued[0] = (ddrphy_dfitimingschecker_state0 == 1'd1);
+       ddrphy_dfitimingschecker_ref_issued[1] = (ddrphy_dfitimingschecker_state1 == 1'd1);
+       ddrphy_dfitimingschecker_ref_issued[2] = (ddrphy_dfitimingschecker_state2 == 1'd1);
+       ddrphy_dfitimingschecker_ref_issued[3] = (ddrphy_dfitimingschecker_state3 == 1'd1);
+end
+assign ddrphy_dfitimingschecker_cmd_recv0 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv1 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv2 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next0 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv3 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv4 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv5 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv6 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv7 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv8 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next1 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv9 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv10 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv11 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv12 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv13 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv14 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next2 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv15 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv16 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv17 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv18 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv19 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv20 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next3 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv21 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv22 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv23 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv24 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv25 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv26 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next4 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv27 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv28 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv29 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv30 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv31 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv32 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next5 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv33 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv34 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv35 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv36 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv37 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv38 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next6 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv39 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv40 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv41 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv42 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv43 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv44 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next7 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv45 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv46 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv47 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
+assign ddrphy_dfitimingschecker_ps1 = ((ddrphy_dfitimingschecker_cnt + 1'd1) * 12'd2500);
+assign ddrphy_dfitimingschecker_state1 = {ddrphy_dfi_p1_cs_n, ddrphy_dfi_p1_ras_n, ddrphy_dfi_p1_cas_n, ddrphy_dfi_p1_we_n};
+assign ddrphy_dfitimingschecker_all_banks1 = ((ddrphy_dfitimingschecker_state1 == 1'd1) | ((ddrphy_dfitimingschecker_state1 == 2'd2) & ddrphy_dfi_p1_address[10]));
+assign ddrphy_dfitimingschecker_cmd_recv48 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv49 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv50 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next8 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv51 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv52 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv53 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv54 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv55 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv56 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next9 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv57 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv58 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv59 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv60 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv61 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv62 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next10 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv63 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv64 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv65 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv66 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv67 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv68 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next11 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv69 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv70 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv71 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv72 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv73 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv74 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next12 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv75 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv76 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv77 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv78 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv79 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv80 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next13 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv81 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv82 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv83 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv84 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv85 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv86 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next14 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv87 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv88 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv89 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv90 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv91 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv92 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next15 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv93 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv94 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv95 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
+assign ddrphy_dfitimingschecker_ps2 = ((ddrphy_dfitimingschecker_cnt + 2'd2) * 12'd2500);
+assign ddrphy_dfitimingschecker_state2 = {ddrphy_dfi_p2_cs_n, ddrphy_dfi_p2_ras_n, ddrphy_dfi_p2_cas_n, ddrphy_dfi_p2_we_n};
+assign ddrphy_dfitimingschecker_all_banks2 = ((ddrphy_dfitimingschecker_state2 == 1'd1) | ((ddrphy_dfitimingschecker_state2 == 2'd2) & ddrphy_dfi_p2_address[10]));
+assign ddrphy_dfitimingschecker_cmd_recv96 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv97 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv98 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next16 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv99 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv100 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv101 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv102 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv103 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv104 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next17 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv105 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv106 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv107 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv108 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv109 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv110 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next18 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv111 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv112 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv113 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv114 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv115 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv116 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next19 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv117 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv118 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv119 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv120 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv121 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv122 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next20 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv123 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv124 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv125 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv126 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv127 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv128 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next21 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv129 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv130 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv131 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv132 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv133 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv134 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next22 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv135 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv136 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv137 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv138 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv139 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv140 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next23 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv141 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv142 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv143 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
+assign ddrphy_dfitimingschecker_ps3 = ((ddrphy_dfitimingschecker_cnt + 2'd3) * 12'd2500);
+assign ddrphy_dfitimingschecker_state3 = {ddrphy_dfi_p3_cs_n, ddrphy_dfi_p3_ras_n, ddrphy_dfi_p3_cas_n, ddrphy_dfi_p3_we_n};
+assign ddrphy_dfitimingschecker_all_banks3 = ((ddrphy_dfitimingschecker_state3 == 1'd1) | ((ddrphy_dfitimingschecker_state3 == 2'd2) & ddrphy_dfi_p3_address[10]));
+assign ddrphy_dfitimingschecker_cmd_recv144 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv145 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv146 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next24 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv147 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv148 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv149 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv150 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv151 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv152 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next25 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv153 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv154 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv155 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv156 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv157 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv158 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next26 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv159 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv160 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv161 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv162 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv163 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv164 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next27 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv165 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv166 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv167 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv168 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv169 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv170 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next28 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv171 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv172 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv173 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv174 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv175 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv176 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next29 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv177 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv178 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv179 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv180 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv181 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv182 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next30 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv183 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv184 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv185 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
+assign ddrphy_dfitimingschecker_cmd_recv186 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
+assign ddrphy_dfitimingschecker_cmd_recv187 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
+assign ddrphy_dfitimingschecker_cmd_recv188 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
+assign ddrphy_dfitimingschecker_act_next31 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
+assign ddrphy_dfitimingschecker_cmd_recv189 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
+assign ddrphy_dfitimingschecker_cmd_recv190 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
+assign ddrphy_dfitimingschecker_cmd_recv191 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
+assign ddrphy_dfitimingschecker_curr_diff = (ddrphy_dfitimingschecker_ps3 - (ddrphy_dfitimingschecker_ref_ps + 23'd7812500));
+assign ddrphy_bankmodel0_wraddr = slice_proxy0[24:3];
+assign ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3];
+always @(*) begin
+       ddrphy_bankmodel0_read_data = 128'd0;
+       if (ddrphy_bankmodel0_active) begin
+               if (ddrphy_bankmodel0_read) begin
+                       ddrphy_bankmodel0_read_data = ddrphy_bankmodel0_read_port_dat_r;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel0_write_port_adr = 21'd0;
+       if (ddrphy_bankmodel0_active) begin
+               ddrphy_bankmodel0_write_port_adr = ddrphy_bankmodel0_wraddr;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel0_write_port_we = 16'd0;
+       if (ddrphy_bankmodel0_active) begin
+               if (4'd8) begin
+                       ddrphy_bankmodel0_write_port_we = ({16{ddrphy_bankmodel0_write}} & (~ddrphy_bankmodel0_write_mask));
+               end else begin
+                       ddrphy_bankmodel0_write_port_we = ddrphy_bankmodel0_write;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel0_write_port_dat_w = 128'd0;
+       if (ddrphy_bankmodel0_active) begin
+               ddrphy_bankmodel0_write_port_dat_w = ddrphy_bankmodel0_write_data;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel0_read_port_adr = 21'd0;
+       if (ddrphy_bankmodel0_active) begin
+               if (ddrphy_bankmodel0_read) begin
+                       ddrphy_bankmodel0_read_port_adr = ddrphy_bankmodel0_rdaddr;
+               end
+       end
+end
+assign ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
+assign ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
+always @(*) begin
+       ddrphy_bankmodel1_write_port_adr = 21'd0;
+       if (ddrphy_bankmodel1_active) begin
+               ddrphy_bankmodel1_write_port_adr = ddrphy_bankmodel1_wraddr;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel1_write_port_we = 16'd0;
+       if (ddrphy_bankmodel1_active) begin
+               if (4'd8) begin
+                       ddrphy_bankmodel1_write_port_we = ({16{ddrphy_bankmodel1_write}} & (~ddrphy_bankmodel1_write_mask));
+               end else begin
+                       ddrphy_bankmodel1_write_port_we = ddrphy_bankmodel1_write;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel1_write_port_dat_w = 128'd0;
+       if (ddrphy_bankmodel1_active) begin
+               ddrphy_bankmodel1_write_port_dat_w = ddrphy_bankmodel1_write_data;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel1_read_port_adr = 21'd0;
+       if (ddrphy_bankmodel1_active) begin
+               if (ddrphy_bankmodel1_read) begin
+                       ddrphy_bankmodel1_read_port_adr = ddrphy_bankmodel1_rdaddr;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel1_read_data = 128'd0;
+       if (ddrphy_bankmodel1_active) begin
+               if (ddrphy_bankmodel1_read) begin
+                       ddrphy_bankmodel1_read_data = ddrphy_bankmodel1_read_port_dat_r;
+               end
+       end
+end
+assign ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
+assign ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
+always @(*) begin
+       ddrphy_bankmodel2_write_port_adr = 21'd0;
+       if (ddrphy_bankmodel2_active) begin
+               ddrphy_bankmodel2_write_port_adr = ddrphy_bankmodel2_wraddr;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel2_write_port_we = 16'd0;
+       if (ddrphy_bankmodel2_active) begin
+               if (4'd8) begin
+                       ddrphy_bankmodel2_write_port_we = ({16{ddrphy_bankmodel2_write}} & (~ddrphy_bankmodel2_write_mask));
+               end else begin
+                       ddrphy_bankmodel2_write_port_we = ddrphy_bankmodel2_write;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel2_write_port_dat_w = 128'd0;
+       if (ddrphy_bankmodel2_active) begin
+               ddrphy_bankmodel2_write_port_dat_w = ddrphy_bankmodel2_write_data;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel2_read_port_adr = 21'd0;
+       if (ddrphy_bankmodel2_active) begin
+               if (ddrphy_bankmodel2_read) begin
+                       ddrphy_bankmodel2_read_port_adr = ddrphy_bankmodel2_rdaddr;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel2_read_data = 128'd0;
+       if (ddrphy_bankmodel2_active) begin
+               if (ddrphy_bankmodel2_read) begin
+                       ddrphy_bankmodel2_read_data = ddrphy_bankmodel2_read_port_dat_r;
+               end
+       end
+end
+assign ddrphy_bankmodel3_wraddr = slice_proxy6[24:3];
+assign ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3];
+always @(*) begin
+       ddrphy_bankmodel3_write_port_we = 16'd0;
+       if (ddrphy_bankmodel3_active) begin
+               if (4'd8) begin
+                       ddrphy_bankmodel3_write_port_we = ({16{ddrphy_bankmodel3_write}} & (~ddrphy_bankmodel3_write_mask));
+               end else begin
+                       ddrphy_bankmodel3_write_port_we = ddrphy_bankmodel3_write;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel3_write_port_dat_w = 128'd0;
+       if (ddrphy_bankmodel3_active) begin
+               ddrphy_bankmodel3_write_port_dat_w = ddrphy_bankmodel3_write_data;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel3_read_port_adr = 21'd0;
+       if (ddrphy_bankmodel3_active) begin
+               if (ddrphy_bankmodel3_read) begin
+                       ddrphy_bankmodel3_read_port_adr = ddrphy_bankmodel3_rdaddr;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel3_read_data = 128'd0;
+       if (ddrphy_bankmodel3_active) begin
+               if (ddrphy_bankmodel3_read) begin
+                       ddrphy_bankmodel3_read_data = ddrphy_bankmodel3_read_port_dat_r;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel3_write_port_adr = 21'd0;
+       if (ddrphy_bankmodel3_active) begin
+               ddrphy_bankmodel3_write_port_adr = ddrphy_bankmodel3_wraddr;
+       end
+end
+assign ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
+assign ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
+always @(*) begin
+       ddrphy_bankmodel4_read_port_adr = 21'd0;
+       if (ddrphy_bankmodel4_active) begin
+               if (ddrphy_bankmodel4_read) begin
+                       ddrphy_bankmodel4_read_port_adr = ddrphy_bankmodel4_rdaddr;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel4_read_data = 128'd0;
+       if (ddrphy_bankmodel4_active) begin
+               if (ddrphy_bankmodel4_read) begin
+                       ddrphy_bankmodel4_read_data = ddrphy_bankmodel4_read_port_dat_r;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel4_write_port_adr = 21'd0;
+       if (ddrphy_bankmodel4_active) begin
+               ddrphy_bankmodel4_write_port_adr = ddrphy_bankmodel4_wraddr;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel4_write_port_we = 16'd0;
+       if (ddrphy_bankmodel4_active) begin
+               if (4'd8) begin
+                       ddrphy_bankmodel4_write_port_we = ({16{ddrphy_bankmodel4_write}} & (~ddrphy_bankmodel4_write_mask));
+               end else begin
+                       ddrphy_bankmodel4_write_port_we = ddrphy_bankmodel4_write;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel4_write_port_dat_w = 128'd0;
+       if (ddrphy_bankmodel4_active) begin
+               ddrphy_bankmodel4_write_port_dat_w = ddrphy_bankmodel4_write_data;
+       end
+end
+assign ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
+assign ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
+always @(*) begin
+       ddrphy_bankmodel5_read_data = 128'd0;
+       if (ddrphy_bankmodel5_active) begin
+               if (ddrphy_bankmodel5_read) begin
+                       ddrphy_bankmodel5_read_data = ddrphy_bankmodel5_read_port_dat_r;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel5_write_port_adr = 21'd0;
+       if (ddrphy_bankmodel5_active) begin
+               ddrphy_bankmodel5_write_port_adr = ddrphy_bankmodel5_wraddr;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel5_write_port_we = 16'd0;
+       if (ddrphy_bankmodel5_active) begin
+               if (4'd8) begin
+                       ddrphy_bankmodel5_write_port_we = ({16{ddrphy_bankmodel5_write}} & (~ddrphy_bankmodel5_write_mask));
+               end else begin
+                       ddrphy_bankmodel5_write_port_we = ddrphy_bankmodel5_write;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel5_write_port_dat_w = 128'd0;
+       if (ddrphy_bankmodel5_active) begin
+               ddrphy_bankmodel5_write_port_dat_w = ddrphy_bankmodel5_write_data;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel5_read_port_adr = 21'd0;
+       if (ddrphy_bankmodel5_active) begin
+               if (ddrphy_bankmodel5_read) begin
+                       ddrphy_bankmodel5_read_port_adr = ddrphy_bankmodel5_rdaddr;
+               end
+       end
+end
+assign ddrphy_bankmodel6_wraddr = slice_proxy12[24:3];
+assign ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3];
+always @(*) begin
+       ddrphy_bankmodel6_read_data = 128'd0;
+       if (ddrphy_bankmodel6_active) begin
+               if (ddrphy_bankmodel6_read) begin
+                       ddrphy_bankmodel6_read_data = ddrphy_bankmodel6_read_port_dat_r;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel6_write_port_adr = 21'd0;
+       if (ddrphy_bankmodel6_active) begin
+               ddrphy_bankmodel6_write_port_adr = ddrphy_bankmodel6_wraddr;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel6_write_port_we = 16'd0;
+       if (ddrphy_bankmodel6_active) begin
+               if (4'd8) begin
+                       ddrphy_bankmodel6_write_port_we = ({16{ddrphy_bankmodel6_write}} & (~ddrphy_bankmodel6_write_mask));
+               end else begin
+                       ddrphy_bankmodel6_write_port_we = ddrphy_bankmodel6_write;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel6_write_port_dat_w = 128'd0;
+       if (ddrphy_bankmodel6_active) begin
+               ddrphy_bankmodel6_write_port_dat_w = ddrphy_bankmodel6_write_data;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel6_read_port_adr = 21'd0;
+       if (ddrphy_bankmodel6_active) begin
+               if (ddrphy_bankmodel6_read) begin
+                       ddrphy_bankmodel6_read_port_adr = ddrphy_bankmodel6_rdaddr;
+               end
+       end
+end
+assign ddrphy_bankmodel7_wraddr = slice_proxy14[24:3];
+assign ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3];
+always @(*) begin
+       ddrphy_bankmodel7_read_data = 128'd0;
+       if (ddrphy_bankmodel7_active) begin
+               if (ddrphy_bankmodel7_read) begin
+                       ddrphy_bankmodel7_read_data = ddrphy_bankmodel7_read_port_dat_r;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel7_write_port_adr = 21'd0;
+       if (ddrphy_bankmodel7_active) begin
+               ddrphy_bankmodel7_write_port_adr = ddrphy_bankmodel7_wraddr;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel7_write_port_we = 16'd0;
+       if (ddrphy_bankmodel7_active) begin
+               if (4'd8) begin
+                       ddrphy_bankmodel7_write_port_we = ({16{ddrphy_bankmodel7_write}} & (~ddrphy_bankmodel7_write_mask));
+               end else begin
+                       ddrphy_bankmodel7_write_port_we = ddrphy_bankmodel7_write;
+               end
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel7_write_port_dat_w = 128'd0;
+       if (ddrphy_bankmodel7_active) begin
+               ddrphy_bankmodel7_write_port_dat_w = ddrphy_bankmodel7_write_data;
+       end
+end
+always @(*) begin
+       ddrphy_bankmodel7_read_port_adr = 21'd0;
+       if (ddrphy_bankmodel7_active) begin
+               if (ddrphy_bankmodel7_read) begin
+                       ddrphy_bankmodel7_read_port_adr = ddrphy_bankmodel7_rdaddr;
+               end
+       end
+end
+assign ddrphy_dfi_p0_address = litedramcore_master_p0_address;
+assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
+assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
+assign ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
+assign ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
+assign ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
+assign ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
+assign ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
+assign ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
+assign ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
+assign ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
+assign ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
+assign ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
+assign ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
+assign litedramcore_master_p0_rddata = ddrphy_dfi_p0_rddata;
+assign litedramcore_master_p0_rddata_valid = ddrphy_dfi_p0_rddata_valid;
+assign ddrphy_dfi_p1_address = litedramcore_master_p1_address;
+assign ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
+assign ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
+assign ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
+assign ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
+assign ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
+assign ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
+assign ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
+assign ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
+assign ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
+assign ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
+assign ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
+assign ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
+assign ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
+assign litedramcore_master_p1_rddata = ddrphy_dfi_p1_rddata;
+assign litedramcore_master_p1_rddata_valid = ddrphy_dfi_p1_rddata_valid;
+assign ddrphy_dfi_p2_address = litedramcore_master_p2_address;
+assign ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
+assign ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
+assign ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
+assign ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
+assign ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
+assign ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
+assign ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
+assign ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
+assign ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
+assign ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
+assign ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
+assign ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
+assign ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
+assign litedramcore_master_p2_rddata = ddrphy_dfi_p2_rddata;
+assign litedramcore_master_p2_rddata_valid = ddrphy_dfi_p2_rddata_valid;
+assign ddrphy_dfi_p3_address = litedramcore_master_p3_address;
+assign ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
+assign ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
+assign ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
+assign ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
+assign ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
+assign ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
+assign ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
+assign ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
+assign ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
+assign ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
+assign ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
+assign ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
+assign ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
+assign litedramcore_master_p3_rddata = ddrphy_dfi_p3_rddata;
+assign litedramcore_master_p3_rddata_valid = ddrphy_dfi_p3_rddata_valid;
+assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
+assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
+assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
+assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
+assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
+assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
+assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
+assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
+assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
+assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
+assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
+assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
+assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
+assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
+assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
+assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
+assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
+assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
+assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
+assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
+assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
+assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
+assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
+assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
+assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
+assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
+assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
+assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
+assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
+assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
+assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
+assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
+assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
+assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
+assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
+assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
+assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
+assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
+assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
+assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
+assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
+assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
+assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
+assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
+assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
+assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
+assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
+assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
+assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
+assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
+assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
+assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
+assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
+assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
+assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
+assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
+assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
+assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
+assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
+assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
+assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
+assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
+assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
+assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
+always @(*) begin
+       litedramcore_master_p2_ras_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n;
+       end else begin
+               litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n;
+       end
+end
+always @(*) begin
+       litedramcore_slave_p2_rddata = 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata;
+       end else begin
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_we_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n;
+       end else begin
+               litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n;
+       end
+end
+always @(*) begin
+       litedramcore_slave_p2_rddata_valid = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
+       end else begin
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_cke = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_cke = litedramcore_slave_p2_cke;
+       end else begin
+               litedramcore_master_p2_cke = litedramcore_inti_p2_cke;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_odt = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_odt = litedramcore_slave_p2_odt;
+       end else begin
+               litedramcore_master_p2_odt = litedramcore_inti_p2_odt;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_reset_n = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n;
+       end else begin
+               litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_act_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n;
+       end else begin
+               litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_wrdata = 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata;
+       end else begin
+               litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p3_rddata = 32'd0;
+       if (litedramcore_storage[0]) begin
+       end else begin
+               litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_wrdata_en = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en;
+       end else begin
+               litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p3_rddata_valid = 1'd0;
+       if (litedramcore_storage[0]) begin
+       end else begin
+               litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_wrdata_mask = 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask;
+       end else begin
+               litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_rddata_en = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en;
+       end else begin
+               litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_address = 14'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_address = litedramcore_slave_p3_address;
+       end else begin
+               litedramcore_master_p3_address = litedramcore_inti_p3_address;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_bank = 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_bank = litedramcore_slave_p3_bank;
+       end else begin
+               litedramcore_master_p3_bank = litedramcore_inti_p3_bank;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_cas_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_cas_n = litedramcore_slave_p3_cas_n;
+       end else begin
+               litedramcore_master_p3_cas_n = litedramcore_inti_p3_cas_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_cs_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_cs_n = litedramcore_slave_p3_cs_n;
+       end else begin
+               litedramcore_master_p3_cs_n = litedramcore_inti_p3_cs_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_ras_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_ras_n = litedramcore_slave_p3_ras_n;
+       end else begin
+               litedramcore_master_p3_ras_n = litedramcore_inti_p3_ras_n;
+       end
+end
+always @(*) begin
+       litedramcore_slave_p3_rddata = 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p3_rddata = litedramcore_master_p3_rddata;
+       end else begin
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_we_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_we_n = litedramcore_slave_p3_we_n;
+       end else begin
+               litedramcore_master_p3_we_n = litedramcore_inti_p3_we_n;
+       end
+end
+always @(*) begin
+       litedramcore_slave_p3_rddata_valid = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
+       end else begin
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_cke = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_cke = litedramcore_slave_p3_cke;
+       end else begin
+               litedramcore_master_p3_cke = litedramcore_inti_p3_cke;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_odt = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_odt = litedramcore_slave_p3_odt;
+       end else begin
+               litedramcore_master_p3_odt = litedramcore_inti_p3_odt;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_reset_n = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_reset_n = litedramcore_slave_p3_reset_n;
+       end else begin
+               litedramcore_master_p3_reset_n = litedramcore_inti_p3_reset_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_act_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_act_n = litedramcore_slave_p3_act_n;
+       end else begin
+               litedramcore_master_p3_act_n = litedramcore_inti_p3_act_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_wrdata = 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_wrdata = litedramcore_slave_p3_wrdata;
+       end else begin
+               litedramcore_master_p3_wrdata = litedramcore_inti_p3_wrdata;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p0_rddata = 32'd0;
+       if (litedramcore_storage[0]) begin
+       end else begin
+               litedramcore_inti_p0_rddata = litedramcore_master_p0_rddata;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_wrdata_en = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_wrdata_en = litedramcore_slave_p3_wrdata_en;
+       end else begin
+               litedramcore_master_p3_wrdata_en = litedramcore_inti_p3_wrdata_en;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p0_rddata_valid = 1'd0;
+       if (litedramcore_storage[0]) begin
+       end else begin
+               litedramcore_inti_p0_rddata_valid = litedramcore_master_p0_rddata_valid;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_wrdata_mask = 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_wrdata_mask = litedramcore_slave_p3_wrdata_mask;
+       end else begin
+               litedramcore_master_p3_wrdata_mask = litedramcore_inti_p3_wrdata_mask;
+       end
+end
+always @(*) begin
+       litedramcore_master_p3_rddata_en = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_rddata_en = litedramcore_slave_p3_rddata_en;
+       end else begin
+               litedramcore_master_p3_rddata_en = litedramcore_inti_p3_rddata_en;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_address = 14'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_address = litedramcore_slave_p0_address;
+       end else begin
+               litedramcore_master_p0_address = litedramcore_inti_p0_address;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_bank = 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_bank = litedramcore_slave_p0_bank;
+       end else begin
+               litedramcore_master_p0_bank = litedramcore_inti_p0_bank;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_cas_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_cas_n = litedramcore_slave_p0_cas_n;
+       end else begin
+               litedramcore_master_p0_cas_n = litedramcore_inti_p0_cas_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_cs_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_cs_n = litedramcore_slave_p0_cs_n;
+       end else begin
+               litedramcore_master_p0_cs_n = litedramcore_inti_p0_cs_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_ras_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_ras_n = litedramcore_slave_p0_ras_n;
+       end else begin
+               litedramcore_master_p0_ras_n = litedramcore_inti_p0_ras_n;
+       end
+end
+always @(*) begin
+       litedramcore_slave_p0_rddata = 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p0_rddata = litedramcore_master_p0_rddata;
+       end else begin
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_we_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_we_n = litedramcore_slave_p0_we_n;
+       end else begin
+               litedramcore_master_p0_we_n = litedramcore_inti_p0_we_n;
+       end
+end
+always @(*) begin
+       litedramcore_slave_p0_rddata_valid = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p0_rddata_valid = litedramcore_master_p0_rddata_valid;
+       end else begin
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_cke = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_cke = litedramcore_slave_p0_cke;
+       end else begin
+               litedramcore_master_p0_cke = litedramcore_inti_p0_cke;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_odt = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_odt = litedramcore_slave_p0_odt;
+       end else begin
+               litedramcore_master_p0_odt = litedramcore_inti_p0_odt;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_reset_n = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_reset_n = litedramcore_slave_p0_reset_n;
+       end else begin
+               litedramcore_master_p0_reset_n = litedramcore_inti_p0_reset_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_act_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_act_n = litedramcore_slave_p0_act_n;
+       end else begin
+               litedramcore_master_p0_act_n = litedramcore_inti_p0_act_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_wrdata = 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_wrdata = litedramcore_slave_p0_wrdata;
+       end else begin
+               litedramcore_master_p0_wrdata = litedramcore_inti_p0_wrdata;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p1_rddata = 32'd0;
+       if (litedramcore_storage[0]) begin
+       end else begin
+               litedramcore_inti_p1_rddata = litedramcore_master_p1_rddata;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_wrdata_en = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_wrdata_en = litedramcore_slave_p0_wrdata_en;
+       end else begin
+               litedramcore_master_p0_wrdata_en = litedramcore_inti_p0_wrdata_en;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p1_rddata_valid = 1'd0;
+       if (litedramcore_storage[0]) begin
+       end else begin
+               litedramcore_inti_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_wrdata_mask = 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_wrdata_mask = litedramcore_slave_p0_wrdata_mask;
+       end else begin
+               litedramcore_master_p0_wrdata_mask = litedramcore_inti_p0_wrdata_mask;
+       end
+end
+always @(*) begin
+       litedramcore_master_p0_rddata_en = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_rddata_en = litedramcore_slave_p0_rddata_en;
+       end else begin
+               litedramcore_master_p0_rddata_en = litedramcore_inti_p0_rddata_en;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_address = 14'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_address = litedramcore_slave_p1_address;
+       end else begin
+               litedramcore_master_p1_address = litedramcore_inti_p1_address;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_bank = 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_bank = litedramcore_slave_p1_bank;
+       end else begin
+               litedramcore_master_p1_bank = litedramcore_inti_p1_bank;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_cas_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_cas_n = litedramcore_slave_p1_cas_n;
+       end else begin
+               litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_cs_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n;
+       end else begin
+               litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_ras_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n;
+       end else begin
+               litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n;
+       end
+end
+always @(*) begin
+       litedramcore_slave_p1_rddata = 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata;
+       end else begin
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_we_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n;
+       end else begin
+               litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n;
+       end
+end
+always @(*) begin
+       litedramcore_slave_p1_rddata_valid = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
+       end else begin
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_cke = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_cke = litedramcore_slave_p1_cke;
+       end else begin
+               litedramcore_master_p1_cke = litedramcore_inti_p1_cke;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_odt = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_odt = litedramcore_slave_p1_odt;
+       end else begin
+               litedramcore_master_p1_odt = litedramcore_inti_p1_odt;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_reset_n = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n;
+       end else begin
+               litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_act_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n;
+       end else begin
+               litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_wrdata = 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata;
+       end else begin
+               litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p2_rddata = 32'd0;
+       if (litedramcore_storage[0]) begin
+       end else begin
+               litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_wrdata_en = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en;
+       end else begin
+               litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p2_rddata_valid = 1'd0;
+       if (litedramcore_storage[0]) begin
+       end else begin
+               litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_wrdata_mask = 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask;
+       end else begin
+               litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask;
+       end
+end
+always @(*) begin
+       litedramcore_master_p1_rddata_en = 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en;
+       end else begin
+               litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_address = 14'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_address = litedramcore_slave_p2_address;
+       end else begin
+               litedramcore_master_p2_address = litedramcore_inti_p2_address;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_bank = 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_bank = litedramcore_slave_p2_bank;
+       end else begin
+               litedramcore_master_p2_bank = litedramcore_inti_p2_bank;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_cas_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n;
+       end else begin
+               litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n;
+       end
+end
+always @(*) begin
+       litedramcore_master_p2_cs_n = 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n;
+       end else begin
+               litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n;
+       end
+end
+assign litedramcore_inti_p0_cke = litedramcore_storage[1];
+assign litedramcore_inti_p1_cke = litedramcore_storage[1];
+assign litedramcore_inti_p2_cke = litedramcore_storage[1];
+assign litedramcore_inti_p3_cke = litedramcore_storage[1];
+assign litedramcore_inti_p0_odt = litedramcore_storage[2];
+assign litedramcore_inti_p1_odt = litedramcore_storage[2];
+assign litedramcore_inti_p2_odt = litedramcore_storage[2];
+assign litedramcore_inti_p3_odt = litedramcore_storage[2];
+assign litedramcore_inti_p0_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p1_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p2_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
+always @(*) begin
+       litedramcore_inti_p0_ras_n = 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_ras_n = (~litedramcore_phaseinjector0_command_storage[3]);
+       end else begin
+               litedramcore_inti_p0_ras_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p0_we_n = 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]);
+       end else begin
+               litedramcore_inti_p0_we_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p0_cas_n = 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]);
+       end else begin
+               litedramcore_inti_p0_cas_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p0_cs_n = 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_cs_n = {1{(~litedramcore_phaseinjector0_command_storage[0])}};
+       end else begin
+               litedramcore_inti_p0_cs_n = {1{1'd1}};
+       end
+end
+assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
+assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
+assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_inti_p0_wrdata_mask = 1'd0;
+always @(*) begin
+       litedramcore_inti_p1_ras_n = 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_ras_n = (~litedramcore_phaseinjector1_command_storage[3]);
+       end else begin
+               litedramcore_inti_p1_ras_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p1_we_n = 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]);
+       end else begin
+               litedramcore_inti_p1_we_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p1_cas_n = 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]);
+       end else begin
+               litedramcore_inti_p1_cas_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p1_cs_n = 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_cs_n = {1{(~litedramcore_phaseinjector1_command_storage[0])}};
+       end else begin
+               litedramcore_inti_p1_cs_n = {1{1'd1}};
+       end
+end
+assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
+assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
+assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_inti_p1_wrdata_mask = 1'd0;
+always @(*) begin
+       litedramcore_inti_p2_ras_n = 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_ras_n = (~litedramcore_phaseinjector2_command_storage[3]);
+       end else begin
+               litedramcore_inti_p2_ras_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p2_we_n = 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]);
+       end else begin
+               litedramcore_inti_p2_we_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p2_cas_n = 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_cas_n = (~litedramcore_phaseinjector2_command_storage[2]);
+       end else begin
+               litedramcore_inti_p2_cas_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p2_cs_n = 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_cs_n = {1{(~litedramcore_phaseinjector2_command_storage[0])}};
+       end else begin
+               litedramcore_inti_p2_cs_n = {1{1'd1}};
+       end
+end
+assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
+assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
+assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
+assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
+assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
+assign litedramcore_inti_p2_wrdata_mask = 1'd0;
+always @(*) begin
+       litedramcore_inti_p3_ras_n = 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_ras_n = (~litedramcore_phaseinjector3_command_storage[3]);
+       end else begin
+               litedramcore_inti_p3_ras_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p3_we_n = 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_we_n = (~litedramcore_phaseinjector3_command_storage[1]);
+       end else begin
+               litedramcore_inti_p3_we_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p3_cas_n = 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_cas_n = (~litedramcore_phaseinjector3_command_storage[2]);
+       end else begin
+               litedramcore_inti_p3_cas_n = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_inti_p3_cs_n = 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_cs_n = {1{(~litedramcore_phaseinjector3_command_storage[0])}};
+       end else begin
+               litedramcore_inti_p3_cs_n = {1{1'd1}};
+       end
+end
+assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
+assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage;
+assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]);
+assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]);
+assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
+assign litedramcore_inti_p3_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
+assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
+assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
+assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
+assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
+assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
+assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
+assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
+assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
+assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
+assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
+assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
+assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
+assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
+assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
+assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
+assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
+assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
+assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
+assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
+assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
+assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
+assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
+assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
+assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
+assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
+assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
+assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
+assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
+assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
+assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
+assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
+assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
+assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
+assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
+assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
+assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
+assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
+assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
+assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
+assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
+assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
+assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
+assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
+assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
+assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
+assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
+assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
+assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
+assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
+assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
+assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
+assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
+assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
+assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
+assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
+assign litedramcore_timer_wait = (~litedramcore_timer_done0);
+assign litedramcore_postponer_req_i = litedramcore_timer_done0;
+assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
+assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
+assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
+assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
+assign litedramcore_timer_done0 = litedramcore_timer_done1;
+assign litedramcore_timer_count0 = litedramcore_timer_count1;
+assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
+assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
+assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
+assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
+assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
+always @(*) begin
+       refresher_next_state = 2'd0;
+       refresher_next_state = refresher_state;
+       case (refresher_state)
+               1'd1: begin
+                       if (litedramcore_cmd_ready) begin
+                               refresher_next_state = 2'd2;
+                       end
+               end
+               2'd2: begin
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                                       refresher_next_state = 2'd3;
+                               end else begin
+                                       refresher_next_state = 1'd0;
+                               end
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_zqcs_executer_done) begin
+                               refresher_next_state = 1'd0;
+                       end
+               end
+               default: begin
+                       if (1'd1) begin
+                               if (litedramcore_wants_refresh) begin
+                                       refresher_next_state = 1'd1;
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_cmd_valid = 1'd0;
+       case (refresher_state)
+               1'd1: begin
+                       litedramcore_cmd_valid = 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_cmd_valid = 1'd1;
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                               end else begin
+                                       litedramcore_cmd_valid = 1'd0;
+                               end
+                       end
+               end
+               2'd3: begin
+                       litedramcore_cmd_valid = 1'd1;
+                       if (litedramcore_zqcs_executer_done) begin
+                               litedramcore_cmd_valid = 1'd0;
+                       end
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_zqcs_executer_start = 1'd0;
+       case (refresher_state)
+               1'd1: begin
+               end
+               2'd2: begin
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                                       litedramcore_zqcs_executer_start = 1'd1;
+                               end else begin
+                               end
+                       end
+               end
+               2'd3: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_cmd_last = 1'd0;
+       case (refresher_state)
+               1'd1: begin
+               end
+               2'd2: begin
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                               end else begin
+                                       litedramcore_cmd_last = 1'd1;
+                               end
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_zqcs_executer_done) begin
+                               litedramcore_cmd_last = 1'd1;
+                       end
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_sequencer_start0 = 1'd0;
+       case (refresher_state)
+               1'd1: begin
+                       if (litedramcore_cmd_ready) begin
+                               litedramcore_sequencer_start0 = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               default: begin
+               end
+       endcase
+end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+always @(*) begin
+       litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+       if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+               litedramcore_bankmachine0_cmd_payload_a = litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine0_cmd_payload_a = ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+end
+assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
+assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+always @(*) begin
+       litedramcore_bankmachine0_auto_precharge = 1'd0;
+       if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine0_auto_precharge = (litedramcore_bankmachine0_row_close == 1'd0);
+               end
+       end
+end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+       litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+       if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+       end
+end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
+always @(*) begin
+       bankmachine0_next_state = 4'd0;
+       bankmachine0_next_state = bankmachine0_state;
+       case (bankmachine0_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               if (litedramcore_bankmachine0_cmd_ready) begin
+                                       bankmachine0_next_state = 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               bankmachine0_next_state = 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               if (litedramcore_bankmachine0_cmd_ready) begin
+                                       bankmachine0_next_state = 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine0_refresh_req)) begin
+                               bankmachine0_next_state = 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine0_next_state = 3'd6;
+               end
+               3'd6: begin
+                       bankmachine0_next_state = 2'd3;
+               end
+               3'd7: begin
+                       bankmachine0_next_state = 4'd8;
+               end
+               4'd8: begin
+                       bankmachine0_next_state = 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                               bankmachine0_next_state = 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+                                                               bankmachine0_next_state = 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine0_next_state = 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine0_next_state = 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine0_cmd_payload_is_read = 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine0_cmd_payload_is_write = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine0_req_wdata_ready = litedramcore_bankmachine0_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine0_req_rdata_valid = litedramcore_bankmachine0_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_refresh_gnt = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       if (litedramcore_bankmachine0_twtpcon_ready) begin
+                               litedramcore_bankmachine0_refresh_gnt = 1'd1;
+                       end
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_cmd_valid = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_valid = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_cmd_valid = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       litedramcore_bankmachine0_cmd_valid = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_row_open = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_row_open = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_row_close = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+                       litedramcore_bankmachine0_row_close = 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_bankmachine0_row_close = 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       litedramcore_bankmachine0_row_close = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       litedramcore_bankmachine0_cmd_payload_cas = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_cmd_payload_ras = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_payload_we = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine0_cmd_payload_we = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+       case (bankmachine0_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               3'd4: begin
+                       litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+always @(*) begin
+       litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+       if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+               litedramcore_bankmachine1_cmd_payload_a = litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine1_cmd_payload_a = ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+end
+assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
+assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+always @(*) begin
+       litedramcore_bankmachine1_auto_precharge = 1'd0;
+       if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine1_auto_precharge = (litedramcore_bankmachine1_row_close == 1'd0);
+               end
+       end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+       litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+       if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+       end
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
+always @(*) begin
+       bankmachine1_next_state = 4'd0;
+       bankmachine1_next_state = bankmachine1_state;
+       case (bankmachine1_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               if (litedramcore_bankmachine1_cmd_ready) begin
+                                       bankmachine1_next_state = 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               bankmachine1_next_state = 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               if (litedramcore_bankmachine1_cmd_ready) begin
+                                       bankmachine1_next_state = 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine1_refresh_req)) begin
+                               bankmachine1_next_state = 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine1_next_state = 3'd6;
+               end
+               3'd6: begin
+                       bankmachine1_next_state = 2'd3;
+               end
+               3'd7: begin
+                       bankmachine1_next_state = 4'd8;
+               end
+               4'd8: begin
+                       bankmachine1_next_state = 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                               bankmachine1_next_state = 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+                                                               bankmachine1_next_state = 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine1_next_state = 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine1_next_state = 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine1_cmd_payload_is_read = 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine1_cmd_payload_is_write = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine1_req_wdata_ready = litedramcore_bankmachine1_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine1_req_rdata_valid = litedramcore_bankmachine1_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_refresh_gnt = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       if (litedramcore_bankmachine1_twtpcon_ready) begin
+                               litedramcore_bankmachine1_refresh_gnt = 1'd1;
+                       end
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_cmd_valid = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_valid = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_cmd_valid = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       litedramcore_bankmachine1_cmd_valid = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_row_open = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_row_open = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_row_close = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+                       litedramcore_bankmachine1_row_close = 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_bankmachine1_row_close = 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       litedramcore_bankmachine1_row_close = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       litedramcore_bankmachine1_cmd_payload_cas = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_cmd_payload_ras = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_payload_we = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine1_cmd_payload_we = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               3'd4: begin
+                       litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+always @(*) begin
+       litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+       if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+               litedramcore_bankmachine2_cmd_payload_a = litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine2_cmd_payload_a = ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+end
+assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
+assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+always @(*) begin
+       litedramcore_bankmachine2_auto_precharge = 1'd0;
+       if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine2_auto_precharge = (litedramcore_bankmachine2_row_close == 1'd0);
+               end
+       end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+       litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+       if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+       end
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+always @(*) begin
+       bankmachine2_next_state = 4'd0;
+       bankmachine2_next_state = bankmachine2_state;
+       case (bankmachine2_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               if (litedramcore_bankmachine2_cmd_ready) begin
+                                       bankmachine2_next_state = 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               bankmachine2_next_state = 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               if (litedramcore_bankmachine2_cmd_ready) begin
+                                       bankmachine2_next_state = 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine2_refresh_req)) begin
+                               bankmachine2_next_state = 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine2_next_state = 3'd6;
+               end
+               3'd6: begin
+                       bankmachine2_next_state = 2'd3;
+               end
+               3'd7: begin
+                       bankmachine2_next_state = 4'd8;
+               end
+               4'd8: begin
+                       bankmachine2_next_state = 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                               bankmachine2_next_state = 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+                                                               bankmachine2_next_state = 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine2_next_state = 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine2_next_state = 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine2_cmd_payload_is_read = 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine2_cmd_payload_is_write = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine2_req_wdata_ready = litedramcore_bankmachine2_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine2_req_rdata_valid = litedramcore_bankmachine2_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_refresh_gnt = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       if (litedramcore_bankmachine2_twtpcon_ready) begin
+                               litedramcore_bankmachine2_refresh_gnt = 1'd1;
+                       end
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_cmd_valid = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_valid = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_cmd_valid = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       litedramcore_bankmachine2_cmd_valid = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_row_open = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_row_open = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_row_close = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+                       litedramcore_bankmachine2_row_close = 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_bankmachine2_row_close = 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       litedramcore_bankmachine2_row_close = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       litedramcore_bankmachine2_cmd_payload_cas = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_cmd_payload_ras = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_payload_we = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine2_cmd_payload_we = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+       case (bankmachine2_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               3'd4: begin
+                       litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+always @(*) begin
+       litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+       if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+               litedramcore_bankmachine3_cmd_payload_a = litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine3_cmd_payload_a = ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+end
+assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
+assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+always @(*) begin
+       litedramcore_bankmachine3_auto_precharge = 1'd0;
+       if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine3_auto_precharge = (litedramcore_bankmachine3_row_close == 1'd0);
+               end
+       end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+       litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+       if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+       end
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
+always @(*) begin
+       bankmachine3_next_state = 4'd0;
+       bankmachine3_next_state = bankmachine3_state;
+       case (bankmachine3_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               if (litedramcore_bankmachine3_cmd_ready) begin
+                                       bankmachine3_next_state = 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               bankmachine3_next_state = 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               if (litedramcore_bankmachine3_cmd_ready) begin
+                                       bankmachine3_next_state = 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine3_refresh_req)) begin
+                               bankmachine3_next_state = 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine3_next_state = 3'd6;
+               end
+               3'd6: begin
+                       bankmachine3_next_state = 2'd3;
+               end
+               3'd7: begin
+                       bankmachine3_next_state = 4'd8;
+               end
+               4'd8: begin
+                       bankmachine3_next_state = 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                               bankmachine3_next_state = 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+                                                               bankmachine3_next_state = 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine3_next_state = 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine3_next_state = 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine3_cmd_payload_is_read = 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine3_cmd_payload_is_write = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine3_req_wdata_ready = litedramcore_bankmachine3_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine3_req_rdata_valid = litedramcore_bankmachine3_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_refresh_gnt = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       if (litedramcore_bankmachine3_twtpcon_ready) begin
+                               litedramcore_bankmachine3_refresh_gnt = 1'd1;
+                       end
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_cmd_valid = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_valid = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_cmd_valid = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       litedramcore_bankmachine3_cmd_valid = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_row_open = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_row_open = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_row_close = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+                       litedramcore_bankmachine3_row_close = 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_bankmachine3_row_close = 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       litedramcore_bankmachine3_row_close = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       litedramcore_bankmachine3_cmd_payload_cas = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_cmd_payload_ras = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_payload_we = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine3_cmd_payload_we = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+       case (bankmachine3_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               3'd4: begin
+                       litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+always @(*) begin
+       litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+       if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+               litedramcore_bankmachine4_cmd_payload_a = litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine4_cmd_payload_a = ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+end
+assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
+assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+always @(*) begin
+       litedramcore_bankmachine4_auto_precharge = 1'd0;
+       if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine4_auto_precharge = (litedramcore_bankmachine4_row_close == 1'd0);
+               end
+       end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+       litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+       if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+       end
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
+always @(*) begin
+       bankmachine4_next_state = 4'd0;
+       bankmachine4_next_state = bankmachine4_state;
+       case (bankmachine4_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               if (litedramcore_bankmachine4_cmd_ready) begin
+                                       bankmachine4_next_state = 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               bankmachine4_next_state = 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               if (litedramcore_bankmachine4_cmd_ready) begin
+                                       bankmachine4_next_state = 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine4_refresh_req)) begin
+                               bankmachine4_next_state = 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine4_next_state = 3'd6;
+               end
+               3'd6: begin
+                       bankmachine4_next_state = 2'd3;
+               end
+               3'd7: begin
+                       bankmachine4_next_state = 4'd8;
+               end
+               4'd8: begin
+                       bankmachine4_next_state = 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                               bankmachine4_next_state = 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+                                                               bankmachine4_next_state = 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine4_next_state = 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine4_next_state = 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine4_cmd_payload_is_read = 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine4_cmd_payload_is_write = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine4_req_wdata_ready = litedramcore_bankmachine4_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine4_req_rdata_valid = litedramcore_bankmachine4_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_refresh_gnt = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       if (litedramcore_bankmachine4_twtpcon_ready) begin
+                               litedramcore_bankmachine4_refresh_gnt = 1'd1;
+                       end
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_cmd_valid = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_valid = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_cmd_valid = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       litedramcore_bankmachine4_cmd_valid = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_row_open = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_row_open = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_row_close = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+                       litedramcore_bankmachine4_row_close = 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_bankmachine4_row_close = 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       litedramcore_bankmachine4_row_close = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       litedramcore_bankmachine4_cmd_payload_cas = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_cmd_payload_ras = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_payload_we = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine4_cmd_payload_we = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+       case (bankmachine4_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               3'd4: begin
+                       litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+always @(*) begin
+       litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+       if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+               litedramcore_bankmachine5_cmd_payload_a = litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine5_cmd_payload_a = ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+end
+assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
+assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+always @(*) begin
+       litedramcore_bankmachine5_auto_precharge = 1'd0;
+       if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine5_auto_precharge = (litedramcore_bankmachine5_row_close == 1'd0);
+               end
+       end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+       litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+       if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+       end
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
+always @(*) begin
+       bankmachine5_next_state = 4'd0;
+       bankmachine5_next_state = bankmachine5_state;
+       case (bankmachine5_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               if (litedramcore_bankmachine5_cmd_ready) begin
+                                       bankmachine5_next_state = 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               bankmachine5_next_state = 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               if (litedramcore_bankmachine5_cmd_ready) begin
+                                       bankmachine5_next_state = 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine5_refresh_req)) begin
+                               bankmachine5_next_state = 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine5_next_state = 3'd6;
+               end
+               3'd6: begin
+                       bankmachine5_next_state = 2'd3;
+               end
+               3'd7: begin
+                       bankmachine5_next_state = 4'd8;
+               end
+               4'd8: begin
+                       bankmachine5_next_state = 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                               bankmachine5_next_state = 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+                                                               bankmachine5_next_state = 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine5_next_state = 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine5_next_state = 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine5_cmd_payload_is_read = 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine5_cmd_payload_is_write = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine5_req_wdata_ready = litedramcore_bankmachine5_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine5_req_rdata_valid = litedramcore_bankmachine5_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_refresh_gnt = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       if (litedramcore_bankmachine5_twtpcon_ready) begin
+                               litedramcore_bankmachine5_refresh_gnt = 1'd1;
+                       end
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_cmd_valid = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_valid = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_cmd_valid = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       litedramcore_bankmachine5_cmd_valid = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_row_open = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_row_open = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_row_close = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+                       litedramcore_bankmachine5_row_close = 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_bankmachine5_row_close = 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       litedramcore_bankmachine5_row_close = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       litedramcore_bankmachine5_cmd_payload_cas = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_cmd_payload_ras = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_payload_we = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine5_cmd_payload_we = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               3'd4: begin
+                       litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+always @(*) begin
+       litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+       if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+               litedramcore_bankmachine6_cmd_payload_a = litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine6_cmd_payload_a = ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+end
+assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
+assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+always @(*) begin
+       litedramcore_bankmachine6_auto_precharge = 1'd0;
+       if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine6_auto_precharge = (litedramcore_bankmachine6_row_close == 1'd0);
+               end
+       end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+       litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+       if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+       end
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
+always @(*) begin
+       bankmachine6_next_state = 4'd0;
+       bankmachine6_next_state = bankmachine6_state;
+       case (bankmachine6_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               if (litedramcore_bankmachine6_cmd_ready) begin
+                                       bankmachine6_next_state = 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               bankmachine6_next_state = 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               if (litedramcore_bankmachine6_cmd_ready) begin
+                                       bankmachine6_next_state = 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine6_refresh_req)) begin
+                               bankmachine6_next_state = 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine6_next_state = 3'd6;
+               end
+               3'd6: begin
+                       bankmachine6_next_state = 2'd3;
+               end
+               3'd7: begin
+                       bankmachine6_next_state = 4'd8;
+               end
+               4'd8: begin
+                       bankmachine6_next_state = 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                               bankmachine6_next_state = 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+                                                               bankmachine6_next_state = 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine6_next_state = 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine6_next_state = 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine6_cmd_payload_is_read = 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine6_cmd_payload_is_write = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine6_req_rdata_valid = litedramcore_bankmachine6_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_refresh_gnt = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       if (litedramcore_bankmachine6_twtpcon_ready) begin
+                               litedramcore_bankmachine6_refresh_gnt = 1'd1;
+                       end
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_cmd_valid = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_valid = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_cmd_valid = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       litedramcore_bankmachine6_cmd_valid = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_row_open = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_row_open = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_row_close = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+                       litedramcore_bankmachine6_row_close = 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_bankmachine6_row_close = 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       litedramcore_bankmachine6_row_close = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       litedramcore_bankmachine6_cmd_payload_cas = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_cmd_payload_ras = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_payload_we = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine6_cmd_payload_we = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+       case (bankmachine6_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               3'd4: begin
+                       litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+always @(*) begin
+       litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+       if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+               litedramcore_bankmachine7_cmd_payload_a = litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine7_cmd_payload_a = ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+end
+assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
+assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+always @(*) begin
+       litedramcore_bankmachine7_auto_precharge = 1'd0;
+       if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine7_auto_precharge = (litedramcore_bankmachine7_row_close == 1'd0);
+               end
+       end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+always @(*) begin
+       litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+       if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+       end
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
+always @(*) begin
+       bankmachine7_next_state = 4'd0;
+       bankmachine7_next_state = bankmachine7_state;
+       case (bankmachine7_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               if (litedramcore_bankmachine7_cmd_ready) begin
+                                       bankmachine7_next_state = 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               bankmachine7_next_state = 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               if (litedramcore_bankmachine7_cmd_ready) begin
+                                       bankmachine7_next_state = 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine7_refresh_req)) begin
+                               bankmachine7_next_state = 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine7_next_state = 3'd6;
+               end
+               3'd6: begin
+                       bankmachine7_next_state = 2'd3;
+               end
+               3'd7: begin
+                       bankmachine7_next_state = 4'd8;
+               end
+               4'd8: begin
+                       bankmachine7_next_state = 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                               bankmachine7_next_state = 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+                                                               bankmachine7_next_state = 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine7_next_state = 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine7_next_state = 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine7_cmd_payload_is_read = 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine7_cmd_payload_is_write = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine7_req_wdata_ready = litedramcore_bankmachine7_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine7_req_rdata_valid = litedramcore_bankmachine7_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_refresh_gnt = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       if (litedramcore_bankmachine7_twtpcon_ready) begin
+                               litedramcore_bankmachine7_refresh_gnt = 1'd1;
+                       end
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_cmd_valid = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_valid = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_cmd_valid = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       litedramcore_bankmachine7_cmd_valid = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_row_open = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_row_open = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_row_close = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+                       litedramcore_bankmachine7_row_close = 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_bankmachine7_row_close = 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       litedramcore_bankmachine7_row_close = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       litedramcore_bankmachine7_cmd_payload_cas = 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_cmd_payload_ras = 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_payload_we = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine7_cmd_payload_we = 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
+                       end
+               end
+               3'd4: begin
+                       litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+end
+assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
+assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
+assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
+assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
+assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
+assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
+assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
+assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
+assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+always @(*) begin
+       litedramcore_choose_cmd_valids = 8'd0;
+       litedramcore_choose_cmd_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+end
+assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
+assign litedramcore_choose_cmd_cmd_valid = comb_rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = comb_rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = comb_rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = comb_rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = comb_rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = comb_rhs_array_muxed5;
+always @(*) begin
+       litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+       if (litedramcore_choose_cmd_cmd_valid) begin
+               litedramcore_choose_cmd_cmd_payload_cas = comb_t_array_muxed0;
+       end
+end
+always @(*) begin
+       litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+       if (litedramcore_choose_cmd_cmd_valid) begin
+               litedramcore_choose_cmd_cmd_payload_ras = comb_t_array_muxed1;
+       end
+end
+always @(*) begin
+       litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+       if (litedramcore_choose_cmd_cmd_valid) begin
+               litedramcore_choose_cmd_cmd_payload_we = comb_t_array_muxed2;
+       end
+end
+always @(*) begin
+       litedramcore_bankmachine0_cmd_ready = 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+               litedramcore_bankmachine0_cmd_ready = 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+               litedramcore_bankmachine0_cmd_ready = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_bankmachine1_cmd_ready = 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+               litedramcore_bankmachine1_cmd_ready = 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+               litedramcore_bankmachine1_cmd_ready = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_bankmachine2_cmd_ready = 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+               litedramcore_bankmachine2_cmd_ready = 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+               litedramcore_bankmachine2_cmd_ready = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_bankmachine3_cmd_ready = 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+               litedramcore_bankmachine3_cmd_ready = 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+               litedramcore_bankmachine3_cmd_ready = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_bankmachine4_cmd_ready = 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+               litedramcore_bankmachine4_cmd_ready = 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+               litedramcore_bankmachine4_cmd_ready = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_bankmachine5_cmd_ready = 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+               litedramcore_bankmachine5_cmd_ready = 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+               litedramcore_bankmachine5_cmd_ready = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_bankmachine6_cmd_ready = 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+               litedramcore_bankmachine6_cmd_ready = 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+               litedramcore_bankmachine6_cmd_ready = 1'd1;
+       end
+end
+always @(*) begin
+       litedramcore_bankmachine7_cmd_ready = 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+               litedramcore_bankmachine7_cmd_ready = 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+               litedramcore_bankmachine7_cmd_ready = 1'd1;
+       end
+end
+assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+always @(*) begin
+       litedramcore_choose_req_valids = 8'd0;
+       litedramcore_choose_req_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+end
+assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
+assign litedramcore_choose_req_cmd_valid = comb_rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = comb_rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = comb_rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = comb_rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = comb_rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = comb_rhs_array_muxed11;
+always @(*) begin
+       litedramcore_choose_req_cmd_payload_cas = 1'd0;
+       if (litedramcore_choose_req_cmd_valid) begin
+               litedramcore_choose_req_cmd_payload_cas = comb_t_array_muxed3;
+       end
+end
+always @(*) begin
+       litedramcore_choose_req_cmd_payload_ras = 1'd0;
+       if (litedramcore_choose_req_cmd_valid) begin
+               litedramcore_choose_req_cmd_payload_ras = comb_t_array_muxed4;
+       end
+end
+always @(*) begin
+       litedramcore_choose_req_cmd_payload_we = 1'd0;
+       if (litedramcore_choose_req_cmd_valid) begin
+               litedramcore_choose_req_cmd_payload_we = comb_t_array_muxed5;
+       end
+end
+assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
+assign litedramcore_dfi_p0_reset_n = 1'd1;
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p1_reset_n = 1'd1;
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_dfi_p2_reset_n = 1'd1;
+assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
+assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
+assign litedramcore_dfi_p3_reset_n = 1'd1;
+assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
+assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
+assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
+always @(*) begin
+       multiplexer_next_state = 4'd0;
+       multiplexer_next_state = multiplexer_state;
+       case (multiplexer_state)
+               1'd1: begin
+                       if (litedramcore_read_available) begin
+                               if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+                                       multiplexer_next_state = 2'd3;
+                               end
+                       end
+                       if (litedramcore_go_to_refresh) begin
+                               multiplexer_next_state = 2'd2;
+                       end
+               end
+               2'd2: begin
+                       if (litedramcore_cmd_last) begin
+                               multiplexer_next_state = 1'd0;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_twtrcon_ready) begin
+                               multiplexer_next_state = 1'd0;
+                       end
+               end
+               3'd4: begin
+                       multiplexer_next_state = 3'd5;
+               end
+               3'd5: begin
+                       multiplexer_next_state = 3'd6;
+               end
+               3'd6: begin
+                       multiplexer_next_state = 3'd7;
+               end
+               3'd7: begin
+                       multiplexer_next_state = 4'd8;
+               end
+               4'd8: begin
+                       multiplexer_next_state = 4'd9;
+               end
+               4'd9: begin
+                       multiplexer_next_state = 4'd10;
+               end
+               4'd10: begin
+                       multiplexer_next_state = 4'd11;
+               end
+               4'd11: begin
+                       multiplexer_next_state = 1'd1;
+               end
+               default: begin
+                       if (litedramcore_write_available) begin
+                               if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+                                       multiplexer_next_state = 3'd4;
+                               end
+                       end
+                       if (litedramcore_go_to_refresh) begin
+                               multiplexer_next_state = 2'd2;
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_steerer_sel1 = 2'd0;
+       case (multiplexer_state)
+               1'd1: begin
+                       litedramcore_steerer_sel1 = 1'd0;
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+                       litedramcore_steerer_sel1 = 1'd1;
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_steerer_sel2 = 2'd0;
+       case (multiplexer_state)
+               1'd1: begin
+                       litedramcore_steerer_sel2 = 1'd1;
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+                       litedramcore_steerer_sel2 = 2'd2;
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_choose_cmd_want_activates = 1'd0;
+       case (multiplexer_state)
+               1'd1: begin
+                       if (1'd0) begin
+                       end else begin
+                               litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+                       if (1'd0) begin
+                       end else begin
+                               litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed;
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_steerer_sel3 = 2'd0;
+       case (multiplexer_state)
+               1'd1: begin
+                       litedramcore_steerer_sel3 = 2'd2;
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+                       litedramcore_steerer_sel3 = 1'd0;
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_en0 = 1'd0;
+       case (multiplexer_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+                       litedramcore_en0 = 1'd1;
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_cmd_ready = 1'd0;
+       case (multiplexer_state)
+               1'd1: begin
+               end
+               2'd2: begin
+                       litedramcore_cmd_ready = 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_choose_cmd_cmd_ready = 1'd0;
+       case (multiplexer_state)
+               1'd1: begin
+                       if (1'd0) begin
+                       end else begin
+                               litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+                       if (1'd0) begin
+                       end else begin
+                               litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_choose_req_want_reads = 1'd0;
+       case (multiplexer_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+                       litedramcore_choose_req_want_reads = 1'd1;
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_choose_req_want_writes = 1'd0;
+       case (multiplexer_state)
+               1'd1: begin
+                       litedramcore_choose_req_want_writes = 1'd1;
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_choose_req_cmd_ready = 1'd0;
+       case (multiplexer_state)
+               1'd1: begin
+                       if (1'd0) begin
+                               litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+                       end else begin
+                               litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+                       if (1'd0) begin
+                               litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+                       end else begin
+                               litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed;
+                       end
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_en1 = 1'd0;
+       case (multiplexer_state)
+               1'd1: begin
+                       litedramcore_en1 = 1'd1;
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_steerer_sel0 = 2'd0;
+       case (multiplexer_state)
+               1'd1: begin
+                       litedramcore_steerer_sel0 = 1'd0;
+               end
+               2'd2: begin
+                       litedramcore_steerer_sel0 = 2'd3;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
+               4'd11: begin
+               end
+               default: begin
+                       litedramcore_steerer_sel0 = 1'd0;
+               end
+       endcase
+end
+assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = comb_rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = comb_rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = comb_rhs_array_muxed14;
+assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = comb_rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = comb_rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = comb_rhs_array_muxed17;
+assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = comb_rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = comb_rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = comb_rhs_array_muxed20;
+assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = comb_rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = comb_rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = comb_rhs_array_muxed23;
+assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = comb_rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = comb_rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = comb_rhs_array_muxed26;
+assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = comb_rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = comb_rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = comb_rhs_array_muxed29;
+assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = comb_rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = comb_rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = comb_rhs_array_muxed32;
+assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = comb_rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = comb_rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = comb_rhs_array_muxed35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = new_master_wdata_ready2;
+assign user_port_rdata_valid = new_master_rdata_valid9;
+always @(*) begin
+       litedramcore_interface_wdata = 128'd0;
+       case ({new_master_wdata_ready2})
+               1'd1: begin
+                       litedramcore_interface_wdata = user_port_wdata_payload_data;
+               end
+               default: begin
+                       litedramcore_interface_wdata = 1'd0;
+               end
+       endcase
+end
+always @(*) begin
+       litedramcore_interface_wdata_we = 16'd0;
+       case ({new_master_wdata_ready2})
+               1'd1: begin
+                       litedramcore_interface_wdata_we = user_port_wdata_payload_we;
+               end
+               default: begin
+                       litedramcore_interface_wdata_we = 1'd0;
+               end
+       endcase
+end
+assign user_port_rdata_payload_data = litedramcore_interface_rdata;
+assign roundrobin0_grant = 1'd0;
+assign roundrobin1_grant = 1'd0;
+assign roundrobin2_grant = 1'd0;
+assign roundrobin3_grant = 1'd0;
+assign roundrobin4_grant = 1'd0;
+assign roundrobin5_grant = 1'd0;
+assign roundrobin6_grant = 1'd0;
+assign roundrobin7_grant = 1'd0;
+assign litedramcore_wishbone_adr = wb_bus_adr;
+assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = wb_bus_sel;
+assign litedramcore_wishbone_cyc = wb_bus_cyc;
+assign litedramcore_wishbone_stb = wb_bus_stb;
+assign wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = wb_bus_we;
+assign litedramcore_wishbone_cti = wb_bus_cti;
+assign litedramcore_wishbone_bte = wb_bus_bte;
+assign wb_bus_err = litedramcore_wishbone_err;
+always @(*) begin
+       csrbank0_sel = 1'd0;
+       csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2);
+       if (interface0_bank_bus_adr[0]) begin
+               csrbank0_sel = 1'd0;
+       end
+end
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0));
+assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0));
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1));
+assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1));
+assign csrbank0_init_done0_w = init_done_storage;
+assign csrbank0_init_error0_w = init_error_storage;
+always @(*) begin
+       csrbank1_sel = 1'd0;
+       csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+       if (interface1_bank_bus_adr[0]) begin
+               csrbank1_sel = 1'd0;
+       end
+end
+assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
+assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 1'd0));
+assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 1'd0));
+assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 1'd1));
+assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 1'd1));
+assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 2'd2));
+assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
+assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 2'd3));
+assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 2'd3));
+assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
+assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd4));
+assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd4));
+assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd5));
+assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd5));
+assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd6));
+assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd6));
+assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd7));
+assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd7));
+assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd8));
+assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd8));
+assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
+assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd9));
+assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd9));
+assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
+assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd10));
+assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd10));
+assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd11));
+assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd11));
+assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd12));
+assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd12));
+assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd13));
+assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd13));
+assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd14));
+assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd14));
+assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
+assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd15));
+assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd15));
+assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
+assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd16));
+assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd16));
+assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd17));
+assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd17));
+assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd18));
+assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd18));
+assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd19));
+assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd19));
+assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd20));
+assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd20));
+assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
+assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd21));
+assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd21));
+assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
+assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd22));
+assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd22));
+assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd23));
+assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd23));
+assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
+assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd24));
+assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd24));
+assign csrbank1_dfii_control0_w = litedramcore_storage[3:0];
+assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
+assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
+assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
+assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we;
+assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
+assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
+assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
+assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we;
+assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
+assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
+assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
+assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
+assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
+assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we;
+assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
+assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
+assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
+assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
+assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
+assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we;
+assign adr = litedramcore_adr;
+assign we = litedramcore_we;
+assign dat_w = litedramcore_dat_w;
+assign litedramcore_dat_r = dat_r;
+assign interface0_bank_bus_adr = adr;
+assign interface1_bank_bus_adr = adr;
+assign interface0_bank_bus_we = we;
+assign interface1_bank_bus_we = we;
+assign interface0_bank_bus_dat_w = dat_w;
+assign interface1_bank_bus_dat_w = dat_w;
+assign dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r);
+assign slice_proxy0 = ((ddrphy_bankmodel0_row * 11'd1024) | ddrphy_bankmodel0_write_col);
+assign slice_proxy1 = ((ddrphy_bankmodel0_row * 11'd1024) | ddrphy_bankmodel0_read_col);
+assign slice_proxy2 = ((ddrphy_bankmodel1_row * 11'd1024) | ddrphy_bankmodel1_write_col);
+assign slice_proxy3 = ((ddrphy_bankmodel1_row * 11'd1024) | ddrphy_bankmodel1_read_col);
+assign slice_proxy4 = ((ddrphy_bankmodel2_row * 11'd1024) | ddrphy_bankmodel2_write_col);
+assign slice_proxy5 = ((ddrphy_bankmodel2_row * 11'd1024) | ddrphy_bankmodel2_read_col);
+assign slice_proxy6 = ((ddrphy_bankmodel3_row * 11'd1024) | ddrphy_bankmodel3_write_col);
+assign slice_proxy7 = ((ddrphy_bankmodel3_row * 11'd1024) | ddrphy_bankmodel3_read_col);
+assign slice_proxy8 = ((ddrphy_bankmodel4_row * 11'd1024) | ddrphy_bankmodel4_write_col);
+assign slice_proxy9 = ((ddrphy_bankmodel4_row * 11'd1024) | ddrphy_bankmodel4_read_col);
+assign slice_proxy10 = ((ddrphy_bankmodel5_row * 11'd1024) | ddrphy_bankmodel5_write_col);
+assign slice_proxy11 = ((ddrphy_bankmodel5_row * 11'd1024) | ddrphy_bankmodel5_read_col);
+assign slice_proxy12 = ((ddrphy_bankmodel6_row * 11'd1024) | ddrphy_bankmodel6_write_col);
+assign slice_proxy13 = ((ddrphy_bankmodel6_row * 11'd1024) | ddrphy_bankmodel6_read_col);
+assign slice_proxy14 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_write_col);
+assign slice_proxy15 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_read_col);
+always @(*) begin
+       comb_rhs_array_muxed0 = 1'd0;
+       case (litedramcore_choose_cmd_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[0];
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[1];
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[2];
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[3];
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[4];
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[5];
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[6];
+               end
+               default: begin
+                       comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[7];
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed1 = 14'd0;
+       case (litedramcore_choose_cmd_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed1 = litedramcore_bankmachine0_cmd_payload_a;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed1 = litedramcore_bankmachine1_cmd_payload_a;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed1 = litedramcore_bankmachine2_cmd_payload_a;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed1 = litedramcore_bankmachine3_cmd_payload_a;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed1 = litedramcore_bankmachine4_cmd_payload_a;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed1 = litedramcore_bankmachine5_cmd_payload_a;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed1 = litedramcore_bankmachine6_cmd_payload_a;
+               end
+               default: begin
+                       comb_rhs_array_muxed1 = litedramcore_bankmachine7_cmd_payload_a;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed2 = 3'd0;
+       case (litedramcore_choose_cmd_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed2 = litedramcore_bankmachine0_cmd_payload_ba;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed2 = litedramcore_bankmachine1_cmd_payload_ba;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed2 = litedramcore_bankmachine2_cmd_payload_ba;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed2 = litedramcore_bankmachine3_cmd_payload_ba;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed2 = litedramcore_bankmachine4_cmd_payload_ba;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed2 = litedramcore_bankmachine5_cmd_payload_ba;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed2 = litedramcore_bankmachine6_cmd_payload_ba;
+               end
+               default: begin
+                       comb_rhs_array_muxed2 = litedramcore_bankmachine7_cmd_payload_ba;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed3 = 1'd0;
+       case (litedramcore_choose_cmd_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed3 = litedramcore_bankmachine0_cmd_payload_is_read;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed3 = litedramcore_bankmachine1_cmd_payload_is_read;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed3 = litedramcore_bankmachine2_cmd_payload_is_read;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed3 = litedramcore_bankmachine3_cmd_payload_is_read;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed3 = litedramcore_bankmachine4_cmd_payload_is_read;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed3 = litedramcore_bankmachine5_cmd_payload_is_read;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed3 = litedramcore_bankmachine6_cmd_payload_is_read;
+               end
+               default: begin
+                       comb_rhs_array_muxed3 = litedramcore_bankmachine7_cmd_payload_is_read;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed4 = 1'd0;
+       case (litedramcore_choose_cmd_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed4 = litedramcore_bankmachine0_cmd_payload_is_write;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed4 = litedramcore_bankmachine1_cmd_payload_is_write;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed4 = litedramcore_bankmachine2_cmd_payload_is_write;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed4 = litedramcore_bankmachine3_cmd_payload_is_write;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed4 = litedramcore_bankmachine4_cmd_payload_is_write;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed4 = litedramcore_bankmachine5_cmd_payload_is_write;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed4 = litedramcore_bankmachine6_cmd_payload_is_write;
+               end
+               default: begin
+                       comb_rhs_array_muxed4 = litedramcore_bankmachine7_cmd_payload_is_write;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed5 = 1'd0;
+       case (litedramcore_choose_cmd_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed5 = litedramcore_bankmachine0_cmd_payload_is_cmd;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed5 = litedramcore_bankmachine1_cmd_payload_is_cmd;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed5 = litedramcore_bankmachine2_cmd_payload_is_cmd;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed5 = litedramcore_bankmachine3_cmd_payload_is_cmd;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed5 = litedramcore_bankmachine4_cmd_payload_is_cmd;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed5 = litedramcore_bankmachine5_cmd_payload_is_cmd;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed5 = litedramcore_bankmachine6_cmd_payload_is_cmd;
+               end
+               default: begin
+                       comb_rhs_array_muxed5 = litedramcore_bankmachine7_cmd_payload_is_cmd;
+               end
+       endcase
+end
+always @(*) begin
+       comb_t_array_muxed0 = 1'd0;
+       case (litedramcore_choose_cmd_grant)
+               1'd0: begin
+                       comb_t_array_muxed0 = litedramcore_bankmachine0_cmd_payload_cas;
+               end
+               1'd1: begin
+                       comb_t_array_muxed0 = litedramcore_bankmachine1_cmd_payload_cas;
+               end
+               2'd2: begin
+                       comb_t_array_muxed0 = litedramcore_bankmachine2_cmd_payload_cas;
+               end
+               2'd3: begin
+                       comb_t_array_muxed0 = litedramcore_bankmachine3_cmd_payload_cas;
+               end
+               3'd4: begin
+                       comb_t_array_muxed0 = litedramcore_bankmachine4_cmd_payload_cas;
+               end
+               3'd5: begin
+                       comb_t_array_muxed0 = litedramcore_bankmachine5_cmd_payload_cas;
+               end
+               3'd6: begin
+                       comb_t_array_muxed0 = litedramcore_bankmachine6_cmd_payload_cas;
+               end
+               default: begin
+                       comb_t_array_muxed0 = litedramcore_bankmachine7_cmd_payload_cas;
+               end
+       endcase
+end
+always @(*) begin
+       comb_t_array_muxed1 = 1'd0;
+       case (litedramcore_choose_cmd_grant)
+               1'd0: begin
+                       comb_t_array_muxed1 = litedramcore_bankmachine0_cmd_payload_ras;
+               end
+               1'd1: begin
+                       comb_t_array_muxed1 = litedramcore_bankmachine1_cmd_payload_ras;
+               end
+               2'd2: begin
+                       comb_t_array_muxed1 = litedramcore_bankmachine2_cmd_payload_ras;
+               end
+               2'd3: begin
+                       comb_t_array_muxed1 = litedramcore_bankmachine3_cmd_payload_ras;
+               end
+               3'd4: begin
+                       comb_t_array_muxed1 = litedramcore_bankmachine4_cmd_payload_ras;
+               end
+               3'd5: begin
+                       comb_t_array_muxed1 = litedramcore_bankmachine5_cmd_payload_ras;
+               end
+               3'd6: begin
+                       comb_t_array_muxed1 = litedramcore_bankmachine6_cmd_payload_ras;
+               end
+               default: begin
+                       comb_t_array_muxed1 = litedramcore_bankmachine7_cmd_payload_ras;
+               end
+       endcase
+end
+always @(*) begin
+       comb_t_array_muxed2 = 1'd0;
+       case (litedramcore_choose_cmd_grant)
+               1'd0: begin
+                       comb_t_array_muxed2 = litedramcore_bankmachine0_cmd_payload_we;
+               end
+               1'd1: begin
+                       comb_t_array_muxed2 = litedramcore_bankmachine1_cmd_payload_we;
+               end
+               2'd2: begin
+                       comb_t_array_muxed2 = litedramcore_bankmachine2_cmd_payload_we;
+               end
+               2'd3: begin
+                       comb_t_array_muxed2 = litedramcore_bankmachine3_cmd_payload_we;
+               end
+               3'd4: begin
+                       comb_t_array_muxed2 = litedramcore_bankmachine4_cmd_payload_we;
+               end
+               3'd5: begin
+                       comb_t_array_muxed2 = litedramcore_bankmachine5_cmd_payload_we;
+               end
+               3'd6: begin
+                       comb_t_array_muxed2 = litedramcore_bankmachine6_cmd_payload_we;
+               end
+               default: begin
+                       comb_t_array_muxed2 = litedramcore_bankmachine7_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed6 = 1'd0;
+       case (litedramcore_choose_req_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed6 = litedramcore_choose_req_valids[0];
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed6 = litedramcore_choose_req_valids[1];
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed6 = litedramcore_choose_req_valids[2];
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed6 = litedramcore_choose_req_valids[3];
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed6 = litedramcore_choose_req_valids[4];
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed6 = litedramcore_choose_req_valids[5];
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed6 = litedramcore_choose_req_valids[6];
+               end
+               default: begin
+                       comb_rhs_array_muxed6 = litedramcore_choose_req_valids[7];
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed7 = 14'd0;
+       case (litedramcore_choose_req_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed7 = litedramcore_bankmachine0_cmd_payload_a;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed7 = litedramcore_bankmachine1_cmd_payload_a;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed7 = litedramcore_bankmachine2_cmd_payload_a;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed7 = litedramcore_bankmachine3_cmd_payload_a;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed7 = litedramcore_bankmachine4_cmd_payload_a;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed7 = litedramcore_bankmachine5_cmd_payload_a;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed7 = litedramcore_bankmachine6_cmd_payload_a;
+               end
+               default: begin
+                       comb_rhs_array_muxed7 = litedramcore_bankmachine7_cmd_payload_a;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed8 = 3'd0;
+       case (litedramcore_choose_req_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed8 = litedramcore_bankmachine0_cmd_payload_ba;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed8 = litedramcore_bankmachine1_cmd_payload_ba;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed8 = litedramcore_bankmachine2_cmd_payload_ba;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed8 = litedramcore_bankmachine3_cmd_payload_ba;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed8 = litedramcore_bankmachine4_cmd_payload_ba;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed8 = litedramcore_bankmachine5_cmd_payload_ba;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed8 = litedramcore_bankmachine6_cmd_payload_ba;
+               end
+               default: begin
+                       comb_rhs_array_muxed8 = litedramcore_bankmachine7_cmd_payload_ba;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed9 = 1'd0;
+       case (litedramcore_choose_req_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed9 = litedramcore_bankmachine0_cmd_payload_is_read;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed9 = litedramcore_bankmachine1_cmd_payload_is_read;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed9 = litedramcore_bankmachine2_cmd_payload_is_read;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed9 = litedramcore_bankmachine3_cmd_payload_is_read;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed9 = litedramcore_bankmachine4_cmd_payload_is_read;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed9 = litedramcore_bankmachine5_cmd_payload_is_read;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed9 = litedramcore_bankmachine6_cmd_payload_is_read;
+               end
+               default: begin
+                       comb_rhs_array_muxed9 = litedramcore_bankmachine7_cmd_payload_is_read;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed10 = 1'd0;
+       case (litedramcore_choose_req_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed10 = litedramcore_bankmachine0_cmd_payload_is_write;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed10 = litedramcore_bankmachine1_cmd_payload_is_write;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed10 = litedramcore_bankmachine2_cmd_payload_is_write;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed10 = litedramcore_bankmachine3_cmd_payload_is_write;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed10 = litedramcore_bankmachine4_cmd_payload_is_write;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed10 = litedramcore_bankmachine5_cmd_payload_is_write;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed10 = litedramcore_bankmachine6_cmd_payload_is_write;
+               end
+               default: begin
+                       comb_rhs_array_muxed10 = litedramcore_bankmachine7_cmd_payload_is_write;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed11 = 1'd0;
+       case (litedramcore_choose_req_grant)
+               1'd0: begin
+                       comb_rhs_array_muxed11 = litedramcore_bankmachine0_cmd_payload_is_cmd;
+               end
+               1'd1: begin
+                       comb_rhs_array_muxed11 = litedramcore_bankmachine1_cmd_payload_is_cmd;
+               end
+               2'd2: begin
+                       comb_rhs_array_muxed11 = litedramcore_bankmachine2_cmd_payload_is_cmd;
+               end
+               2'd3: begin
+                       comb_rhs_array_muxed11 = litedramcore_bankmachine3_cmd_payload_is_cmd;
+               end
+               3'd4: begin
+                       comb_rhs_array_muxed11 = litedramcore_bankmachine4_cmd_payload_is_cmd;
+               end
+               3'd5: begin
+                       comb_rhs_array_muxed11 = litedramcore_bankmachine5_cmd_payload_is_cmd;
+               end
+               3'd6: begin
+                       comb_rhs_array_muxed11 = litedramcore_bankmachine6_cmd_payload_is_cmd;
+               end
+               default: begin
+                       comb_rhs_array_muxed11 = litedramcore_bankmachine7_cmd_payload_is_cmd;
+               end
+       endcase
+end
+always @(*) begin
+       comb_t_array_muxed3 = 1'd0;
+       case (litedramcore_choose_req_grant)
+               1'd0: begin
+                       comb_t_array_muxed3 = litedramcore_bankmachine0_cmd_payload_cas;
+               end
+               1'd1: begin
+                       comb_t_array_muxed3 = litedramcore_bankmachine1_cmd_payload_cas;
+               end
+               2'd2: begin
+                       comb_t_array_muxed3 = litedramcore_bankmachine2_cmd_payload_cas;
+               end
+               2'd3: begin
+                       comb_t_array_muxed3 = litedramcore_bankmachine3_cmd_payload_cas;
+               end
+               3'd4: begin
+                       comb_t_array_muxed3 = litedramcore_bankmachine4_cmd_payload_cas;
+               end
+               3'd5: begin
+                       comb_t_array_muxed3 = litedramcore_bankmachine5_cmd_payload_cas;
+               end
+               3'd6: begin
+                       comb_t_array_muxed3 = litedramcore_bankmachine6_cmd_payload_cas;
+               end
+               default: begin
+                       comb_t_array_muxed3 = litedramcore_bankmachine7_cmd_payload_cas;
+               end
+       endcase
+end
+always @(*) begin
+       comb_t_array_muxed4 = 1'd0;
+       case (litedramcore_choose_req_grant)
+               1'd0: begin
+                       comb_t_array_muxed4 = litedramcore_bankmachine0_cmd_payload_ras;
+               end
+               1'd1: begin
+                       comb_t_array_muxed4 = litedramcore_bankmachine1_cmd_payload_ras;
+               end
+               2'd2: begin
+                       comb_t_array_muxed4 = litedramcore_bankmachine2_cmd_payload_ras;
+               end
+               2'd3: begin
+                       comb_t_array_muxed4 = litedramcore_bankmachine3_cmd_payload_ras;
+               end
+               3'd4: begin
+                       comb_t_array_muxed4 = litedramcore_bankmachine4_cmd_payload_ras;
+               end
+               3'd5: begin
+                       comb_t_array_muxed4 = litedramcore_bankmachine5_cmd_payload_ras;
+               end
+               3'd6: begin
+                       comb_t_array_muxed4 = litedramcore_bankmachine6_cmd_payload_ras;
+               end
+               default: begin
+                       comb_t_array_muxed4 = litedramcore_bankmachine7_cmd_payload_ras;
+               end
+       endcase
+end
+always @(*) begin
+       comb_t_array_muxed5 = 1'd0;
+       case (litedramcore_choose_req_grant)
+               1'd0: begin
+                       comb_t_array_muxed5 = litedramcore_bankmachine0_cmd_payload_we;
+               end
+               1'd1: begin
+                       comb_t_array_muxed5 = litedramcore_bankmachine1_cmd_payload_we;
+               end
+               2'd2: begin
+                       comb_t_array_muxed5 = litedramcore_bankmachine2_cmd_payload_we;
+               end
+               2'd3: begin
+                       comb_t_array_muxed5 = litedramcore_bankmachine3_cmd_payload_we;
+               end
+               3'd4: begin
+                       comb_t_array_muxed5 = litedramcore_bankmachine4_cmd_payload_we;
+               end
+               3'd5: begin
+                       comb_t_array_muxed5 = litedramcore_bankmachine5_cmd_payload_we;
+               end
+               3'd6: begin
+                       comb_t_array_muxed5 = litedramcore_bankmachine6_cmd_payload_we;
+               end
+               default: begin
+                       comb_t_array_muxed5 = litedramcore_bankmachine7_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed12 = 21'd0;
+       case (roundrobin0_grant)
+               default: begin
+                       comb_rhs_array_muxed12 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed13 = 1'd0;
+       case (roundrobin0_grant)
+               default: begin
+                       comb_rhs_array_muxed13 = user_port_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed14 = 1'd0;
+       case (roundrobin0_grant)
+               default: begin
+                       comb_rhs_array_muxed14 = (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed15 = 21'd0;
+       case (roundrobin1_grant)
+               default: begin
+                       comb_rhs_array_muxed15 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed16 = 1'd0;
+       case (roundrobin1_grant)
+               default: begin
+                       comb_rhs_array_muxed16 = user_port_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed17 = 1'd0;
+       case (roundrobin1_grant)
+               default: begin
+                       comb_rhs_array_muxed17 = (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed18 = 21'd0;
+       case (roundrobin2_grant)
+               default: begin
+                       comb_rhs_array_muxed18 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed19 = 1'd0;
+       case (roundrobin2_grant)
+               default: begin
+                       comb_rhs_array_muxed19 = user_port_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed20 = 1'd0;
+       case (roundrobin2_grant)
+               default: begin
+                       comb_rhs_array_muxed20 = (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed21 = 21'd0;
+       case (roundrobin3_grant)
+               default: begin
+                       comb_rhs_array_muxed21 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed22 = 1'd0;
+       case (roundrobin3_grant)
+               default: begin
+                       comb_rhs_array_muxed22 = user_port_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed23 = 1'd0;
+       case (roundrobin3_grant)
+               default: begin
+                       comb_rhs_array_muxed23 = (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed24 = 21'd0;
+       case (roundrobin4_grant)
+               default: begin
+                       comb_rhs_array_muxed24 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed25 = 1'd0;
+       case (roundrobin4_grant)
+               default: begin
+                       comb_rhs_array_muxed25 = user_port_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed26 = 1'd0;
+       case (roundrobin4_grant)
+               default: begin
+                       comb_rhs_array_muxed26 = (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed27 = 21'd0;
+       case (roundrobin5_grant)
+               default: begin
+                       comb_rhs_array_muxed27 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed28 = 1'd0;
+       case (roundrobin5_grant)
+               default: begin
+                       comb_rhs_array_muxed28 = user_port_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed29 = 1'd0;
+       case (roundrobin5_grant)
+               default: begin
+                       comb_rhs_array_muxed29 = (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed30 = 21'd0;
+       case (roundrobin6_grant)
+               default: begin
+                       comb_rhs_array_muxed30 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed31 = 1'd0;
+       case (roundrobin6_grant)
+               default: begin
+                       comb_rhs_array_muxed31 = user_port_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed32 = 1'd0;
+       case (roundrobin6_grant)
+               default: begin
+                       comb_rhs_array_muxed32 = (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed33 = 21'd0;
+       case (roundrobin7_grant)
+               default: begin
+                       comb_rhs_array_muxed33 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed34 = 1'd0;
+       case (roundrobin7_grant)
+               default: begin
+                       comb_rhs_array_muxed34 = user_port_cmd_payload_we;
+               end
+       endcase
+end
+always @(*) begin
+       comb_rhs_array_muxed35 = 1'd0;
+       case (roundrobin7_grant)
+               default: begin
+                       comb_rhs_array_muxed35 = (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed0 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed1 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next0)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed2 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed3 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next1)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed4 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed5 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next2)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed6 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed7 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next3)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed8 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed9 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next4)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed10 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed11 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next5)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed12 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed13 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next6)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed14 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed15 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next7)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed16 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed17 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next8)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed18 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed19 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next9)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed20 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed21 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next10)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed22 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed23 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next11)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed24 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed25 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next12)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed26 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed27 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next13)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed28 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed29 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next14)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed30 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed31 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next15)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed32 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed33 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next16)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed34 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed35 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next17)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed36 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed37 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next18)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed38 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed39 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next19)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed40 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed41 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next20)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed42 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed43 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next21)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed44 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed45 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next22)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed46 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed47 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next23)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed48 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed49 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next24)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed50 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed51 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next25)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed52 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed53 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next26)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed54 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed55 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next27)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed56 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed57 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next28)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed58 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed59 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next29)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed60 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed61 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next30)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed62 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_curr)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_basiclowerer_array_muxed63 = 64'd0;
+       case (ddrphy_dfitimingschecker_act_next31)
+               1'd0: begin
+                       sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker0;
+               end
+               1'd1: begin
+                       sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker1;
+               end
+               2'd2: begin
+                       sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker2;
+               end
+               default: begin
+                       sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker3;
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed0 = 3'd0;
+       case (litedramcore_steerer_sel0)
+               1'd0: begin
+                       sync_rhs_array_muxed0 = litedramcore_nop_ba[2:0];
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed0 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed0 = litedramcore_choose_req_cmd_payload_ba[2:0];
+               end
+               default: begin
+                       sync_rhs_array_muxed0 = litedramcore_cmd_payload_ba[2:0];
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed1 = 14'd0;
+       case (litedramcore_steerer_sel0)
+               1'd0: begin
+                       sync_rhs_array_muxed1 = litedramcore_nop_a;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed1 = litedramcore_choose_cmd_cmd_payload_a;
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed1 = litedramcore_choose_req_cmd_payload_a;
+               end
+               default: begin
+                       sync_rhs_array_muxed1 = litedramcore_cmd_payload_a;
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed2 = 1'd0;
+       case (litedramcore_steerer_sel0)
+               1'd0: begin
+                       sync_rhs_array_muxed2 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed2 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed2 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+               end
+               default: begin
+                       sync_rhs_array_muxed2 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed3 = 1'd0;
+       case (litedramcore_steerer_sel0)
+               1'd0: begin
+                       sync_rhs_array_muxed3 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed3 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed3 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+               end
+               default: begin
+                       sync_rhs_array_muxed3 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed4 = 1'd0;
+       case (litedramcore_steerer_sel0)
+               1'd0: begin
+                       sync_rhs_array_muxed4 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed4 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed4 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+               end
+               default: begin
+                       sync_rhs_array_muxed4 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed5 = 1'd0;
+       case (litedramcore_steerer_sel0)
+               1'd0: begin
+                       sync_rhs_array_muxed5 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed5 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed5 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+               end
+               default: begin
+                       sync_rhs_array_muxed5 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed6 = 1'd0;
+       case (litedramcore_steerer_sel0)
+               1'd0: begin
+                       sync_rhs_array_muxed6 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed6 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed6 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+               end
+               default: begin
+                       sync_rhs_array_muxed6 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed7 = 3'd0;
+       case (litedramcore_steerer_sel1)
+               1'd0: begin
+                       sync_rhs_array_muxed7 = litedramcore_nop_ba[2:0];
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed7 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed7 = litedramcore_choose_req_cmd_payload_ba[2:0];
+               end
+               default: begin
+                       sync_rhs_array_muxed7 = litedramcore_cmd_payload_ba[2:0];
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed8 = 14'd0;
+       case (litedramcore_steerer_sel1)
+               1'd0: begin
+                       sync_rhs_array_muxed8 = litedramcore_nop_a;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed8 = litedramcore_choose_cmd_cmd_payload_a;
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed8 = litedramcore_choose_req_cmd_payload_a;
+               end
+               default: begin
+                       sync_rhs_array_muxed8 = litedramcore_cmd_payload_a;
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed9 = 1'd0;
+       case (litedramcore_steerer_sel1)
+               1'd0: begin
+                       sync_rhs_array_muxed9 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed9 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed9 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+               end
+               default: begin
+                       sync_rhs_array_muxed9 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed10 = 1'd0;
+       case (litedramcore_steerer_sel1)
+               1'd0: begin
+                       sync_rhs_array_muxed10 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed10 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed10 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+               end
+               default: begin
+                       sync_rhs_array_muxed10 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed11 = 1'd0;
+       case (litedramcore_steerer_sel1)
+               1'd0: begin
+                       sync_rhs_array_muxed11 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed11 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed11 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+               end
+               default: begin
+                       sync_rhs_array_muxed11 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed12 = 1'd0;
+       case (litedramcore_steerer_sel1)
+               1'd0: begin
+                       sync_rhs_array_muxed12 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed12 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed12 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+               end
+               default: begin
+                       sync_rhs_array_muxed12 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed13 = 1'd0;
+       case (litedramcore_steerer_sel1)
+               1'd0: begin
+                       sync_rhs_array_muxed13 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed13 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed13 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+               end
+               default: begin
+                       sync_rhs_array_muxed13 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed14 = 3'd0;
+       case (litedramcore_steerer_sel2)
+               1'd0: begin
+                       sync_rhs_array_muxed14 = litedramcore_nop_ba[2:0];
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed14 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed14 = litedramcore_choose_req_cmd_payload_ba[2:0];
+               end
+               default: begin
+                       sync_rhs_array_muxed14 = litedramcore_cmd_payload_ba[2:0];
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed15 = 14'd0;
+       case (litedramcore_steerer_sel2)
+               1'd0: begin
+                       sync_rhs_array_muxed15 = litedramcore_nop_a;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed15 = litedramcore_choose_cmd_cmd_payload_a;
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed15 = litedramcore_choose_req_cmd_payload_a;
+               end
+               default: begin
+                       sync_rhs_array_muxed15 = litedramcore_cmd_payload_a;
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed16 = 1'd0;
+       case (litedramcore_steerer_sel2)
+               1'd0: begin
+                       sync_rhs_array_muxed16 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed16 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed16 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+               end
+               default: begin
+                       sync_rhs_array_muxed16 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed17 = 1'd0;
+       case (litedramcore_steerer_sel2)
+               1'd0: begin
+                       sync_rhs_array_muxed17 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed17 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed17 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+               end
+               default: begin
+                       sync_rhs_array_muxed17 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed18 = 1'd0;
+       case (litedramcore_steerer_sel2)
+               1'd0: begin
+                       sync_rhs_array_muxed18 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed18 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed18 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+               end
+               default: begin
+                       sync_rhs_array_muxed18 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed19 = 1'd0;
+       case (litedramcore_steerer_sel2)
+               1'd0: begin
+                       sync_rhs_array_muxed19 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed19 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed19 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+               end
+               default: begin
+                       sync_rhs_array_muxed19 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed20 = 1'd0;
+       case (litedramcore_steerer_sel2)
+               1'd0: begin
+                       sync_rhs_array_muxed20 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed20 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed20 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+               end
+               default: begin
+                       sync_rhs_array_muxed20 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed21 = 3'd0;
+       case (litedramcore_steerer_sel3)
+               1'd0: begin
+                       sync_rhs_array_muxed21 = litedramcore_nop_ba[2:0];
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed21 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed21 = litedramcore_choose_req_cmd_payload_ba[2:0];
+               end
+               default: begin
+                       sync_rhs_array_muxed21 = litedramcore_cmd_payload_ba[2:0];
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed22 = 14'd0;
+       case (litedramcore_steerer_sel3)
+               1'd0: begin
+                       sync_rhs_array_muxed22 = litedramcore_nop_a;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed22 = litedramcore_choose_cmd_cmd_payload_a;
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed22 = litedramcore_choose_req_cmd_payload_a;
+               end
+               default: begin
+                       sync_rhs_array_muxed22 = litedramcore_cmd_payload_a;
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed23 = 1'd0;
+       case (litedramcore_steerer_sel3)
+               1'd0: begin
+                       sync_rhs_array_muxed23 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed23 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed23 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+               end
+               default: begin
+                       sync_rhs_array_muxed23 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed24 = 1'd0;
+       case (litedramcore_steerer_sel3)
+               1'd0: begin
+                       sync_rhs_array_muxed24 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed24 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed24 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+               end
+               default: begin
+                       sync_rhs_array_muxed24 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed25 = 1'd0;
+       case (litedramcore_steerer_sel3)
+               1'd0: begin
+                       sync_rhs_array_muxed25 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed25 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed25 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+               end
+               default: begin
+                       sync_rhs_array_muxed25 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed26 = 1'd0;
+       case (litedramcore_steerer_sel3)
+               1'd0: begin
+                       sync_rhs_array_muxed26 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed26 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed26 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+               end
+               default: begin
+                       sync_rhs_array_muxed26 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+               end
+       endcase
+end
+always @(*) begin
+       sync_rhs_array_muxed27 = 1'd0;
+       case (litedramcore_steerer_sel3)
+               1'd0: begin
+                       sync_rhs_array_muxed27 = 1'd0;
+               end
+               1'd1: begin
+                       sync_rhs_array_muxed27 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+               end
+               2'd2: begin
+                       sync_rhs_array_muxed27 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+               end
+               default: begin
+                       sync_rhs_array_muxed27 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+               end
+       endcase
+end
+
+always @(posedge por_clk) begin
+       int_rst <= 1'd0;
+end
+
+always @(posedge sys_clk) begin
+       state <= next_state;
+       ddrphy_new_bank_write0 <= ddrphy_bank_write0;
+       ddrphy_new_bank_write_col0 <= ddrphy_bank_write_col0;
+       ddrphy_new_bank_write1 <= ddrphy_new_bank_write0;
+       ddrphy_new_bank_write_col1 <= ddrphy_new_bank_write_col0;
+       ddrphy_new_bank_write2 <= ddrphy_bank_write1;
+       ddrphy_new_bank_write_col2 <= ddrphy_bank_write_col1;
+       ddrphy_new_bank_write3 <= ddrphy_new_bank_write2;
+       ddrphy_new_bank_write_col3 <= ddrphy_new_bank_write_col2;
+       ddrphy_new_bank_write4 <= ddrphy_bank_write2;
+       ddrphy_new_bank_write_col4 <= ddrphy_bank_write_col2;
+       ddrphy_new_bank_write5 <= ddrphy_new_bank_write4;
+       ddrphy_new_bank_write_col5 <= ddrphy_new_bank_write_col4;
+       ddrphy_new_bank_write6 <= ddrphy_bank_write3;
+       ddrphy_new_bank_write_col6 <= ddrphy_bank_write_col3;
+       ddrphy_new_bank_write7 <= ddrphy_new_bank_write6;
+       ddrphy_new_bank_write_col7 <= ddrphy_new_bank_write_col6;
+       ddrphy_new_bank_write8 <= ddrphy_bank_write4;
+       ddrphy_new_bank_write_col8 <= ddrphy_bank_write_col4;
+       ddrphy_new_bank_write9 <= ddrphy_new_bank_write8;
+       ddrphy_new_bank_write_col9 <= ddrphy_new_bank_write_col8;
+       ddrphy_new_bank_write10 <= ddrphy_bank_write5;
+       ddrphy_new_bank_write_col10 <= ddrphy_bank_write_col5;
+       ddrphy_new_bank_write11 <= ddrphy_new_bank_write10;
+       ddrphy_new_bank_write_col11 <= ddrphy_new_bank_write_col10;
+       ddrphy_new_bank_write12 <= ddrphy_bank_write6;
+       ddrphy_new_bank_write_col12 <= ddrphy_bank_write_col6;
+       ddrphy_new_bank_write13 <= ddrphy_new_bank_write12;
+       ddrphy_new_bank_write_col13 <= ddrphy_new_bank_write_col12;
+       ddrphy_new_bank_write14 <= ddrphy_bank_write7;
+       ddrphy_new_bank_write_col14 <= ddrphy_bank_write_col7;
+       ddrphy_new_bank_write15 <= ddrphy_new_bank_write14;
+       ddrphy_new_bank_write_col15 <= ddrphy_new_bank_write_col14;
+       ddrphy_new_banks_read0 <= ddrphy_banks_read;
+       ddrphy_new_banks_read_data0 <= ddrphy_banks_read_data;
+       ddrphy_new_banks_read1 <= ddrphy_new_banks_read0;
+       ddrphy_new_banks_read_data1 <= ddrphy_new_banks_read_data0;
+       ddrphy_new_banks_read2 <= ddrphy_new_banks_read1;
+       ddrphy_new_banks_read_data2 <= ddrphy_new_banks_read_data1;
+       ddrphy_new_banks_read3 <= ddrphy_new_banks_read2;
+       ddrphy_new_banks_read_data3 <= ddrphy_new_banks_read_data2;
+       ddrphy_new_banks_read4 <= ddrphy_new_banks_read3;
+       ddrphy_new_banks_read_data4 <= ddrphy_new_banks_read_data3;
+       ddrphy_new_banks_read5 <= ddrphy_new_banks_read4;
+       ddrphy_new_banks_read_data5 <= ddrphy_new_banks_read_data4;
+       ddrphy_new_banks_read6 <= ddrphy_new_banks_read5;
+       ddrphy_new_banks_read_data6 <= ddrphy_new_banks_read_data5;
+       ddrphy_new_banks_read7 <= ddrphy_new_banks_read6;
+       ddrphy_new_banks_read_data7 <= ddrphy_new_banks_read_data6;
+       ddrphy_new_banks_read8 <= ddrphy_new_banks_read7;
+       ddrphy_new_banks_read_data8 <= ddrphy_new_banks_read_data7;
+       ddrphy_dfitimingschecker_cnt <= (ddrphy_dfitimingschecker_cnt + 3'd4);
+       if (((ddrphy_dfitimingschecker_cmd_recv0 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv0 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv0 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv0) begin
+               ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv1 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv1) begin
+               ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv2) begin
+               ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed0 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed1 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv2) begin
+               sync_t_array_muxed0 = ddrphy_dfitimingschecker_ps0;
+               case (ddrphy_dfitimingschecker_act_next0)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed0;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed0;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed0;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed0;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv3) begin
+               ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv4 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv4 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv4 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv4) begin
+               ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv5) begin
+               ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv6 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv6 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv6 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv6) begin
+               ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv7 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv7) begin
+               ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv8) begin
+               ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed2 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed3 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv8) begin
+               sync_t_array_muxed1 = ddrphy_dfitimingschecker_ps0;
+               case (ddrphy_dfitimingschecker_act_next1)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed1;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed1;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed1;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed1;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv9) begin
+               ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv10 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv10 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv10 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv10) begin
+               ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv11) begin
+               ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv12 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv12 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv12 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv12) begin
+               ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv13 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv13) begin
+               ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv14) begin
+               ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed4 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed5 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv14) begin
+               sync_t_array_muxed2 = ddrphy_dfitimingschecker_ps0;
+               case (ddrphy_dfitimingschecker_act_next2)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed2;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed2;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed2;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed2;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv15) begin
+               ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv16 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv16 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv16 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv16) begin
+               ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv17) begin
+               ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv18 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv18 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv18 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv18) begin
+               ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv19 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv19) begin
+               ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv20) begin
+               ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed6 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed7 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv20) begin
+               sync_t_array_muxed3 = ddrphy_dfitimingschecker_ps0;
+               case (ddrphy_dfitimingschecker_act_next3)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed3;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed3;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed3;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed3;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv21) begin
+               ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv22 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv22 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv22 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv22) begin
+               ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv23) begin
+               ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv24 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv24 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv24 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv24) begin
+               ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv25 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv25) begin
+               ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv26) begin
+               ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed8 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed9 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv26) begin
+               sync_t_array_muxed4 = ddrphy_dfitimingschecker_ps0;
+               case (ddrphy_dfitimingschecker_act_next4)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed4;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed4;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed4;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed4;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next4;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv27) begin
+               ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv28 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv28 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv28 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv28) begin
+               ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv29) begin
+               ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv30 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv30 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv30 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv30) begin
+               ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv31 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv31) begin
+               ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv32) begin
+               ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed10 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed11 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv32) begin
+               sync_t_array_muxed5 = ddrphy_dfitimingschecker_ps0;
+               case (ddrphy_dfitimingschecker_act_next5)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed5;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed5;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed5;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed5;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next5;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv33) begin
+               ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv34 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv34 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv34 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv34) begin
+               ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv35) begin
+               ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv36 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv36 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv36 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv36) begin
+               ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv37 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv37) begin
+               ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv38) begin
+               ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed12 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed13 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv38) begin
+               sync_t_array_muxed6 = ddrphy_dfitimingschecker_ps0;
+               case (ddrphy_dfitimingschecker_act_next6)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed6;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed6;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed6;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed6;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next6;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv39) begin
+               ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv40 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv40 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv40 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv40) begin
+               ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv41) begin
+               ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv42 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv42 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv42 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv42) begin
+               ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv43 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv43) begin
+               ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv44) begin
+               ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed14 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed15 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv44) begin
+               sync_t_array_muxed7 = ddrphy_dfitimingschecker_ps0;
+               case (ddrphy_dfitimingschecker_act_next7)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed7;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed7;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed7;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed7;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next7;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv45) begin
+               ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv46 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv46 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv46 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv46) begin
+               ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv47) begin
+               ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps0;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv48 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv48 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv48 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv48) begin
+               ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv49 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv49) begin
+               ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv50) begin
+               ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed16 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed17 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv50) begin
+               sync_t_array_muxed8 = ddrphy_dfitimingschecker_ps1;
+               case (ddrphy_dfitimingschecker_act_next8)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed8;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed8;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed8;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed8;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next8;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv51) begin
+               ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv52 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv52 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv52 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv52) begin
+               ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv53) begin
+               ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv54 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv54 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv54 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv54) begin
+               ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv55 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv55) begin
+               ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv56) begin
+               ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed18 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed19 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv56) begin
+               sync_t_array_muxed9 = ddrphy_dfitimingschecker_ps1;
+               case (ddrphy_dfitimingschecker_act_next9)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed9;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed9;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed9;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed9;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next9;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv57) begin
+               ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv58 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv58 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv58 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv58) begin
+               ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv59) begin
+               ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv60 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv60 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv60 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv60) begin
+               ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv61 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv61) begin
+               ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv62) begin
+               ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed20 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed21 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv62) begin
+               sync_t_array_muxed10 = ddrphy_dfitimingschecker_ps1;
+               case (ddrphy_dfitimingschecker_act_next10)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed10;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed10;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed10;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed10;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next10;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv63) begin
+               ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv64 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv64 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv64 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv64) begin
+               ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv65) begin
+               ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv66 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv66 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv66 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv66) begin
+               ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv67 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv67) begin
+               ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv68) begin
+               ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed22 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed23 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv68) begin
+               sync_t_array_muxed11 = ddrphy_dfitimingschecker_ps1;
+               case (ddrphy_dfitimingschecker_act_next11)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed11;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed11;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed11;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed11;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next11;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv69) begin
+               ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv70 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv70 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv70 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv70) begin
+               ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv71) begin
+               ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv72 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv72 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv72 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv72) begin
+               ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv73 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv73) begin
+               ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv74) begin
+               ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed24 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed25 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv74) begin
+               sync_t_array_muxed12 = ddrphy_dfitimingschecker_ps1;
+               case (ddrphy_dfitimingschecker_act_next12)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed12;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed12;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed12;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed12;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next12;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv75) begin
+               ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv76 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv76 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv76 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv76) begin
+               ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv77) begin
+               ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv78 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv78 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv78 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv78) begin
+               ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv79 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv79) begin
+               ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv80) begin
+               ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed26 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed27 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv80) begin
+               sync_t_array_muxed13 = ddrphy_dfitimingschecker_ps1;
+               case (ddrphy_dfitimingschecker_act_next13)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed13;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed13;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed13;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed13;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next13;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv81) begin
+               ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv82 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv82 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv82 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv82) begin
+               ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv83) begin
+               ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv84 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv84 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv84 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv84) begin
+               ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv85 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv85) begin
+               ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv86) begin
+               ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed28 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed29 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv86) begin
+               sync_t_array_muxed14 = ddrphy_dfitimingschecker_ps1;
+               case (ddrphy_dfitimingschecker_act_next14)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed14;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed14;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed14;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed14;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next14;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv87) begin
+               ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv88 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv88 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv88 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv88) begin
+               ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv89) begin
+               ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv90 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv90 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv90 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv90) begin
+               ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv91 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv91) begin
+               ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv92) begin
+               ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed30 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed31 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv92) begin
+               sync_t_array_muxed15 = ddrphy_dfitimingschecker_ps1;
+               case (ddrphy_dfitimingschecker_act_next15)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed15;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed15;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed15;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed15;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next15;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv93) begin
+               ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv94 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv94 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv94 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv94) begin
+               ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv95) begin
+               ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps1;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv96 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv96 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv96 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv96) begin
+               ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv97 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv97) begin
+               ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv98) begin
+               ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed32 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed33 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv98) begin
+               sync_t_array_muxed16 = ddrphy_dfitimingschecker_ps2;
+               case (ddrphy_dfitimingschecker_act_next16)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed16;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed16;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed16;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed16;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next16;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv99) begin
+               ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv100 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv100 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv100 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv100) begin
+               ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv101) begin
+               ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv102 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv102 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv102 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv102) begin
+               ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv103 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv103) begin
+               ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv104) begin
+               ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed34 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed35 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv104) begin
+               sync_t_array_muxed17 = ddrphy_dfitimingschecker_ps2;
+               case (ddrphy_dfitimingschecker_act_next17)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed17;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed17;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed17;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed17;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next17;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv105) begin
+               ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv106 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv106 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv106 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv106) begin
+               ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv107) begin
+               ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv108 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv108 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv108 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv108) begin
+               ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv109 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv109) begin
+               ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv110) begin
+               ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed36 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed37 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv110) begin
+               sync_t_array_muxed18 = ddrphy_dfitimingschecker_ps2;
+               case (ddrphy_dfitimingschecker_act_next18)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed18;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed18;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed18;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed18;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next18;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv111) begin
+               ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv112 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv112 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv112 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv112) begin
+               ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv113) begin
+               ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv114 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv114 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv114 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv114) begin
+               ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv115 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv115) begin
+               ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv116) begin
+               ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed38 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed39 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv116) begin
+               sync_t_array_muxed19 = ddrphy_dfitimingschecker_ps2;
+               case (ddrphy_dfitimingschecker_act_next19)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed19;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed19;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed19;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed19;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next19;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv117) begin
+               ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv118 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv118 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv118 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv118) begin
+               ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv119) begin
+               ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv120 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv120 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv120 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv120) begin
+               ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv121 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv121) begin
+               ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv122) begin
+               ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed40 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed41 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv122) begin
+               sync_t_array_muxed20 = ddrphy_dfitimingschecker_ps2;
+               case (ddrphy_dfitimingschecker_act_next20)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed20;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed20;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed20;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed20;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next20;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv123) begin
+               ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv124 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv124 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv124 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv124) begin
+               ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv125) begin
+               ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv126 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv126 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv126 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv126) begin
+               ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv127 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv127) begin
+               ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv128) begin
+               ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed42 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed43 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv128) begin
+               sync_t_array_muxed21 = ddrphy_dfitimingschecker_ps2;
+               case (ddrphy_dfitimingschecker_act_next21)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed21;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed21;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed21;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed21;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next21;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv129) begin
+               ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv130 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv130 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv130 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv130) begin
+               ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv131) begin
+               ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv132 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv132 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv132 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv132) begin
+               ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv133 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv133) begin
+               ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv134) begin
+               ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed44 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed45 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv134) begin
+               sync_t_array_muxed22 = ddrphy_dfitimingschecker_ps2;
+               case (ddrphy_dfitimingschecker_act_next22)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed22;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed22;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed22;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed22;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next22;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv135) begin
+               ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv136 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv136 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv136 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv136) begin
+               ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv137) begin
+               ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv138 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv138 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv138 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv138) begin
+               ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv139 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv139) begin
+               ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv140) begin
+               ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed46 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed47 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv140) begin
+               sync_t_array_muxed23 = ddrphy_dfitimingschecker_ps2;
+               case (ddrphy_dfitimingschecker_act_next23)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed23;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed23;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed23;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed23;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next23;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv141) begin
+               ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv142 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv142 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv142 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv142) begin
+               ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv143) begin
+               ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps2;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv144 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv144 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv144 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv144) begin
+               ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv145 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv145) begin
+               ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv146) begin
+               ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed48 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed49 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv146) begin
+               sync_t_array_muxed24 = ddrphy_dfitimingschecker_ps3;
+               case (ddrphy_dfitimingschecker_act_next24)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed24;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed24;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed24;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed24;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next24;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv147) begin
+               ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv148 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv148 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv148 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv148) begin
+               ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv149) begin
+               ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv150 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv150 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv150 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv150) begin
+               ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv151 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv151) begin
+               ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv152) begin
+               ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed50 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed51 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv152) begin
+               sync_t_array_muxed25 = ddrphy_dfitimingschecker_ps3;
+               case (ddrphy_dfitimingschecker_act_next25)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed25;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed25;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed25;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed25;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next25;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv153) begin
+               ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv154 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv154 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv154 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv154) begin
+               ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv155) begin
+               ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv156 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv156 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv156 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv156) begin
+               ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv157 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv157) begin
+               ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv158) begin
+               ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed52 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed53 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv158) begin
+               sync_t_array_muxed26 = ddrphy_dfitimingschecker_ps3;
+               case (ddrphy_dfitimingschecker_act_next26)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed26;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed26;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed26;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed26;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next26;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv159) begin
+               ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv160 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv160 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv160 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv160) begin
+               ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv161) begin
+               ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv162 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv162 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv162 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv162) begin
+               ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv163 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv163) begin
+               ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv164) begin
+               ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed54 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed55 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv164) begin
+               sync_t_array_muxed27 = ddrphy_dfitimingschecker_ps3;
+               case (ddrphy_dfitimingschecker_act_next27)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed27;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed27;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed27;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed27;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next27;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv165) begin
+               ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv166 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv166 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv166 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv166) begin
+               ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv167) begin
+               ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv168 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv168 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv168 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv168) begin
+               ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv169 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv169) begin
+               ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv170) begin
+               ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed56 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed57 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv170) begin
+               sync_t_array_muxed28 = ddrphy_dfitimingschecker_ps3;
+               case (ddrphy_dfitimingschecker_act_next28)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed28;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed28;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed28;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed28;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next28;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv171) begin
+               ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv172 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv172 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv172 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv172) begin
+               ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv173) begin
+               ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv174 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv174 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv174 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv174) begin
+               ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv175 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv175) begin
+               ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv176) begin
+               ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed58 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed59 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv176) begin
+               sync_t_array_muxed29 = ddrphy_dfitimingschecker_ps3;
+               case (ddrphy_dfitimingschecker_act_next29)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed29;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed29;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed29;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed29;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next29;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv177) begin
+               ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv178 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv178 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv178 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv178) begin
+               ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv179) begin
+               ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv180 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv180 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv180 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv180) begin
+               ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv181 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv181) begin
+               ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv182) begin
+               ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed60 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed61 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv182) begin
+               sync_t_array_muxed30 = ddrphy_dfitimingschecker_ps3;
+               case (ddrphy_dfitimingschecker_act_next30)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed30;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed30;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed30;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed30;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next30;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv183) begin
+               ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv184 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv184 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv184 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv184) begin
+               ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv185) begin
+               ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv186 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
+               $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv186 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin
+               $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv186 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin
+               $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv186) begin
+               ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv187 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
+               $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv187) begin
+               ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
+               $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
+               $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin
+               $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin
+               $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv188) begin
+               ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed62 + 14'd10000)))) begin
+               $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if ((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed63 + 16'd40000)))) begin
+               $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv188) begin
+               sync_t_array_muxed31 = ddrphy_dfitimingschecker_ps3;
+               case (ddrphy_dfitimingschecker_act_next31)
+                       1'd0: begin
+                               ddrphy_dfitimingschecker0 <= sync_t_array_muxed31;
+                       end
+                       1'd1: begin
+                               ddrphy_dfitimingschecker1 <= sync_t_array_muxed31;
+                       end
+                       2'd2: begin
+                               ddrphy_dfitimingschecker2 <= sync_t_array_muxed31;
+                       end
+                       default: begin
+                               ddrphy_dfitimingschecker3 <= sync_t_array_muxed31;
+                       end
+               endcase
+               ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next31;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
+               $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
+               $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin
+               $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv189) begin
+               ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv190 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
+               $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv190 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
+               $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (((ddrphy_dfitimingschecker_cmd_recv190 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
+               $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv190) begin
+               ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
+       end
+       if (ddrphy_dfitimingschecker_cmd_recv191) begin
+               ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
+       end
+       if ((ddrphy_dfitimingschecker_ref_ps_mod < 36'd64000000000)) begin
+               ddrphy_dfitimingschecker_ref_ps_mod <= (ddrphy_dfitimingschecker_ref_ps_mod + 14'd10000);
+       end else begin
+               ddrphy_dfitimingschecker_ref_ps_mod <= 1'd0;
+       end
+       if ((ddrphy_dfitimingschecker_ref_issued != 1'd0)) begin
+               ddrphy_dfitimingschecker_ref_ps <= ddrphy_dfitimingschecker_ps3;
+               ddrphy_dfitimingschecker_ref_ps_diff <= (ddrphy_dfitimingschecker_ref_ps_diff - ddrphy_dfitimingschecker_curr_diff);
+       end
+       if (($signed({1'd0, (ddrphy_dfitimingschecker_ref_ps_mod == 1'd0)}) & (ddrphy_dfitimingschecker_ref_ps_diff > $signed({1'd0, 1'd0})))) begin
+               $display("[%016dps] tREFI violation (64ms period): %0d", ddrphy_dfitimingschecker_ps3, ddrphy_dfitimingschecker_ref_ps_diff);
+       end
+       if ((ddrphy_dfitimingschecker_ref_issued != 1'd0)) begin
+               ddrphy_dfitimingschecker_ref_done <= 1'd1;
+       end
+       if ((((ddrphy_dfitimingschecker_ref_issued == 1'd0) & ddrphy_dfitimingschecker_ref_done) & (ddrphy_dfitimingschecker_ref_ps > (ddrphy_dfitimingschecker_ps3 + 27'd70312500)))) begin
+               $display("[%016dps] tREFI violation (too many postponed refreshes)", ddrphy_dfitimingschecker_ps3);
+               ddrphy_dfitimingschecker_ref_done <= 1'd0;
+       end
+       if (ddrphy_bankmodel0_precharge) begin
+               ddrphy_bankmodel0_active <= 1'd0;
+       end else begin
+               if (ddrphy_bankmodel0_activate) begin
+                       ddrphy_bankmodel0_active <= 1'd1;
+                       ddrphy_bankmodel0_row <= ddrphy_bankmodel0_activate_row;
+               end
+       end
+       if (ddrphy_bankmodel1_precharge) begin
+               ddrphy_bankmodel1_active <= 1'd0;
+       end else begin
+               if (ddrphy_bankmodel1_activate) begin
+                       ddrphy_bankmodel1_active <= 1'd1;
+                       ddrphy_bankmodel1_row <= ddrphy_bankmodel1_activate_row;
+               end
+       end
+       if (ddrphy_bankmodel2_precharge) begin
+               ddrphy_bankmodel2_active <= 1'd0;
+       end else begin
+               if (ddrphy_bankmodel2_activate) begin
+                       ddrphy_bankmodel2_active <= 1'd1;
+                       ddrphy_bankmodel2_row <= ddrphy_bankmodel2_activate_row;
+               end
+       end
+       if (ddrphy_bankmodel3_precharge) begin
+               ddrphy_bankmodel3_active <= 1'd0;
+       end else begin
+               if (ddrphy_bankmodel3_activate) begin
+                       ddrphy_bankmodel3_active <= 1'd1;
+                       ddrphy_bankmodel3_row <= ddrphy_bankmodel3_activate_row;
+               end
+       end
+       if (ddrphy_bankmodel4_precharge) begin
+               ddrphy_bankmodel4_active <= 1'd0;
+       end else begin
+               if (ddrphy_bankmodel4_activate) begin
+                       ddrphy_bankmodel4_active <= 1'd1;
+                       ddrphy_bankmodel4_row <= ddrphy_bankmodel4_activate_row;
+               end
+       end
+       if (ddrphy_bankmodel5_precharge) begin
+               ddrphy_bankmodel5_active <= 1'd0;
+       end else begin
+               if (ddrphy_bankmodel5_activate) begin
+                       ddrphy_bankmodel5_active <= 1'd1;
+                       ddrphy_bankmodel5_row <= ddrphy_bankmodel5_activate_row;
+               end
+       end
+       if (ddrphy_bankmodel6_precharge) begin
+               ddrphy_bankmodel6_active <= 1'd0;
+       end else begin
+               if (ddrphy_bankmodel6_activate) begin
+                       ddrphy_bankmodel6_active <= 1'd1;
+                       ddrphy_bankmodel6_row <= ddrphy_bankmodel6_activate_row;
+               end
+       end
+       if (ddrphy_bankmodel7_precharge) begin
+               ddrphy_bankmodel7_active <= 1'd0;
+       end else begin
+               if (ddrphy_bankmodel7_activate) begin
+                       ddrphy_bankmodel7_active <= 1'd1;
+                       ddrphy_bankmodel7_row <= ddrphy_bankmodel7_activate_row;
+               end
+       end
+       if (litedramcore_inti_p0_rddata_valid) begin
+               litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata;
+       end
+       if (litedramcore_inti_p1_rddata_valid) begin
+               litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata;
+       end
+       if (litedramcore_inti_p2_rddata_valid) begin
+               litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata;
+       end
+       if (litedramcore_inti_p3_rddata_valid) begin
+               litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata;
+       end
+       if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+               litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+       end else begin
+               litedramcore_timer_count1 <= 10'd781;
+       end
+       litedramcore_postponer_req_o <= 1'd0;
+       if (litedramcore_postponer_req_i) begin
+               litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+               if ((litedramcore_postponer_count == 1'd0)) begin
+                       litedramcore_postponer_count <= 1'd0;
+                       litedramcore_postponer_req_o <= 1'd1;
+               end
+       end
+       if (litedramcore_sequencer_start0) begin
+               litedramcore_sequencer_count <= 1'd0;
+       end else begin
+               if (litedramcore_sequencer_done1) begin
+                       if ((litedramcore_sequencer_count != 1'd0)) begin
+                               litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+                       end
+               end
+       end
+       litedramcore_cmd_payload_a <= 1'd0;
+       litedramcore_cmd_payload_ba <= 1'd0;
+       litedramcore_cmd_payload_cas <= 1'd0;
+       litedramcore_cmd_payload_ras <= 1'd0;
+       litedramcore_cmd_payload_we <= 1'd0;
+       litedramcore_sequencer_done1 <= 1'd0;
+       if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+               litedramcore_cmd_payload_a <= 11'd1024;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd1;
+               litedramcore_cmd_payload_we <= 1'd1;
+       end
+       if ((litedramcore_sequencer_counter == 2'd3)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd1;
+               litedramcore_cmd_payload_ras <= 1'd1;
+               litedramcore_cmd_payload_we <= 1'd0;
+       end
+       if ((litedramcore_sequencer_counter == 6'd35)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd0;
+               litedramcore_cmd_payload_we <= 1'd0;
+               litedramcore_sequencer_done1 <= 1'd1;
+       end
+       if ((litedramcore_sequencer_counter == 6'd35)) begin
+               litedramcore_sequencer_counter <= 1'd0;
+       end else begin
+               if ((litedramcore_sequencer_counter != 1'd0)) begin
+                       litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+               end else begin
+                       if (litedramcore_sequencer_start1) begin
+                               litedramcore_sequencer_counter <= 1'd1;
+                       end
+               end
+       end
+       if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+               litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+       end else begin
+               litedramcore_zqcs_timer_count1 <= 27'd99999999;
+       end
+       litedramcore_zqcs_executer_done <= 1'd0;
+       if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+               litedramcore_cmd_payload_a <= 11'd1024;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd1;
+               litedramcore_cmd_payload_we <= 1'd1;
+       end
+       if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd0;
+               litedramcore_cmd_payload_we <= 1'd1;
+       end
+       if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd0;
+               litedramcore_cmd_payload_we <= 1'd0;
+               litedramcore_zqcs_executer_done <= 1'd1;
+       end
+       if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+               litedramcore_zqcs_executer_counter <= 1'd0;
+       end else begin
+               if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+                       litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+               end else begin
+                       if (litedramcore_zqcs_executer_start) begin
+                               litedramcore_zqcs_executer_counter <= 1'd1;
+                       end
+               end
+       end
+       refresher_state <= refresher_next_state;
+       if (litedramcore_bankmachine0_row_close) begin
+               litedramcore_bankmachine0_row_opened <= 1'd0;
+       end else begin
+               if (litedramcore_bankmachine0_row_open) begin
+                       litedramcore_bankmachine0_row_opened <= 1'd1;
+                       litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+               end
+       end
+       if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+       end
+       if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+       end
+       if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+               end
+       end else begin
+               if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+               end
+       end
+       if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
+               litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
+               litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
+               litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+       end
+       if (litedramcore_bankmachine0_twtpcon_valid) begin
+               litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+                       litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine0_trccon_valid) begin
+               litedramcore_bankmachine0_trccon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine0_trccon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine0_trccon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine0_trccon_ready)) begin
+                       litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine0_trccon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine0_trascon_valid) begin
+               litedramcore_bankmachine0_trascon_count <= 3'd4;
+               if (1'd0) begin
+                       litedramcore_bankmachine0_trascon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine0_trascon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine0_trascon_ready)) begin
+                       litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine0_trascon_ready <= 1'd1;
+                       end
+               end
+       end
+       bankmachine0_state <= bankmachine0_next_state;
+       if (litedramcore_bankmachine1_row_close) begin
+               litedramcore_bankmachine1_row_opened <= 1'd0;
+       end else begin
+               if (litedramcore_bankmachine1_row_open) begin
+                       litedramcore_bankmachine1_row_opened <= 1'd1;
+                       litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+               end
+       end
+       if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+       end
+       if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+       end
+       if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+               end
+       end else begin
+               if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+               end
+       end
+       if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
+               litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
+               litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
+               litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+       end
+       if (litedramcore_bankmachine1_twtpcon_valid) begin
+               litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+                       litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine1_trccon_valid) begin
+               litedramcore_bankmachine1_trccon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine1_trccon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine1_trccon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine1_trccon_ready)) begin
+                       litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine1_trccon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine1_trascon_valid) begin
+               litedramcore_bankmachine1_trascon_count <= 3'd4;
+               if (1'd0) begin
+                       litedramcore_bankmachine1_trascon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine1_trascon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine1_trascon_ready)) begin
+                       litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine1_trascon_ready <= 1'd1;
+                       end
+               end
+       end
+       bankmachine1_state <= bankmachine1_next_state;
+       if (litedramcore_bankmachine2_row_close) begin
+               litedramcore_bankmachine2_row_opened <= 1'd0;
+       end else begin
+               if (litedramcore_bankmachine2_row_open) begin
+                       litedramcore_bankmachine2_row_opened <= 1'd1;
+                       litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+               end
+       end
+       if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+       end
+       if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+       end
+       if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+               end
+       end else begin
+               if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+               end
+       end
+       if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
+               litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
+               litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
+               litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+       end
+       if (litedramcore_bankmachine2_twtpcon_valid) begin
+               litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+                       litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine2_trccon_valid) begin
+               litedramcore_bankmachine2_trccon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine2_trccon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine2_trccon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine2_trccon_ready)) begin
+                       litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine2_trccon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine2_trascon_valid) begin
+               litedramcore_bankmachine2_trascon_count <= 3'd4;
+               if (1'd0) begin
+                       litedramcore_bankmachine2_trascon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine2_trascon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine2_trascon_ready)) begin
+                       litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine2_trascon_ready <= 1'd1;
+                       end
+               end
+       end
+       bankmachine2_state <= bankmachine2_next_state;
+       if (litedramcore_bankmachine3_row_close) begin
+               litedramcore_bankmachine3_row_opened <= 1'd0;
+       end else begin
+               if (litedramcore_bankmachine3_row_open) begin
+                       litedramcore_bankmachine3_row_opened <= 1'd1;
+                       litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+               end
+       end
+       if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+       end
+       if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+       end
+       if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+               end
+       end else begin
+               if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+               end
+       end
+       if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
+               litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
+               litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
+               litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+       end
+       if (litedramcore_bankmachine3_twtpcon_valid) begin
+               litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+                       litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine3_trccon_valid) begin
+               litedramcore_bankmachine3_trccon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine3_trccon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine3_trccon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine3_trccon_ready)) begin
+                       litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine3_trccon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine3_trascon_valid) begin
+               litedramcore_bankmachine3_trascon_count <= 3'd4;
+               if (1'd0) begin
+                       litedramcore_bankmachine3_trascon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine3_trascon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine3_trascon_ready)) begin
+                       litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine3_trascon_ready <= 1'd1;
+                       end
+               end
+       end
+       bankmachine3_state <= bankmachine3_next_state;
+       if (litedramcore_bankmachine4_row_close) begin
+               litedramcore_bankmachine4_row_opened <= 1'd0;
+       end else begin
+               if (litedramcore_bankmachine4_row_open) begin
+                       litedramcore_bankmachine4_row_opened <= 1'd1;
+                       litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+               end
+       end
+       if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+       end
+       if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+       end
+       if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+               end
+       end else begin
+               if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+               end
+       end
+       if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
+               litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
+               litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
+               litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+       end
+       if (litedramcore_bankmachine4_twtpcon_valid) begin
+               litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+                       litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine4_trccon_valid) begin
+               litedramcore_bankmachine4_trccon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine4_trccon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine4_trccon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine4_trccon_ready)) begin
+                       litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine4_trccon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine4_trascon_valid) begin
+               litedramcore_bankmachine4_trascon_count <= 3'd4;
+               if (1'd0) begin
+                       litedramcore_bankmachine4_trascon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine4_trascon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine4_trascon_ready)) begin
+                       litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine4_trascon_ready <= 1'd1;
+                       end
+               end
+       end
+       bankmachine4_state <= bankmachine4_next_state;
+       if (litedramcore_bankmachine5_row_close) begin
+               litedramcore_bankmachine5_row_opened <= 1'd0;
+       end else begin
+               if (litedramcore_bankmachine5_row_open) begin
+                       litedramcore_bankmachine5_row_opened <= 1'd1;
+                       litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+               end
+       end
+       if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+       end
+       if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+       end
+       if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+               end
+       end else begin
+               if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+               end
+       end
+       if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
+               litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
+               litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
+               litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+       end
+       if (litedramcore_bankmachine5_twtpcon_valid) begin
+               litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+                       litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine5_trccon_valid) begin
+               litedramcore_bankmachine5_trccon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine5_trccon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine5_trccon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine5_trccon_ready)) begin
+                       litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine5_trccon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine5_trascon_valid) begin
+               litedramcore_bankmachine5_trascon_count <= 3'd4;
+               if (1'd0) begin
+                       litedramcore_bankmachine5_trascon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine5_trascon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine5_trascon_ready)) begin
+                       litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine5_trascon_ready <= 1'd1;
+                       end
+               end
+       end
+       bankmachine5_state <= bankmachine5_next_state;
+       if (litedramcore_bankmachine6_row_close) begin
+               litedramcore_bankmachine6_row_opened <= 1'd0;
+       end else begin
+               if (litedramcore_bankmachine6_row_open) begin
+                       litedramcore_bankmachine6_row_opened <= 1'd1;
+                       litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+               end
+       end
+       if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+       end
+       if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+       end
+       if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+               end
+       end else begin
+               if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+               end
+       end
+       if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
+               litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
+               litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
+               litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+       end
+       if (litedramcore_bankmachine6_twtpcon_valid) begin
+               litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+                       litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine6_trccon_valid) begin
+               litedramcore_bankmachine6_trccon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine6_trccon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine6_trccon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine6_trccon_ready)) begin
+                       litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine6_trccon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine6_trascon_valid) begin
+               litedramcore_bankmachine6_trascon_count <= 3'd4;
+               if (1'd0) begin
+                       litedramcore_bankmachine6_trascon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine6_trascon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine6_trascon_ready)) begin
+                       litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine6_trascon_ready <= 1'd1;
+                       end
+               end
+       end
+       bankmachine6_state <= bankmachine6_next_state;
+       if (litedramcore_bankmachine7_row_close) begin
+               litedramcore_bankmachine7_row_opened <= 1'd0;
+       end else begin
+               if (litedramcore_bankmachine7_row_open) begin
+                       litedramcore_bankmachine7_row_opened <= 1'd1;
+                       litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+               end
+       end
+       if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+       end
+       if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+       end
+       if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+               end
+       end else begin
+               if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+               end
+       end
+       if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
+               litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
+               litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
+               litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+       end
+       if (litedramcore_bankmachine7_twtpcon_valid) begin
+               litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+                       litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine7_trccon_valid) begin
+               litedramcore_bankmachine7_trccon_count <= 3'd5;
+               if (1'd0) begin
+                       litedramcore_bankmachine7_trccon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine7_trccon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine7_trccon_ready)) begin
+                       litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine7_trccon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_bankmachine7_trascon_valid) begin
+               litedramcore_bankmachine7_trascon_count <= 3'd4;
+               if (1'd0) begin
+                       litedramcore_bankmachine7_trascon_ready <= 1'd1;
+               end else begin
+                       litedramcore_bankmachine7_trascon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_bankmachine7_trascon_ready)) begin
+                       litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine7_trascon_ready <= 1'd1;
+                       end
+               end
+       end
+       bankmachine7_state <= bankmachine7_next_state;
+       if ((~litedramcore_en0)) begin
+               litedramcore_time0 <= 5'd31;
+       end else begin
+               if ((~litedramcore_max_time0)) begin
+                       litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+               end
+       end
+       if ((~litedramcore_en1)) begin
+               litedramcore_time1 <= 4'd15;
+       end else begin
+               if ((~litedramcore_max_time1)) begin
+                       litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+               end
+       end
+       if (litedramcore_choose_cmd_ce) begin
+               case (litedramcore_choose_cmd_grant)
+                       1'd0: begin
+                               if (litedramcore_choose_cmd_request[1]) begin
+                                       litedramcore_choose_cmd_grant <= 1'd1;
+                               end else begin
+                                       if (litedramcore_choose_cmd_request[2]) begin
+                                               litedramcore_choose_cmd_grant <= 2'd2;
+                                       end else begin
+                                               if (litedramcore_choose_cmd_request[3]) begin
+                                                       litedramcore_choose_cmd_grant <= 2'd3;
+                                               end else begin
+                                                       if (litedramcore_choose_cmd_request[4]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd4;
+                                                       end else begin
+                                                               if (litedramcore_choose_cmd_request[5]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd5;
+                                                               end else begin
+                                                                       if (litedramcore_choose_cmd_request[6]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd6;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_cmd_request[7]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd7;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       1'd1: begin
+                               if (litedramcore_choose_cmd_request[2]) begin
+                                       litedramcore_choose_cmd_grant <= 2'd2;
+                               end else begin
+                                       if (litedramcore_choose_cmd_request[3]) begin
+                                               litedramcore_choose_cmd_grant <= 2'd3;
+                                       end else begin
+                                               if (litedramcore_choose_cmd_request[4]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd4;
+                                               end else begin
+                                                       if (litedramcore_choose_cmd_request[5]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd5;
+                                                       end else begin
+                                                               if (litedramcore_choose_cmd_request[6]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd6;
+                                                               end else begin
+                                                                       if (litedramcore_choose_cmd_request[7]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd7;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_cmd_request[0]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 1'd0;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       2'd2: begin
+                               if (litedramcore_choose_cmd_request[3]) begin
+                                       litedramcore_choose_cmd_grant <= 2'd3;
+                               end else begin
+                                       if (litedramcore_choose_cmd_request[4]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd4;
+                                       end else begin
+                                               if (litedramcore_choose_cmd_request[5]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd5;
+                                               end else begin
+                                                       if (litedramcore_choose_cmd_request[6]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd6;
+                                                       end else begin
+                                                               if (litedramcore_choose_cmd_request[7]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd7;
+                                                               end else begin
+                                                                       if (litedramcore_choose_cmd_request[0]) begin
+                                                                               litedramcore_choose_cmd_grant <= 1'd0;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_cmd_request[1]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 1'd1;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       2'd3: begin
+                               if (litedramcore_choose_cmd_request[4]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd4;
+                               end else begin
+                                       if (litedramcore_choose_cmd_request[5]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd5;
+                                       end else begin
+                                               if (litedramcore_choose_cmd_request[6]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd6;
+                                               end else begin
+                                                       if (litedramcore_choose_cmd_request[7]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd7;
+                                                       end else begin
+                                                               if (litedramcore_choose_cmd_request[0]) begin
+                                                                       litedramcore_choose_cmd_grant <= 1'd0;
+                                                               end else begin
+                                                                       if (litedramcore_choose_cmd_request[1]) begin
+                                                                               litedramcore_choose_cmd_grant <= 1'd1;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_cmd_request[2]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 2'd2;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       3'd4: begin
+                               if (litedramcore_choose_cmd_request[5]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd5;
+                               end else begin
+                                       if (litedramcore_choose_cmd_request[6]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd6;
+                                       end else begin
+                                               if (litedramcore_choose_cmd_request[7]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd7;
+                                               end else begin
+                                                       if (litedramcore_choose_cmd_request[0]) begin
+                                                               litedramcore_choose_cmd_grant <= 1'd0;
+                                                       end else begin
+                                                               if (litedramcore_choose_cmd_request[1]) begin
+                                                                       litedramcore_choose_cmd_grant <= 1'd1;
+                                                               end else begin
+                                                                       if (litedramcore_choose_cmd_request[2]) begin
+                                                                               litedramcore_choose_cmd_grant <= 2'd2;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_cmd_request[3]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 2'd3;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       3'd5: begin
+                               if (litedramcore_choose_cmd_request[6]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd6;
+                               end else begin
+                                       if (litedramcore_choose_cmd_request[7]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd7;
+                                       end else begin
+                                               if (litedramcore_choose_cmd_request[0]) begin
+                                                       litedramcore_choose_cmd_grant <= 1'd0;
+                                               end else begin
+                                                       if (litedramcore_choose_cmd_request[1]) begin
+                                                               litedramcore_choose_cmd_grant <= 1'd1;
+                                                       end else begin
+                                                               if (litedramcore_choose_cmd_request[2]) begin
+                                                                       litedramcore_choose_cmd_grant <= 2'd2;
+                                                               end else begin
+                                                                       if (litedramcore_choose_cmd_request[3]) begin
+                                                                               litedramcore_choose_cmd_grant <= 2'd3;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_cmd_request[4]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd4;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       3'd6: begin
+                               if (litedramcore_choose_cmd_request[7]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd7;
+                               end else begin
+                                       if (litedramcore_choose_cmd_request[0]) begin
+                                               litedramcore_choose_cmd_grant <= 1'd0;
+                                       end else begin
+                                               if (litedramcore_choose_cmd_request[1]) begin
+                                                       litedramcore_choose_cmd_grant <= 1'd1;
+                                               end else begin
+                                                       if (litedramcore_choose_cmd_request[2]) begin
+                                                               litedramcore_choose_cmd_grant <= 2'd2;
+                                                       end else begin
+                                                               if (litedramcore_choose_cmd_request[3]) begin
+                                                                       litedramcore_choose_cmd_grant <= 2'd3;
+                                                               end else begin
+                                                                       if (litedramcore_choose_cmd_request[4]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd4;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_cmd_request[5]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd5;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       3'd7: begin
+                               if (litedramcore_choose_cmd_request[0]) begin
+                                       litedramcore_choose_cmd_grant <= 1'd0;
+                               end else begin
+                                       if (litedramcore_choose_cmd_request[1]) begin
+                                               litedramcore_choose_cmd_grant <= 1'd1;
+                                       end else begin
+                                               if (litedramcore_choose_cmd_request[2]) begin
+                                                       litedramcore_choose_cmd_grant <= 2'd2;
+                                               end else begin
+                                                       if (litedramcore_choose_cmd_request[3]) begin
+                                                               litedramcore_choose_cmd_grant <= 2'd3;
+                                                       end else begin
+                                                               if (litedramcore_choose_cmd_request[4]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd4;
+                                                               end else begin
+                                                                       if (litedramcore_choose_cmd_request[5]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd5;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_cmd_request[6]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd6;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+               endcase
+       end
+       if (litedramcore_choose_req_ce) begin
+               case (litedramcore_choose_req_grant)
+                       1'd0: begin
+                               if (litedramcore_choose_req_request[1]) begin
+                                       litedramcore_choose_req_grant <= 1'd1;
+                               end else begin
+                                       if (litedramcore_choose_req_request[2]) begin
+                                               litedramcore_choose_req_grant <= 2'd2;
+                                       end else begin
+                                               if (litedramcore_choose_req_request[3]) begin
+                                                       litedramcore_choose_req_grant <= 2'd3;
+                                               end else begin
+                                                       if (litedramcore_choose_req_request[4]) begin
+                                                               litedramcore_choose_req_grant <= 3'd4;
+                                                       end else begin
+                                                               if (litedramcore_choose_req_request[5]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd5;
+                                                               end else begin
+                                                                       if (litedramcore_choose_req_request[6]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd6;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_req_request[7]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd7;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       1'd1: begin
+                               if (litedramcore_choose_req_request[2]) begin
+                                       litedramcore_choose_req_grant <= 2'd2;
+                               end else begin
+                                       if (litedramcore_choose_req_request[3]) begin
+                                               litedramcore_choose_req_grant <= 2'd3;
+                                       end else begin
+                                               if (litedramcore_choose_req_request[4]) begin
+                                                       litedramcore_choose_req_grant <= 3'd4;
+                                               end else begin
+                                                       if (litedramcore_choose_req_request[5]) begin
+                                                               litedramcore_choose_req_grant <= 3'd5;
+                                                       end else begin
+                                                               if (litedramcore_choose_req_request[6]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd6;
+                                                               end else begin
+                                                                       if (litedramcore_choose_req_request[7]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd7;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_req_request[0]) begin
+                                                                                       litedramcore_choose_req_grant <= 1'd0;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       2'd2: begin
+                               if (litedramcore_choose_req_request[3]) begin
+                                       litedramcore_choose_req_grant <= 2'd3;
+                               end else begin
+                                       if (litedramcore_choose_req_request[4]) begin
+                                               litedramcore_choose_req_grant <= 3'd4;
+                                       end else begin
+                                               if (litedramcore_choose_req_request[5]) begin
+                                                       litedramcore_choose_req_grant <= 3'd5;
+                                               end else begin
+                                                       if (litedramcore_choose_req_request[6]) begin
+                                                               litedramcore_choose_req_grant <= 3'd6;
+                                                       end else begin
+                                                               if (litedramcore_choose_req_request[7]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd7;
+                                                               end else begin
+                                                                       if (litedramcore_choose_req_request[0]) begin
+                                                                               litedramcore_choose_req_grant <= 1'd0;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_req_request[1]) begin
+                                                                                       litedramcore_choose_req_grant <= 1'd1;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       2'd3: begin
+                               if (litedramcore_choose_req_request[4]) begin
+                                       litedramcore_choose_req_grant <= 3'd4;
+                               end else begin
+                                       if (litedramcore_choose_req_request[5]) begin
+                                               litedramcore_choose_req_grant <= 3'd5;
+                                       end else begin
+                                               if (litedramcore_choose_req_request[6]) begin
+                                                       litedramcore_choose_req_grant <= 3'd6;
+                                               end else begin
+                                                       if (litedramcore_choose_req_request[7]) begin
+                                                               litedramcore_choose_req_grant <= 3'd7;
+                                                       end else begin
+                                                               if (litedramcore_choose_req_request[0]) begin
+                                                                       litedramcore_choose_req_grant <= 1'd0;
+                                                               end else begin
+                                                                       if (litedramcore_choose_req_request[1]) begin
+                                                                               litedramcore_choose_req_grant <= 1'd1;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_req_request[2]) begin
+                                                                                       litedramcore_choose_req_grant <= 2'd2;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       3'd4: begin
+                               if (litedramcore_choose_req_request[5]) begin
+                                       litedramcore_choose_req_grant <= 3'd5;
+                               end else begin
+                                       if (litedramcore_choose_req_request[6]) begin
+                                               litedramcore_choose_req_grant <= 3'd6;
+                                       end else begin
+                                               if (litedramcore_choose_req_request[7]) begin
+                                                       litedramcore_choose_req_grant <= 3'd7;
+                                               end else begin
+                                                       if (litedramcore_choose_req_request[0]) begin
+                                                               litedramcore_choose_req_grant <= 1'd0;
+                                                       end else begin
+                                                               if (litedramcore_choose_req_request[1]) begin
+                                                                       litedramcore_choose_req_grant <= 1'd1;
+                                                               end else begin
+                                                                       if (litedramcore_choose_req_request[2]) begin
+                                                                               litedramcore_choose_req_grant <= 2'd2;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_req_request[3]) begin
+                                                                                       litedramcore_choose_req_grant <= 2'd3;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       3'd5: begin
+                               if (litedramcore_choose_req_request[6]) begin
+                                       litedramcore_choose_req_grant <= 3'd6;
+                               end else begin
+                                       if (litedramcore_choose_req_request[7]) begin
+                                               litedramcore_choose_req_grant <= 3'd7;
+                                       end else begin
+                                               if (litedramcore_choose_req_request[0]) begin
+                                                       litedramcore_choose_req_grant <= 1'd0;
+                                               end else begin
+                                                       if (litedramcore_choose_req_request[1]) begin
+                                                               litedramcore_choose_req_grant <= 1'd1;
+                                                       end else begin
+                                                               if (litedramcore_choose_req_request[2]) begin
+                                                                       litedramcore_choose_req_grant <= 2'd2;
+                                                               end else begin
+                                                                       if (litedramcore_choose_req_request[3]) begin
+                                                                               litedramcore_choose_req_grant <= 2'd3;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_req_request[4]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd4;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       3'd6: begin
+                               if (litedramcore_choose_req_request[7]) begin
+                                       litedramcore_choose_req_grant <= 3'd7;
+                               end else begin
+                                       if (litedramcore_choose_req_request[0]) begin
+                                               litedramcore_choose_req_grant <= 1'd0;
+                                       end else begin
+                                               if (litedramcore_choose_req_request[1]) begin
+                                                       litedramcore_choose_req_grant <= 1'd1;
+                                               end else begin
+                                                       if (litedramcore_choose_req_request[2]) begin
+                                                               litedramcore_choose_req_grant <= 2'd2;
+                                                       end else begin
+                                                               if (litedramcore_choose_req_request[3]) begin
+                                                                       litedramcore_choose_req_grant <= 2'd3;
+                                                               end else begin
+                                                                       if (litedramcore_choose_req_request[4]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd4;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_req_request[5]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd5;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+                       3'd7: begin
+                               if (litedramcore_choose_req_request[0]) begin
+                                       litedramcore_choose_req_grant <= 1'd0;
+                               end else begin
+                                       if (litedramcore_choose_req_request[1]) begin
+                                               litedramcore_choose_req_grant <= 1'd1;
+                                       end else begin
+                                               if (litedramcore_choose_req_request[2]) begin
+                                                       litedramcore_choose_req_grant <= 2'd2;
+                                               end else begin
+                                                       if (litedramcore_choose_req_request[3]) begin
+                                                               litedramcore_choose_req_grant <= 2'd3;
+                                                       end else begin
+                                                               if (litedramcore_choose_req_request[4]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd4;
+                                                               end else begin
+                                                                       if (litedramcore_choose_req_request[5]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd5;
+                                                                       end else begin
+                                                                               if (litedramcore_choose_req_request[6]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd6;
+                                                                               end
+                                                                       end
+                                                               end
+                                                       end
+                                               end
+                                       end
+                               end
+                       end
+               endcase
+       end
+       litedramcore_dfi_p0_cs_n <= 1'd0;
+       litedramcore_dfi_p0_bank <= sync_rhs_array_muxed0;
+       litedramcore_dfi_p0_address <= sync_rhs_array_muxed1;
+       litedramcore_dfi_p0_cas_n <= (~sync_rhs_array_muxed2);
+       litedramcore_dfi_p0_ras_n <= (~sync_rhs_array_muxed3);
+       litedramcore_dfi_p0_we_n <= (~sync_rhs_array_muxed4);
+       litedramcore_dfi_p0_rddata_en <= sync_rhs_array_muxed5;
+       litedramcore_dfi_p0_wrdata_en <= sync_rhs_array_muxed6;
+       litedramcore_dfi_p1_cs_n <= 1'd0;
+       litedramcore_dfi_p1_bank <= sync_rhs_array_muxed7;
+       litedramcore_dfi_p1_address <= sync_rhs_array_muxed8;
+       litedramcore_dfi_p1_cas_n <= (~sync_rhs_array_muxed9);
+       litedramcore_dfi_p1_ras_n <= (~sync_rhs_array_muxed10);
+       litedramcore_dfi_p1_we_n <= (~sync_rhs_array_muxed11);
+       litedramcore_dfi_p1_rddata_en <= sync_rhs_array_muxed12;
+       litedramcore_dfi_p1_wrdata_en <= sync_rhs_array_muxed13;
+       litedramcore_dfi_p2_cs_n <= 1'd0;
+       litedramcore_dfi_p2_bank <= sync_rhs_array_muxed14;
+       litedramcore_dfi_p2_address <= sync_rhs_array_muxed15;
+       litedramcore_dfi_p2_cas_n <= (~sync_rhs_array_muxed16);
+       litedramcore_dfi_p2_ras_n <= (~sync_rhs_array_muxed17);
+       litedramcore_dfi_p2_we_n <= (~sync_rhs_array_muxed18);
+       litedramcore_dfi_p2_rddata_en <= sync_rhs_array_muxed19;
+       litedramcore_dfi_p2_wrdata_en <= sync_rhs_array_muxed20;
+       litedramcore_dfi_p3_cs_n <= 1'd0;
+       litedramcore_dfi_p3_bank <= sync_rhs_array_muxed21;
+       litedramcore_dfi_p3_address <= sync_rhs_array_muxed22;
+       litedramcore_dfi_p3_cas_n <= (~sync_rhs_array_muxed23);
+       litedramcore_dfi_p3_ras_n <= (~sync_rhs_array_muxed24);
+       litedramcore_dfi_p3_we_n <= (~sync_rhs_array_muxed25);
+       litedramcore_dfi_p3_rddata_en <= sync_rhs_array_muxed26;
+       litedramcore_dfi_p3_wrdata_en <= sync_rhs_array_muxed27;
+       if (litedramcore_trrdcon_valid) begin
+               litedramcore_trrdcon_count <= 1'd1;
+               if (1'd0) begin
+                       litedramcore_trrdcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_trrdcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_trrdcon_ready)) begin
+                       litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+                       if ((litedramcore_trrdcon_count == 1'd1)) begin
+                               litedramcore_trrdcon_ready <= 1'd1;
+                       end
+               end
+       end
+       litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+       if ((litedramcore_tfawcon_count < 3'd4)) begin
+               if ((litedramcore_tfawcon_count == 2'd3)) begin
+                       litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+               end else begin
+                       litedramcore_tfawcon_ready <= 1'd1;
+               end
+       end
+       if (litedramcore_tccdcon_valid) begin
+               litedramcore_tccdcon_count <= 1'd0;
+               if (1'd1) begin
+                       litedramcore_tccdcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_tccdcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_tccdcon_ready)) begin
+                       litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+                       if ((litedramcore_tccdcon_count == 1'd1)) begin
+                               litedramcore_tccdcon_ready <= 1'd1;
+                       end
+               end
+       end
+       if (litedramcore_twtrcon_valid) begin
+               litedramcore_twtrcon_count <= 3'd4;
+               if (1'd0) begin
+                       litedramcore_twtrcon_ready <= 1'd1;
+               end else begin
+                       litedramcore_twtrcon_ready <= 1'd0;
+               end
+       end else begin
+               if ((~litedramcore_twtrcon_ready)) begin
+                       litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+                       if ((litedramcore_twtrcon_count == 1'd1)) begin
+                               litedramcore_twtrcon_ready <= 1'd1;
+                       end
+               end
+       end
+       multiplexer_state <= multiplexer_next_state;
+       new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+       new_master_wdata_ready1 <= new_master_wdata_ready0;
+       new_master_wdata_ready2 <= new_master_wdata_ready1;
+       new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+       new_master_rdata_valid1 <= new_master_rdata_valid0;
+       new_master_rdata_valid2 <= new_master_rdata_valid1;
+       new_master_rdata_valid3 <= new_master_rdata_valid2;
+       new_master_rdata_valid4 <= new_master_rdata_valid3;
+       new_master_rdata_valid5 <= new_master_rdata_valid4;
+       new_master_rdata_valid6 <= new_master_rdata_valid5;
+       new_master_rdata_valid7 <= new_master_rdata_valid6;
+       new_master_rdata_valid8 <= new_master_rdata_valid7;
+       new_master_rdata_valid9 <= new_master_rdata_valid8;
+       interface0_bank_bus_dat_r <= 1'd0;
+       if (csrbank0_sel) begin
+               case (interface0_bank_bus_adr[1])
+                       1'd0: begin
+                               interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+                       end
+                       1'd1: begin
+                               interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+                       end
+               endcase
+       end
+       if (csrbank0_init_done0_re) begin
+               init_done_storage <= csrbank0_init_done0_r;
+       end
+       init_done_re <= csrbank0_init_done0_re;
+       if (csrbank0_init_error0_re) begin
+               init_error_storage <= csrbank0_init_error0_r;
+       end
+       init_error_re <= csrbank0_init_error0_re;
+       interface1_bank_bus_dat_r <= 1'd0;
+       if (csrbank1_sel) begin
+               case (interface1_bank_bus_adr[5:1])
+                       1'd0: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
+                       end
+                       1'd1: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w;
+                       end
+                       2'd2: begin
+                               interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+                       end
+                       2'd3: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
+                       end
+                       3'd4: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
+                       end
+                       3'd5: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
+                       end
+                       3'd6: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
+                       end
+                       3'd7: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
+                       end
+                       4'd8: begin
+                               interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+                       end
+                       4'd9: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
+                       end
+                       4'd10: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
+                       end
+                       4'd11: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
+                       end
+                       4'd12: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
+                       end
+                       4'd13: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
+                       end
+                       4'd14: begin
+                               interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+                       end
+                       4'd15: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
+                       end
+                       5'd16: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
+                       end
+                       5'd17: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
+                       end
+                       5'd18: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
+                       end
+                       5'd19: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
+                       end
+                       5'd20: begin
+                               interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+                       end
+                       5'd21: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
+                       end
+                       5'd22: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
+                       end
+                       5'd23: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
+                       end
+                       5'd24: begin
+                               interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
+                       end
+               endcase
+       end
+       if (csrbank1_dfii_control0_re) begin
+               litedramcore_storage[3:0] <= csrbank1_dfii_control0_r;
+       end
+       litedramcore_re <= csrbank1_dfii_control0_re;
+       if (csrbank1_dfii_pi0_command0_re) begin
+               litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
+       end
+       litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
+       if (csrbank1_dfii_pi0_address0_re) begin
+               litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
+       end
+       litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
+       if (csrbank1_dfii_pi0_baddress0_re) begin
+               litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
+       end
+       litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
+       if (csrbank1_dfii_pi0_wrdata0_re) begin
+               litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
+       end
+       litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
+       if (csrbank1_dfii_pi1_command0_re) begin
+               litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
+       end
+       litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
+       if (csrbank1_dfii_pi1_address0_re) begin
+               litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
+       end
+       litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
+       if (csrbank1_dfii_pi1_baddress0_re) begin
+               litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
+       end
+       litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
+       if (csrbank1_dfii_pi1_wrdata0_re) begin
+               litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
+       end
+       litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
+       if (csrbank1_dfii_pi2_command0_re) begin
+               litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
+       end
+       litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
+       if (csrbank1_dfii_pi2_address0_re) begin
+               litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
+       end
+       litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
+       if (csrbank1_dfii_pi2_baddress0_re) begin
+               litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
+       end
+       litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
+       if (csrbank1_dfii_pi2_wrdata0_re) begin
+               litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
+       end
+       litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
+       if (csrbank1_dfii_pi3_command0_re) begin
+               litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
+       end
+       litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
+       if (csrbank1_dfii_pi3_address0_re) begin
+               litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
+       end
+       litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
+       if (csrbank1_dfii_pi3_baddress0_re) begin
+               litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
+       end
+       litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
+       if (csrbank1_dfii_pi3_wrdata0_re) begin
+               litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
+       end
+       litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
+       if (sys_rst) begin
+               ddrphy_dfitimingschecker_cnt <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker0 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker1 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker2 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker3 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker4 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker5 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker6 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker7 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker8 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker9 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker10 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker11 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker12 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker13 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker14 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker15 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker16 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker17 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker18 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker19 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker20 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker21 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker22 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker23 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker24 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker25 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker26 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker27 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker28 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker29 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker30 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker31 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker32 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker33 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker34 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker35 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker36 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker37 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker38 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker39 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker40 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker41 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker42 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker43 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker44 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker45 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker46 <= 64'd0;
+               ddrphy_dfitimingschecker_dfitimingschecker47 <= 64'd0;
+               ddrphy_dfitimingschecker_last_cmd0 <= 4'd0;
+               ddrphy_dfitimingschecker_last_cmd1 <= 4'd0;
+               ddrphy_dfitimingschecker_last_cmd2 <= 4'd0;
+               ddrphy_dfitimingschecker_last_cmd3 <= 4'd0;
+               ddrphy_dfitimingschecker_last_cmd4 <= 4'd0;
+               ddrphy_dfitimingschecker_last_cmd5 <= 4'd0;
+               ddrphy_dfitimingschecker_last_cmd6 <= 4'd0;
+               ddrphy_dfitimingschecker_last_cmd7 <= 4'd0;
+               ddrphy_dfitimingschecker0 <= 64'd0;
+               ddrphy_dfitimingschecker1 <= 64'd0;
+               ddrphy_dfitimingschecker2 <= 64'd0;
+               ddrphy_dfitimingschecker3 <= 64'd0;
+               ddrphy_dfitimingschecker_act_curr <= 2'd0;
+               ddrphy_dfitimingschecker_ref_ps <= 64'd0;
+               ddrphy_dfitimingschecker_ref_ps_mod <= 64'd0;
+               ddrphy_dfitimingschecker_ref_ps_diff <= 64'd0;
+               ddrphy_dfitimingschecker_ref_done <= 1'd0;
+               ddrphy_bankmodel0_active <= 1'd0;
+               ddrphy_bankmodel0_row <= 14'd0;
+               ddrphy_bankmodel1_active <= 1'd0;
+               ddrphy_bankmodel1_row <= 14'd0;
+               ddrphy_bankmodel2_active <= 1'd0;
+               ddrphy_bankmodel2_row <= 14'd0;
+               ddrphy_bankmodel3_active <= 1'd0;
+               ddrphy_bankmodel3_row <= 14'd0;
+               ddrphy_bankmodel4_active <= 1'd0;
+               ddrphy_bankmodel4_row <= 14'd0;
+               ddrphy_bankmodel5_active <= 1'd0;
+               ddrphy_bankmodel5_row <= 14'd0;
+               ddrphy_bankmodel6_active <= 1'd0;
+               ddrphy_bankmodel6_row <= 14'd0;
+               ddrphy_bankmodel7_active <= 1'd0;
+               ddrphy_bankmodel7_row <= 14'd0;
+               ddrphy_new_bank_write0 <= 1'd0;
+               ddrphy_new_bank_write_col0 <= 10'd0;
+               ddrphy_new_bank_write1 <= 1'd0;
+               ddrphy_new_bank_write_col1 <= 10'd0;
+               ddrphy_new_bank_write2 <= 1'd0;
+               ddrphy_new_bank_write_col2 <= 10'd0;
+               ddrphy_new_bank_write3 <= 1'd0;
+               ddrphy_new_bank_write_col3 <= 10'd0;
+               ddrphy_new_bank_write4 <= 1'd0;
+               ddrphy_new_bank_write_col4 <= 10'd0;
+               ddrphy_new_bank_write5 <= 1'd0;
+               ddrphy_new_bank_write_col5 <= 10'd0;
+               ddrphy_new_bank_write6 <= 1'd0;
+               ddrphy_new_bank_write_col6 <= 10'd0;
+               ddrphy_new_bank_write7 <= 1'd0;
+               ddrphy_new_bank_write_col7 <= 10'd0;
+               ddrphy_new_bank_write8 <= 1'd0;
+               ddrphy_new_bank_write_col8 <= 10'd0;
+               ddrphy_new_bank_write9 <= 1'd0;
+               ddrphy_new_bank_write_col9 <= 10'd0;
+               ddrphy_new_bank_write10 <= 1'd0;
+               ddrphy_new_bank_write_col10 <= 10'd0;
+               ddrphy_new_bank_write11 <= 1'd0;
+               ddrphy_new_bank_write_col11 <= 10'd0;
+               ddrphy_new_bank_write12 <= 1'd0;
+               ddrphy_new_bank_write_col12 <= 10'd0;
+               ddrphy_new_bank_write13 <= 1'd0;
+               ddrphy_new_bank_write_col13 <= 10'd0;
+               ddrphy_new_bank_write14 <= 1'd0;
+               ddrphy_new_bank_write_col14 <= 10'd0;
+               ddrphy_new_bank_write15 <= 1'd0;
+               ddrphy_new_bank_write_col15 <= 10'd0;
+               ddrphy_new_banks_read0 <= 1'd0;
+               ddrphy_new_banks_read_data0 <= 128'd0;
+               ddrphy_new_banks_read1 <= 1'd0;
+               ddrphy_new_banks_read_data1 <= 128'd0;
+               ddrphy_new_banks_read2 <= 1'd0;
+               ddrphy_new_banks_read_data2 <= 128'd0;
+               ddrphy_new_banks_read3 <= 1'd0;
+               ddrphy_new_banks_read_data3 <= 128'd0;
+               ddrphy_new_banks_read4 <= 1'd0;
+               ddrphy_new_banks_read_data4 <= 128'd0;
+               ddrphy_new_banks_read5 <= 1'd0;
+               ddrphy_new_banks_read_data5 <= 128'd0;
+               ddrphy_new_banks_read6 <= 1'd0;
+               ddrphy_new_banks_read_data6 <= 128'd0;
+               ddrphy_new_banks_read7 <= 1'd0;
+               ddrphy_new_banks_read_data7 <= 128'd0;
+               ddrphy_new_banks_read8 <= 1'd0;
+               ddrphy_new_banks_read_data8 <= 128'd0;
+               litedramcore_storage <= 4'd0;
+               litedramcore_re <= 1'd0;
+               litedramcore_phaseinjector0_command_storage <= 6'd0;
+               litedramcore_phaseinjector0_command_re <= 1'd0;
+               litedramcore_phaseinjector0_address_re <= 1'd0;
+               litedramcore_phaseinjector0_baddress_re <= 1'd0;
+               litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector0_status <= 32'd0;
+               litedramcore_phaseinjector1_command_storage <= 6'd0;
+               litedramcore_phaseinjector1_command_re <= 1'd0;
+               litedramcore_phaseinjector1_address_re <= 1'd0;
+               litedramcore_phaseinjector1_baddress_re <= 1'd0;
+               litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector1_status <= 32'd0;
+               litedramcore_phaseinjector2_command_storage <= 6'd0;
+               litedramcore_phaseinjector2_command_re <= 1'd0;
+               litedramcore_phaseinjector2_address_re <= 1'd0;
+               litedramcore_phaseinjector2_baddress_re <= 1'd0;
+               litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector2_status <= 32'd0;
+               litedramcore_phaseinjector3_command_storage <= 6'd0;
+               litedramcore_phaseinjector3_command_re <= 1'd0;
+               litedramcore_phaseinjector3_address_re <= 1'd0;
+               litedramcore_phaseinjector3_baddress_re <= 1'd0;
+               litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector3_status <= 32'd0;
+               litedramcore_dfi_p0_address <= 14'd0;
+               litedramcore_dfi_p0_bank <= 3'd0;
+               litedramcore_dfi_p0_cas_n <= 1'd1;
+               litedramcore_dfi_p0_cs_n <= 1'd1;
+               litedramcore_dfi_p0_ras_n <= 1'd1;
+               litedramcore_dfi_p0_we_n <= 1'd1;
+               litedramcore_dfi_p0_wrdata_en <= 1'd0;
+               litedramcore_dfi_p0_rddata_en <= 1'd0;
+               litedramcore_dfi_p1_address <= 14'd0;
+               litedramcore_dfi_p1_bank <= 3'd0;
+               litedramcore_dfi_p1_cas_n <= 1'd1;
+               litedramcore_dfi_p1_cs_n <= 1'd1;
+               litedramcore_dfi_p1_ras_n <= 1'd1;
+               litedramcore_dfi_p1_we_n <= 1'd1;
+               litedramcore_dfi_p1_wrdata_en <= 1'd0;
+               litedramcore_dfi_p1_rddata_en <= 1'd0;
+               litedramcore_dfi_p2_address <= 14'd0;
+               litedramcore_dfi_p2_bank <= 3'd0;
+               litedramcore_dfi_p2_cas_n <= 1'd1;
+               litedramcore_dfi_p2_cs_n <= 1'd1;
+               litedramcore_dfi_p2_ras_n <= 1'd1;
+               litedramcore_dfi_p2_we_n <= 1'd1;
+               litedramcore_dfi_p2_wrdata_en <= 1'd0;
+               litedramcore_dfi_p2_rddata_en <= 1'd0;
+               litedramcore_dfi_p3_address <= 14'd0;
+               litedramcore_dfi_p3_bank <= 3'd0;
+               litedramcore_dfi_p3_cas_n <= 1'd1;
+               litedramcore_dfi_p3_cs_n <= 1'd1;
+               litedramcore_dfi_p3_ras_n <= 1'd1;
+               litedramcore_dfi_p3_we_n <= 1'd1;
+               litedramcore_dfi_p3_wrdata_en <= 1'd0;
+               litedramcore_dfi_p3_rddata_en <= 1'd0;
+               litedramcore_timer_count1 <= 10'd781;
+               litedramcore_postponer_req_o <= 1'd0;
+               litedramcore_postponer_count <= 1'd0;
+               litedramcore_sequencer_done1 <= 1'd0;
+               litedramcore_sequencer_counter <= 6'd0;
+               litedramcore_sequencer_count <= 1'd0;
+               litedramcore_zqcs_timer_count1 <= 27'd99999999;
+               litedramcore_zqcs_executer_done <= 1'd0;
+               litedramcore_zqcs_executer_counter <= 5'd0;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine0_row <= 14'd0;
+               litedramcore_bankmachine0_row_opened <= 1'd0;
+               litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+               litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine0_trccon_ready <= 1'd0;
+               litedramcore_bankmachine0_trccon_count <= 3'd0;
+               litedramcore_bankmachine0_trascon_ready <= 1'd0;
+               litedramcore_bankmachine0_trascon_count <= 3'd0;
+               litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine1_row <= 14'd0;
+               litedramcore_bankmachine1_row_opened <= 1'd0;
+               litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+               litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine1_trccon_ready <= 1'd0;
+               litedramcore_bankmachine1_trccon_count <= 3'd0;
+               litedramcore_bankmachine1_trascon_ready <= 1'd0;
+               litedramcore_bankmachine1_trascon_count <= 3'd0;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine2_row <= 14'd0;
+               litedramcore_bankmachine2_row_opened <= 1'd0;
+               litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+               litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine2_trccon_ready <= 1'd0;
+               litedramcore_bankmachine2_trccon_count <= 3'd0;
+               litedramcore_bankmachine2_trascon_ready <= 1'd0;
+               litedramcore_bankmachine2_trascon_count <= 3'd0;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine3_row <= 14'd0;
+               litedramcore_bankmachine3_row_opened <= 1'd0;
+               litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+               litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine3_trccon_ready <= 1'd0;
+               litedramcore_bankmachine3_trccon_count <= 3'd0;
+               litedramcore_bankmachine3_trascon_ready <= 1'd0;
+               litedramcore_bankmachine3_trascon_count <= 3'd0;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine4_row <= 14'd0;
+               litedramcore_bankmachine4_row_opened <= 1'd0;
+               litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+               litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine4_trccon_ready <= 1'd0;
+               litedramcore_bankmachine4_trccon_count <= 3'd0;
+               litedramcore_bankmachine4_trascon_ready <= 1'd0;
+               litedramcore_bankmachine4_trascon_count <= 3'd0;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine5_row <= 14'd0;
+               litedramcore_bankmachine5_row_opened <= 1'd0;
+               litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+               litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine5_trccon_ready <= 1'd0;
+               litedramcore_bankmachine5_trccon_count <= 3'd0;
+               litedramcore_bankmachine5_trascon_ready <= 1'd0;
+               litedramcore_bankmachine5_trascon_count <= 3'd0;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine6_row <= 14'd0;
+               litedramcore_bankmachine6_row_opened <= 1'd0;
+               litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+               litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine6_trccon_ready <= 1'd0;
+               litedramcore_bankmachine6_trccon_count <= 3'd0;
+               litedramcore_bankmachine6_trascon_ready <= 1'd0;
+               litedramcore_bankmachine6_trascon_count <= 3'd0;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine7_row <= 14'd0;
+               litedramcore_bankmachine7_row_opened <= 1'd0;
+               litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+               litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine7_trccon_ready <= 1'd0;
+               litedramcore_bankmachine7_trccon_count <= 3'd0;
+               litedramcore_bankmachine7_trascon_ready <= 1'd0;
+               litedramcore_bankmachine7_trascon_count <= 3'd0;
+               litedramcore_choose_cmd_grant <= 3'd0;
+               litedramcore_choose_req_grant <= 3'd0;
+               litedramcore_trrdcon_ready <= 1'd0;
+               litedramcore_trrdcon_count <= 1'd0;
+               litedramcore_tfawcon_ready <= 1'd1;
+               litedramcore_tfawcon_window <= 5'd0;
+               litedramcore_tccdcon_ready <= 1'd0;
+               litedramcore_tccdcon_count <= 1'd0;
+               litedramcore_twtrcon_ready <= 1'd0;
+               litedramcore_twtrcon_count <= 3'd0;
+               litedramcore_time0 <= 5'd0;
+               litedramcore_time1 <= 4'd0;
+               init_done_storage <= 1'd0;
+               init_done_re <= 1'd0;
+               init_error_storage <= 1'd0;
+               init_error_re <= 1'd0;
+               state <= 1'd0;
+               refresher_state <= 2'd0;
+               bankmachine0_state <= 4'd0;
+               bankmachine1_state <= 4'd0;
+               bankmachine2_state <= 4'd0;
+               bankmachine3_state <= 4'd0;
+               bankmachine4_state <= 4'd0;
+               bankmachine5_state <= 4'd0;
+               bankmachine6_state <= 4'd0;
+               bankmachine7_state <= 4'd0;
+               multiplexer_state <= 4'd0;
+               new_master_wdata_ready0 <= 1'd0;
+               new_master_wdata_ready1 <= 1'd0;
+               new_master_wdata_ready2 <= 1'd0;
+               new_master_rdata_valid0 <= 1'd0;
+               new_master_rdata_valid1 <= 1'd0;
+               new_master_rdata_valid2 <= 1'd0;
+               new_master_rdata_valid3 <= 1'd0;
+               new_master_rdata_valid4 <= 1'd0;
+               new_master_rdata_valid5 <= 1'd0;
+               new_master_rdata_valid6 <= 1'd0;
+               new_master_rdata_valid7 <= 1'd0;
+               new_master_rdata_valid8 <= 1'd0;
+               new_master_rdata_valid9 <= 1'd0;
+       end
+end
+
+reg [127:0] mem[0:2097151];
+reg [20:0] memadr;
+always @(posedge sys_clk) begin
+       if (ddrphy_bankmodel0_write_port_we[0])
+               mem[ddrphy_bankmodel0_write_port_adr][7:0] <= ddrphy_bankmodel0_write_port_dat_w[7:0];
+       if (ddrphy_bankmodel0_write_port_we[1])
+               mem[ddrphy_bankmodel0_write_port_adr][15:8] <= ddrphy_bankmodel0_write_port_dat_w[15:8];
+       if (ddrphy_bankmodel0_write_port_we[2])
+               mem[ddrphy_bankmodel0_write_port_adr][23:16] <= ddrphy_bankmodel0_write_port_dat_w[23:16];
+       if (ddrphy_bankmodel0_write_port_we[3])
+               mem[ddrphy_bankmodel0_write_port_adr][31:24] <= ddrphy_bankmodel0_write_port_dat_w[31:24];
+       if (ddrphy_bankmodel0_write_port_we[4])
+               mem[ddrphy_bankmodel0_write_port_adr][39:32] <= ddrphy_bankmodel0_write_port_dat_w[39:32];
+       if (ddrphy_bankmodel0_write_port_we[5])
+               mem[ddrphy_bankmodel0_write_port_adr][47:40] <= ddrphy_bankmodel0_write_port_dat_w[47:40];
+       if (ddrphy_bankmodel0_write_port_we[6])
+               mem[ddrphy_bankmodel0_write_port_adr][55:48] <= ddrphy_bankmodel0_write_port_dat_w[55:48];
+       if (ddrphy_bankmodel0_write_port_we[7])
+               mem[ddrphy_bankmodel0_write_port_adr][63:56] <= ddrphy_bankmodel0_write_port_dat_w[63:56];
+       if (ddrphy_bankmodel0_write_port_we[8])
+               mem[ddrphy_bankmodel0_write_port_adr][71:64] <= ddrphy_bankmodel0_write_port_dat_w[71:64];
+       if (ddrphy_bankmodel0_write_port_we[9])
+               mem[ddrphy_bankmodel0_write_port_adr][79:72] <= ddrphy_bankmodel0_write_port_dat_w[79:72];
+       if (ddrphy_bankmodel0_write_port_we[10])
+               mem[ddrphy_bankmodel0_write_port_adr][87:80] <= ddrphy_bankmodel0_write_port_dat_w[87:80];
+       if (ddrphy_bankmodel0_write_port_we[11])
+               mem[ddrphy_bankmodel0_write_port_adr][95:88] <= ddrphy_bankmodel0_write_port_dat_w[95:88];
+       if (ddrphy_bankmodel0_write_port_we[12])
+               mem[ddrphy_bankmodel0_write_port_adr][103:96] <= ddrphy_bankmodel0_write_port_dat_w[103:96];
+       if (ddrphy_bankmodel0_write_port_we[13])
+               mem[ddrphy_bankmodel0_write_port_adr][111:104] <= ddrphy_bankmodel0_write_port_dat_w[111:104];
+       if (ddrphy_bankmodel0_write_port_we[14])
+               mem[ddrphy_bankmodel0_write_port_adr][119:112] <= ddrphy_bankmodel0_write_port_dat_w[119:112];
+       if (ddrphy_bankmodel0_write_port_we[15])
+               mem[ddrphy_bankmodel0_write_port_adr][127:120] <= ddrphy_bankmodel0_write_port_dat_w[127:120];
+       memadr <= ddrphy_bankmodel0_write_port_adr;
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign ddrphy_bankmodel0_write_port_dat_r = mem[memadr];
+assign ddrphy_bankmodel0_read_port_dat_r = mem[ddrphy_bankmodel0_read_port_adr];
+
+reg [127:0] mem_1[0:2097151];
+reg [20:0] memadr_1;
+always @(posedge sys_clk) begin
+       if (ddrphy_bankmodel1_write_port_we[0])
+               mem_1[ddrphy_bankmodel1_write_port_adr][7:0] <= ddrphy_bankmodel1_write_port_dat_w[7:0];
+       if (ddrphy_bankmodel1_write_port_we[1])
+               mem_1[ddrphy_bankmodel1_write_port_adr][15:8] <= ddrphy_bankmodel1_write_port_dat_w[15:8];
+       if (ddrphy_bankmodel1_write_port_we[2])
+               mem_1[ddrphy_bankmodel1_write_port_adr][23:16] <= ddrphy_bankmodel1_write_port_dat_w[23:16];
+       if (ddrphy_bankmodel1_write_port_we[3])
+               mem_1[ddrphy_bankmodel1_write_port_adr][31:24] <= ddrphy_bankmodel1_write_port_dat_w[31:24];
+       if (ddrphy_bankmodel1_write_port_we[4])
+               mem_1[ddrphy_bankmodel1_write_port_adr][39:32] <= ddrphy_bankmodel1_write_port_dat_w[39:32];
+       if (ddrphy_bankmodel1_write_port_we[5])
+               mem_1[ddrphy_bankmodel1_write_port_adr][47:40] <= ddrphy_bankmodel1_write_port_dat_w[47:40];
+       if (ddrphy_bankmodel1_write_port_we[6])
+               mem_1[ddrphy_bankmodel1_write_port_adr][55:48] <= ddrphy_bankmodel1_write_port_dat_w[55:48];
+       if (ddrphy_bankmodel1_write_port_we[7])
+               mem_1[ddrphy_bankmodel1_write_port_adr][63:56] <= ddrphy_bankmodel1_write_port_dat_w[63:56];
+       if (ddrphy_bankmodel1_write_port_we[8])
+               mem_1[ddrphy_bankmodel1_write_port_adr][71:64] <= ddrphy_bankmodel1_write_port_dat_w[71:64];
+       if (ddrphy_bankmodel1_write_port_we[9])
+               mem_1[ddrphy_bankmodel1_write_port_adr][79:72] <= ddrphy_bankmodel1_write_port_dat_w[79:72];
+       if (ddrphy_bankmodel1_write_port_we[10])
+               mem_1[ddrphy_bankmodel1_write_port_adr][87:80] <= ddrphy_bankmodel1_write_port_dat_w[87:80];
+       if (ddrphy_bankmodel1_write_port_we[11])
+               mem_1[ddrphy_bankmodel1_write_port_adr][95:88] <= ddrphy_bankmodel1_write_port_dat_w[95:88];
+       if (ddrphy_bankmodel1_write_port_we[12])
+               mem_1[ddrphy_bankmodel1_write_port_adr][103:96] <= ddrphy_bankmodel1_write_port_dat_w[103:96];
+       if (ddrphy_bankmodel1_write_port_we[13])
+               mem_1[ddrphy_bankmodel1_write_port_adr][111:104] <= ddrphy_bankmodel1_write_port_dat_w[111:104];
+       if (ddrphy_bankmodel1_write_port_we[14])
+               mem_1[ddrphy_bankmodel1_write_port_adr][119:112] <= ddrphy_bankmodel1_write_port_dat_w[119:112];
+       if (ddrphy_bankmodel1_write_port_we[15])
+               mem_1[ddrphy_bankmodel1_write_port_adr][127:120] <= ddrphy_bankmodel1_write_port_dat_w[127:120];
+       memadr_1 <= ddrphy_bankmodel1_write_port_adr;
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign ddrphy_bankmodel1_write_port_dat_r = mem_1[memadr_1];
+assign ddrphy_bankmodel1_read_port_dat_r = mem_1[ddrphy_bankmodel1_read_port_adr];
+
+reg [127:0] mem_2[0:2097151];
+reg [20:0] memadr_2;
+always @(posedge sys_clk) begin
+       if (ddrphy_bankmodel2_write_port_we[0])
+               mem_2[ddrphy_bankmodel2_write_port_adr][7:0] <= ddrphy_bankmodel2_write_port_dat_w[7:0];
+       if (ddrphy_bankmodel2_write_port_we[1])
+               mem_2[ddrphy_bankmodel2_write_port_adr][15:8] <= ddrphy_bankmodel2_write_port_dat_w[15:8];
+       if (ddrphy_bankmodel2_write_port_we[2])
+               mem_2[ddrphy_bankmodel2_write_port_adr][23:16] <= ddrphy_bankmodel2_write_port_dat_w[23:16];
+       if (ddrphy_bankmodel2_write_port_we[3])
+               mem_2[ddrphy_bankmodel2_write_port_adr][31:24] <= ddrphy_bankmodel2_write_port_dat_w[31:24];
+       if (ddrphy_bankmodel2_write_port_we[4])
+               mem_2[ddrphy_bankmodel2_write_port_adr][39:32] <= ddrphy_bankmodel2_write_port_dat_w[39:32];
+       if (ddrphy_bankmodel2_write_port_we[5])
+               mem_2[ddrphy_bankmodel2_write_port_adr][47:40] <= ddrphy_bankmodel2_write_port_dat_w[47:40];
+       if (ddrphy_bankmodel2_write_port_we[6])
+               mem_2[ddrphy_bankmodel2_write_port_adr][55:48] <= ddrphy_bankmodel2_write_port_dat_w[55:48];
+       if (ddrphy_bankmodel2_write_port_we[7])
+               mem_2[ddrphy_bankmodel2_write_port_adr][63:56] <= ddrphy_bankmodel2_write_port_dat_w[63:56];
+       if (ddrphy_bankmodel2_write_port_we[8])
+               mem_2[ddrphy_bankmodel2_write_port_adr][71:64] <= ddrphy_bankmodel2_write_port_dat_w[71:64];
+       if (ddrphy_bankmodel2_write_port_we[9])
+               mem_2[ddrphy_bankmodel2_write_port_adr][79:72] <= ddrphy_bankmodel2_write_port_dat_w[79:72];
+       if (ddrphy_bankmodel2_write_port_we[10])
+               mem_2[ddrphy_bankmodel2_write_port_adr][87:80] <= ddrphy_bankmodel2_write_port_dat_w[87:80];
+       if (ddrphy_bankmodel2_write_port_we[11])
+               mem_2[ddrphy_bankmodel2_write_port_adr][95:88] <= ddrphy_bankmodel2_write_port_dat_w[95:88];
+       if (ddrphy_bankmodel2_write_port_we[12])
+               mem_2[ddrphy_bankmodel2_write_port_adr][103:96] <= ddrphy_bankmodel2_write_port_dat_w[103:96];
+       if (ddrphy_bankmodel2_write_port_we[13])
+               mem_2[ddrphy_bankmodel2_write_port_adr][111:104] <= ddrphy_bankmodel2_write_port_dat_w[111:104];
+       if (ddrphy_bankmodel2_write_port_we[14])
+               mem_2[ddrphy_bankmodel2_write_port_adr][119:112] <= ddrphy_bankmodel2_write_port_dat_w[119:112];
+       if (ddrphy_bankmodel2_write_port_we[15])
+               mem_2[ddrphy_bankmodel2_write_port_adr][127:120] <= ddrphy_bankmodel2_write_port_dat_w[127:120];
+       memadr_2 <= ddrphy_bankmodel2_write_port_adr;
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign ddrphy_bankmodel2_write_port_dat_r = mem_2[memadr_2];
+assign ddrphy_bankmodel2_read_port_dat_r = mem_2[ddrphy_bankmodel2_read_port_adr];
+
+reg [127:0] mem_3[0:2097151];
+reg [20:0] memadr_3;
+always @(posedge sys_clk) begin
+       if (ddrphy_bankmodel3_write_port_we[0])
+               mem_3[ddrphy_bankmodel3_write_port_adr][7:0] <= ddrphy_bankmodel3_write_port_dat_w[7:0];
+       if (ddrphy_bankmodel3_write_port_we[1])
+               mem_3[ddrphy_bankmodel3_write_port_adr][15:8] <= ddrphy_bankmodel3_write_port_dat_w[15:8];
+       if (ddrphy_bankmodel3_write_port_we[2])
+               mem_3[ddrphy_bankmodel3_write_port_adr][23:16] <= ddrphy_bankmodel3_write_port_dat_w[23:16];
+       if (ddrphy_bankmodel3_write_port_we[3])
+               mem_3[ddrphy_bankmodel3_write_port_adr][31:24] <= ddrphy_bankmodel3_write_port_dat_w[31:24];
+       if (ddrphy_bankmodel3_write_port_we[4])
+               mem_3[ddrphy_bankmodel3_write_port_adr][39:32] <= ddrphy_bankmodel3_write_port_dat_w[39:32];
+       if (ddrphy_bankmodel3_write_port_we[5])
+               mem_3[ddrphy_bankmodel3_write_port_adr][47:40] <= ddrphy_bankmodel3_write_port_dat_w[47:40];
+       if (ddrphy_bankmodel3_write_port_we[6])
+               mem_3[ddrphy_bankmodel3_write_port_adr][55:48] <= ddrphy_bankmodel3_write_port_dat_w[55:48];
+       if (ddrphy_bankmodel3_write_port_we[7])
+               mem_3[ddrphy_bankmodel3_write_port_adr][63:56] <= ddrphy_bankmodel3_write_port_dat_w[63:56];
+       if (ddrphy_bankmodel3_write_port_we[8])
+               mem_3[ddrphy_bankmodel3_write_port_adr][71:64] <= ddrphy_bankmodel3_write_port_dat_w[71:64];
+       if (ddrphy_bankmodel3_write_port_we[9])
+               mem_3[ddrphy_bankmodel3_write_port_adr][79:72] <= ddrphy_bankmodel3_write_port_dat_w[79:72];
+       if (ddrphy_bankmodel3_write_port_we[10])
+               mem_3[ddrphy_bankmodel3_write_port_adr][87:80] <= ddrphy_bankmodel3_write_port_dat_w[87:80];
+       if (ddrphy_bankmodel3_write_port_we[11])
+               mem_3[ddrphy_bankmodel3_write_port_adr][95:88] <= ddrphy_bankmodel3_write_port_dat_w[95:88];
+       if (ddrphy_bankmodel3_write_port_we[12])
+               mem_3[ddrphy_bankmodel3_write_port_adr][103:96] <= ddrphy_bankmodel3_write_port_dat_w[103:96];
+       if (ddrphy_bankmodel3_write_port_we[13])
+               mem_3[ddrphy_bankmodel3_write_port_adr][111:104] <= ddrphy_bankmodel3_write_port_dat_w[111:104];
+       if (ddrphy_bankmodel3_write_port_we[14])
+               mem_3[ddrphy_bankmodel3_write_port_adr][119:112] <= ddrphy_bankmodel3_write_port_dat_w[119:112];
+       if (ddrphy_bankmodel3_write_port_we[15])
+               mem_3[ddrphy_bankmodel3_write_port_adr][127:120] <= ddrphy_bankmodel3_write_port_dat_w[127:120];
+       memadr_3 <= ddrphy_bankmodel3_write_port_adr;
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign ddrphy_bankmodel3_write_port_dat_r = mem_3[memadr_3];
+assign ddrphy_bankmodel3_read_port_dat_r = mem_3[ddrphy_bankmodel3_read_port_adr];
+
+reg [127:0] mem_4[0:2097151];
+reg [20:0] memadr_4;
+always @(posedge sys_clk) begin
+       if (ddrphy_bankmodel4_write_port_we[0])
+               mem_4[ddrphy_bankmodel4_write_port_adr][7:0] <= ddrphy_bankmodel4_write_port_dat_w[7:0];
+       if (ddrphy_bankmodel4_write_port_we[1])
+               mem_4[ddrphy_bankmodel4_write_port_adr][15:8] <= ddrphy_bankmodel4_write_port_dat_w[15:8];
+       if (ddrphy_bankmodel4_write_port_we[2])
+               mem_4[ddrphy_bankmodel4_write_port_adr][23:16] <= ddrphy_bankmodel4_write_port_dat_w[23:16];
+       if (ddrphy_bankmodel4_write_port_we[3])
+               mem_4[ddrphy_bankmodel4_write_port_adr][31:24] <= ddrphy_bankmodel4_write_port_dat_w[31:24];
+       if (ddrphy_bankmodel4_write_port_we[4])
+               mem_4[ddrphy_bankmodel4_write_port_adr][39:32] <= ddrphy_bankmodel4_write_port_dat_w[39:32];
+       if (ddrphy_bankmodel4_write_port_we[5])
+               mem_4[ddrphy_bankmodel4_write_port_adr][47:40] <= ddrphy_bankmodel4_write_port_dat_w[47:40];
+       if (ddrphy_bankmodel4_write_port_we[6])
+               mem_4[ddrphy_bankmodel4_write_port_adr][55:48] <= ddrphy_bankmodel4_write_port_dat_w[55:48];
+       if (ddrphy_bankmodel4_write_port_we[7])
+               mem_4[ddrphy_bankmodel4_write_port_adr][63:56] <= ddrphy_bankmodel4_write_port_dat_w[63:56];
+       if (ddrphy_bankmodel4_write_port_we[8])
+               mem_4[ddrphy_bankmodel4_write_port_adr][71:64] <= ddrphy_bankmodel4_write_port_dat_w[71:64];
+       if (ddrphy_bankmodel4_write_port_we[9])
+               mem_4[ddrphy_bankmodel4_write_port_adr][79:72] <= ddrphy_bankmodel4_write_port_dat_w[79:72];
+       if (ddrphy_bankmodel4_write_port_we[10])
+               mem_4[ddrphy_bankmodel4_write_port_adr][87:80] <= ddrphy_bankmodel4_write_port_dat_w[87:80];
+       if (ddrphy_bankmodel4_write_port_we[11])
+               mem_4[ddrphy_bankmodel4_write_port_adr][95:88] <= ddrphy_bankmodel4_write_port_dat_w[95:88];
+       if (ddrphy_bankmodel4_write_port_we[12])
+               mem_4[ddrphy_bankmodel4_write_port_adr][103:96] <= ddrphy_bankmodel4_write_port_dat_w[103:96];
+       if (ddrphy_bankmodel4_write_port_we[13])
+               mem_4[ddrphy_bankmodel4_write_port_adr][111:104] <= ddrphy_bankmodel4_write_port_dat_w[111:104];
+       if (ddrphy_bankmodel4_write_port_we[14])
+               mem_4[ddrphy_bankmodel4_write_port_adr][119:112] <= ddrphy_bankmodel4_write_port_dat_w[119:112];
+       if (ddrphy_bankmodel4_write_port_we[15])
+               mem_4[ddrphy_bankmodel4_write_port_adr][127:120] <= ddrphy_bankmodel4_write_port_dat_w[127:120];
+       memadr_4 <= ddrphy_bankmodel4_write_port_adr;
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign ddrphy_bankmodel4_write_port_dat_r = mem_4[memadr_4];
+assign ddrphy_bankmodel4_read_port_dat_r = mem_4[ddrphy_bankmodel4_read_port_adr];
+
+reg [127:0] mem_5[0:2097151];
+reg [20:0] memadr_5;
+always @(posedge sys_clk) begin
+       if (ddrphy_bankmodel5_write_port_we[0])
+               mem_5[ddrphy_bankmodel5_write_port_adr][7:0] <= ddrphy_bankmodel5_write_port_dat_w[7:0];
+       if (ddrphy_bankmodel5_write_port_we[1])
+               mem_5[ddrphy_bankmodel5_write_port_adr][15:8] <= ddrphy_bankmodel5_write_port_dat_w[15:8];
+       if (ddrphy_bankmodel5_write_port_we[2])
+               mem_5[ddrphy_bankmodel5_write_port_adr][23:16] <= ddrphy_bankmodel5_write_port_dat_w[23:16];
+       if (ddrphy_bankmodel5_write_port_we[3])
+               mem_5[ddrphy_bankmodel5_write_port_adr][31:24] <= ddrphy_bankmodel5_write_port_dat_w[31:24];
+       if (ddrphy_bankmodel5_write_port_we[4])
+               mem_5[ddrphy_bankmodel5_write_port_adr][39:32] <= ddrphy_bankmodel5_write_port_dat_w[39:32];
+       if (ddrphy_bankmodel5_write_port_we[5])
+               mem_5[ddrphy_bankmodel5_write_port_adr][47:40] <= ddrphy_bankmodel5_write_port_dat_w[47:40];
+       if (ddrphy_bankmodel5_write_port_we[6])
+               mem_5[ddrphy_bankmodel5_write_port_adr][55:48] <= ddrphy_bankmodel5_write_port_dat_w[55:48];
+       if (ddrphy_bankmodel5_write_port_we[7])
+               mem_5[ddrphy_bankmodel5_write_port_adr][63:56] <= ddrphy_bankmodel5_write_port_dat_w[63:56];
+       if (ddrphy_bankmodel5_write_port_we[8])
+               mem_5[ddrphy_bankmodel5_write_port_adr][71:64] <= ddrphy_bankmodel5_write_port_dat_w[71:64];
+       if (ddrphy_bankmodel5_write_port_we[9])
+               mem_5[ddrphy_bankmodel5_write_port_adr][79:72] <= ddrphy_bankmodel5_write_port_dat_w[79:72];
+       if (ddrphy_bankmodel5_write_port_we[10])
+               mem_5[ddrphy_bankmodel5_write_port_adr][87:80] <= ddrphy_bankmodel5_write_port_dat_w[87:80];
+       if (ddrphy_bankmodel5_write_port_we[11])
+               mem_5[ddrphy_bankmodel5_write_port_adr][95:88] <= ddrphy_bankmodel5_write_port_dat_w[95:88];
+       if (ddrphy_bankmodel5_write_port_we[12])
+               mem_5[ddrphy_bankmodel5_write_port_adr][103:96] <= ddrphy_bankmodel5_write_port_dat_w[103:96];
+       if (ddrphy_bankmodel5_write_port_we[13])
+               mem_5[ddrphy_bankmodel5_write_port_adr][111:104] <= ddrphy_bankmodel5_write_port_dat_w[111:104];
+       if (ddrphy_bankmodel5_write_port_we[14])
+               mem_5[ddrphy_bankmodel5_write_port_adr][119:112] <= ddrphy_bankmodel5_write_port_dat_w[119:112];
+       if (ddrphy_bankmodel5_write_port_we[15])
+               mem_5[ddrphy_bankmodel5_write_port_adr][127:120] <= ddrphy_bankmodel5_write_port_dat_w[127:120];
+       memadr_5 <= ddrphy_bankmodel5_write_port_adr;
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign ddrphy_bankmodel5_write_port_dat_r = mem_5[memadr_5];
+assign ddrphy_bankmodel5_read_port_dat_r = mem_5[ddrphy_bankmodel5_read_port_adr];
+
+reg [127:0] mem_6[0:2097151];
+reg [20:0] memadr_6;
+always @(posedge sys_clk) begin
+       if (ddrphy_bankmodel6_write_port_we[0])
+               mem_6[ddrphy_bankmodel6_write_port_adr][7:0] <= ddrphy_bankmodel6_write_port_dat_w[7:0];
+       if (ddrphy_bankmodel6_write_port_we[1])
+               mem_6[ddrphy_bankmodel6_write_port_adr][15:8] <= ddrphy_bankmodel6_write_port_dat_w[15:8];
+       if (ddrphy_bankmodel6_write_port_we[2])
+               mem_6[ddrphy_bankmodel6_write_port_adr][23:16] <= ddrphy_bankmodel6_write_port_dat_w[23:16];
+       if (ddrphy_bankmodel6_write_port_we[3])
+               mem_6[ddrphy_bankmodel6_write_port_adr][31:24] <= ddrphy_bankmodel6_write_port_dat_w[31:24];
+       if (ddrphy_bankmodel6_write_port_we[4])
+               mem_6[ddrphy_bankmodel6_write_port_adr][39:32] <= ddrphy_bankmodel6_write_port_dat_w[39:32];
+       if (ddrphy_bankmodel6_write_port_we[5])
+               mem_6[ddrphy_bankmodel6_write_port_adr][47:40] <= ddrphy_bankmodel6_write_port_dat_w[47:40];
+       if (ddrphy_bankmodel6_write_port_we[6])
+               mem_6[ddrphy_bankmodel6_write_port_adr][55:48] <= ddrphy_bankmodel6_write_port_dat_w[55:48];
+       if (ddrphy_bankmodel6_write_port_we[7])
+               mem_6[ddrphy_bankmodel6_write_port_adr][63:56] <= ddrphy_bankmodel6_write_port_dat_w[63:56];
+       if (ddrphy_bankmodel6_write_port_we[8])
+               mem_6[ddrphy_bankmodel6_write_port_adr][71:64] <= ddrphy_bankmodel6_write_port_dat_w[71:64];
+       if (ddrphy_bankmodel6_write_port_we[9])
+               mem_6[ddrphy_bankmodel6_write_port_adr][79:72] <= ddrphy_bankmodel6_write_port_dat_w[79:72];
+       if (ddrphy_bankmodel6_write_port_we[10])
+               mem_6[ddrphy_bankmodel6_write_port_adr][87:80] <= ddrphy_bankmodel6_write_port_dat_w[87:80];
+       if (ddrphy_bankmodel6_write_port_we[11])
+               mem_6[ddrphy_bankmodel6_write_port_adr][95:88] <= ddrphy_bankmodel6_write_port_dat_w[95:88];
+       if (ddrphy_bankmodel6_write_port_we[12])
+               mem_6[ddrphy_bankmodel6_write_port_adr][103:96] <= ddrphy_bankmodel6_write_port_dat_w[103:96];
+       if (ddrphy_bankmodel6_write_port_we[13])
+               mem_6[ddrphy_bankmodel6_write_port_adr][111:104] <= ddrphy_bankmodel6_write_port_dat_w[111:104];
+       if (ddrphy_bankmodel6_write_port_we[14])
+               mem_6[ddrphy_bankmodel6_write_port_adr][119:112] <= ddrphy_bankmodel6_write_port_dat_w[119:112];
+       if (ddrphy_bankmodel6_write_port_we[15])
+               mem_6[ddrphy_bankmodel6_write_port_adr][127:120] <= ddrphy_bankmodel6_write_port_dat_w[127:120];
+       memadr_6 <= ddrphy_bankmodel6_write_port_adr;
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign ddrphy_bankmodel6_write_port_dat_r = mem_6[memadr_6];
+assign ddrphy_bankmodel6_read_port_dat_r = mem_6[ddrphy_bankmodel6_read_port_adr];
+
+reg [127:0] mem_7[0:2097151];
+reg [20:0] memadr_7;
+always @(posedge sys_clk) begin
+       if (ddrphy_bankmodel7_write_port_we[0])
+               mem_7[ddrphy_bankmodel7_write_port_adr][7:0] <= ddrphy_bankmodel7_write_port_dat_w[7:0];
+       if (ddrphy_bankmodel7_write_port_we[1])
+               mem_7[ddrphy_bankmodel7_write_port_adr][15:8] <= ddrphy_bankmodel7_write_port_dat_w[15:8];
+       if (ddrphy_bankmodel7_write_port_we[2])
+               mem_7[ddrphy_bankmodel7_write_port_adr][23:16] <= ddrphy_bankmodel7_write_port_dat_w[23:16];
+       if (ddrphy_bankmodel7_write_port_we[3])
+               mem_7[ddrphy_bankmodel7_write_port_adr][31:24] <= ddrphy_bankmodel7_write_port_dat_w[31:24];
+       if (ddrphy_bankmodel7_write_port_we[4])
+               mem_7[ddrphy_bankmodel7_write_port_adr][39:32] <= ddrphy_bankmodel7_write_port_dat_w[39:32];
+       if (ddrphy_bankmodel7_write_port_we[5])
+               mem_7[ddrphy_bankmodel7_write_port_adr][47:40] <= ddrphy_bankmodel7_write_port_dat_w[47:40];
+       if (ddrphy_bankmodel7_write_port_we[6])
+               mem_7[ddrphy_bankmodel7_write_port_adr][55:48] <= ddrphy_bankmodel7_write_port_dat_w[55:48];
+       if (ddrphy_bankmodel7_write_port_we[7])
+               mem_7[ddrphy_bankmodel7_write_port_adr][63:56] <= ddrphy_bankmodel7_write_port_dat_w[63:56];
+       if (ddrphy_bankmodel7_write_port_we[8])
+               mem_7[ddrphy_bankmodel7_write_port_adr][71:64] <= ddrphy_bankmodel7_write_port_dat_w[71:64];
+       if (ddrphy_bankmodel7_write_port_we[9])
+               mem_7[ddrphy_bankmodel7_write_port_adr][79:72] <= ddrphy_bankmodel7_write_port_dat_w[79:72];
+       if (ddrphy_bankmodel7_write_port_we[10])
+               mem_7[ddrphy_bankmodel7_write_port_adr][87:80] <= ddrphy_bankmodel7_write_port_dat_w[87:80];
+       if (ddrphy_bankmodel7_write_port_we[11])
+               mem_7[ddrphy_bankmodel7_write_port_adr][95:88] <= ddrphy_bankmodel7_write_port_dat_w[95:88];
+       if (ddrphy_bankmodel7_write_port_we[12])
+               mem_7[ddrphy_bankmodel7_write_port_adr][103:96] <= ddrphy_bankmodel7_write_port_dat_w[103:96];
+       if (ddrphy_bankmodel7_write_port_we[13])
+               mem_7[ddrphy_bankmodel7_write_port_adr][111:104] <= ddrphy_bankmodel7_write_port_dat_w[111:104];
+       if (ddrphy_bankmodel7_write_port_we[14])
+               mem_7[ddrphy_bankmodel7_write_port_adr][119:112] <= ddrphy_bankmodel7_write_port_dat_w[119:112];
+       if (ddrphy_bankmodel7_write_port_we[15])
+               mem_7[ddrphy_bankmodel7_write_port_adr][127:120] <= ddrphy_bankmodel7_write_port_dat_w[127:120];
+       memadr_7 <= ddrphy_bankmodel7_write_port_adr;
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign ddrphy_bankmodel7_write_port_dat_r = mem_7[memadr_7];
+assign ddrphy_bankmodel7_read_port_dat_r = mem_7[ddrphy_bankmodel7_read_port_adr];
+
+reg [23:0] storage[0:15];
+reg [23:0] memdat;
+always @(posedge sys_clk) begin
+       if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+               storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+       memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_1[0:15];
+reg [23:0] memdat_1;
+always @(posedge sys_clk) begin
+       if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+               storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_2[0:15];
+reg [23:0] memdat_2;
+always @(posedge sys_clk) begin
+       if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+               storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_3[0:15];
+reg [23:0] memdat_3;
+always @(posedge sys_clk) begin
+       if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+               storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_4[0:15];
+reg [23:0] memdat_4;
+always @(posedge sys_clk) begin
+       if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+               storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_5[0:15];
+reg [23:0] memdat_5;
+always @(posedge sys_clk) begin
+       if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+               storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_6[0:15];
+reg [23:0] memdat_6;
+always @(posedge sys_clk) begin
+       if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+               storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_7[0:15];
+reg [23:0] memdat_7;
+always @(posedge sys_clk) begin
+       if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+               storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+
+endmodule