Added synth_ice40 support for latches via logic loops

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 83009d1765b758d6cb9470f585271cf31c18aea9..14761c6c8f42712bd40a16c28fa688cc0f3194d9 100644 (file)
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -23,6 +23,7 @@ techlibs/ice40/brams_init3.vh: techlibs/ice40/brams_init.mk
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/arith_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
 

diff --git a/techlibs/ice40/latches_map.v b/techlibs/ice40/latches_map.v
new file mode 100644 (file)
index 0000000..c28f88c
--- /dev/null
+++ b/techlibs/ice40/latches_map.v
@@ -0,0 +1,11 @@
+module \$_DLATCH_N_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = E ? D : Q;
+endmodule

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index cadf3b038b823801b7fcf92c0a44459d97adfb98..0134c13c109b4b98f6b11e2341a3a2729842ab23 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -214,6 +214,7 @@ struct SynthIce40Pass : public ScriptPass
                                run("abc", "      (only if -abc2)");
                                run("ice40_opt", "(only if -abc2)");
                        }
+                       run("techmap -map +/ice40/latches_map.v");
                        run("abc -lut 4");
                        run("clean");
                }