equiv_purge bugfix, using SigChunk in Yosys namespace

diff --git a/kernel/yosys.h b/kernel/yosys.h
index 6aacd4d54bbd6a1e3ed0422722a056e6774e8fb6..af849fca821575d61757de4f5dd7b9cc5e36c939 100644 (file)
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -169,6 +169,7 @@ namespace RTLIL {
        struct IdString;
        struct Const;
        struct SigBit;
+       struct SigChunk;
        struct SigSpec;
        struct Wire;
        struct Cell;
@@ -184,6 +185,7 @@ namespace AST {
 using RTLIL::IdString;
 using RTLIL::Const;
 using RTLIL::SigBit;
+using RTLIL::SigChunk;
 using RTLIL::SigSpec;
 using RTLIL::Wire;
 using RTLIL::Cell;

diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index 34318dec2192964bda320fcfec2b555c7a22a3af..982176c44f6684fe07c116522b8bda0a68d3d2e3 100644 (file)
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -156,7 +156,7 @@ struct EquivMiterWorker
                struct RewriteSigSpecWorker {
                        RTLIL::Module * mod;
                        void operator()(SigSpec &sig) {
-                               vector<RTLIL::SigChunk> chunks = sig.chunks();
+                               vector<SigChunk> chunks = sig.chunks();
                                for (auto &c : chunks)
                                        if (c.wire != NULL)
                                                c.wire = mod->wires_.at(c.wire->name);

diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index e14ffe31c0da50831299c8a75d35bd288f98d5d3..f4141ad4dfcca43adfb544709e604bda9d8993fe 100644 (file)
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -162,8 +162,9 @@ struct EquivPurgeWorker
 
                srcsig.sort_and_unify();
 
-               for (SigSpec sig : srcsig.chunks())
-                       rewrite_sigmap.add(sig, make_input(sig));
+               for (SigChunk chunk : srcsig.chunks())
+                       if (chunk.wire != nullptr)
+                               rewrite_sigmap.add(chunk, make_input(chunk));
 
                for (auto cell : module->cells())
                        if (cell->type == "$equiv")

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 68a7fc1f6ff3e5bfd667837eb865e53cf138b7ad..d9ec4bc6a850eb3ef2f3c3df497e6e7ccf7d8b6f 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -737,7 +737,7 @@ struct ExtractPass : public Pass {
                                        RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
                                        newCell->parameters = cell->parameters;
                                        for (auto &conn : cell->connections()) {
-                                               std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
+                                               std::vector<SigChunk> chunks = sigmap(conn.second);
                                                for (auto &chunk : chunks)
                                                        if (chunk.wire != NULL)
                                                                chunk.wire = newMod->wires_.at(chunk.wire->name);

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 592710eda66891a8b92f880248eb52342de6720c..19b2bda9cbafa7426e945f4f8844c4e2f9e7ce5a 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -49,7 +49,7 @@ void apply_prefix(std::string prefix, std::string &id)
 
 void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
 {
-       std::vector<RTLIL::SigChunk> chunks = sig;
+       vector<SigChunk> chunks = sig;
        for (auto &chunk : chunks)
                if (chunk.wire != NULL) {
                        std::string wire_name = chunk.wire->name.str();