New clock_domain API

diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py
index c73d2474eb7f636c16a346412346ddf01e7d8895..f1d366dfa896ac0e76b2f53408f78a06d18073c7 100644 (file)
--- a/mibuild/altera_quartus.py
+++ b/mibuild/altera_quartus.py
@@ -72,12 +72,12 @@ quartus_sta {build_name}.qpf
                raise OSError("Subprocess failed")
 
 class AlteraQuartusPlatform(GenericPlatform):
-       def build(self, fragment, clock_domains=None, build_dir="build", build_name="top",
+       def build(self, fragment, build_dir="build", build_name="top",
                        quartus_path="/opt/Altera", run=True):
                tools.mkdir_noerror(build_dir)
                os.chdir(build_dir)
 
-               v_src, named_sc, named_pc = self.get_verilog(fragment, clock_domains)
+               v_src, named_sc, named_pc = self.get_verilog(fragment)
                v_file = build_name + ".v"
                tools.write_to_file(v_file, v_src)
                sources = self.sources + [(v_file, "verilog")]

diff --git a/mibuild/crg.py b/mibuild/crg.py
index 131b7e6270f589f89fd1888de950dc4f0b8b69e6..5d8510dd71b7bb823a74418636660465950c7f2c 100644 (file)
--- a/mibuild/crg.py
+++ b/mibuild/crg.py
@@ -1,20 +1,12 @@
 from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 
-class CRG(Module):
-       def get_clock_domains(self):
-               r = dict()
-               for k, v in self.__dict__.items():
-                       if isinstance(v, ClockDomain):
-                               r[v.name] = v
-               return r
-
-class SimpleCRG(CRG):
+class SimpleCRG(Module):
        def __init__(self, platform, clk_name, rst_name, rst_invert=False):
-                       self.cd = ClockDomain("sys")
-                       platform.request(clk_name, None, self.cd.clk)
+                       self.clock_domains.cd_sys = ClockDomain()
+                       platform.request(clk_name, None, self.cd_sys.clk)
                        if rst_invert:
                                rst_n = platform.request(rst_name)
-                               self.comb += self.cd.rst.eq(~rst_n)
+                               self.comb += self.cd_sys.rst.eq(~rst_n)
                        else:
-                               platform.request(rst_name, None, self.cd.rst)
+                               platform.request(rst_name, None, self.cd_sys.rst)

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index 89360bc49f1d935622029fb30c52c3e755854b2d..d3fe50b22439dc229d0be0cd01d2cf299749b885 100644 (file)
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -197,7 +197,7 @@ class GenericPlatform:
                                if language is not None:
                                        self.add_source(os.path.join(root, filename), language)
 
-       def get_verilog(self, fragment, clock_domains=None, **kwargs):
+       def get_verilog(self, fragment, **kwargs):
                if not isinstance(fragment, Fragment):
                        fragment = fragment.get_fragment()
                # We may create a temporary clock/reset generator that would request pins.
@@ -206,17 +206,15 @@ class GenericPlatform:
                backup = self.constraint_manager.save()
                try:
                        # if none exists, create a default clock domain and drive it
-                       if clock_domains is None:
+                       if not fragment.clock_domains:
                                if self.default_crg_factory is None:
                                        raise NotImplementedError("No clock/reset generator defined by either platform or user")
                                crg = self.default_crg_factory(self)
                                frag = fragment + crg.get_fragment()
-                               clock_domains = crg.get_clock_domains()
                        else:
                                frag = fragment
                        # generate Verilog
-                       src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
-                               clock_domains=clock_domains, return_ns=True, **kwargs)
+                       src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), return_ns=True, **kwargs)
                        # resolve signal names in constraints
                        sc = self.constraint_manager.get_sig_constraints()
                        named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]
@@ -230,7 +228,7 @@ class GenericPlatform:
                        self.constraint_manager.restore(backup)
                return src, named_sc, named_pc
                
-       def build(self, fragment, clock_domains=None):
+       def build(self, fragment):
                raise NotImplementedError("GenericPlatform.build must be overloaded")
 
        def add_arguments(self, parser):

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 698d0b04fc01ef24c655d588b832c6cda621d635..dd3d3263046cc8c6cdf9b0294f3ddab80626fb41 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -3,10 +3,11 @@ from decimal import Decimal
 
 from migen.fhdl.structure import *
 from migen.fhdl.specials import Instance, SynthesisDirective
+from migen.fhdl.module import Module
 from migen.genlib.cdc import *
 
 from mibuild.generic_platform import *
-from mibuild.crg import CRG, SimpleCRG
+from mibuild.crg import SimpleCRG
 from mibuild import tools
 
 def _add_period_constraint(platform, clk, period):
@@ -18,20 +19,21 @@ class CRG_SE(SimpleCRG):
                SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
                _add_period_constraint(platform, self.cd.clk, period)
 
-class CRG_DS(CRG):
-       def __init__(self, platform, clk_name, rst_name, period):
-               self.cd = ClockDomain("sys")
+class CRG_DS(Module):
+       def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
+               self.clock_domains.cd_sys = ClockDomain()
                self._clk = platform.request(clk_name)
-               platform.request(rst_name, None, self.cd.rst)
+               if rst_invert:
+                       rst_n = platform.request(rst_name)
+                       self.comb += self.cd_sys.rst.eq(~rst_n)
+               else:
+                       platform.request(rst_name, None, self.cd.rst)
                _add_period_constraint(platform, self._clk.p, period)
-
-       def get_fragment(self):
-               ibufg = Instance("IBUFGDS",
+               self.specials += Instance("IBUFGDS",
                        Instance.Input("I", self._clk.p),
                        Instance.Input("IB", self._clk.n),
                        Instance.Output("O", self.cd.clk)
                )
-               return Fragment(specials={ibufg})
 
 def _format_constraint(c):
        if isinstance(c, Pins):
@@ -127,12 +129,12 @@ class XilinxISEPlatform(GenericPlatform):
                so.update(special_overrides)
                return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
 
-       def build(self, fragment, clock_domains=None, build_dir="build", build_name="top",
+       def build(self, fragment, build_dir="build", build_name="top",
                        ise_path="/opt/Xilinx", run=True):
                tools.mkdir_noerror(build_dir)
                os.chdir(build_dir)
 
-               v_src, named_sc, named_pc = self.get_verilog(fragment, clock_domains)
+               v_src, named_sc, named_pc = self.get_verilog(fragment)
                v_file = build_name + ".v"
                tools.write_to_file(v_file, v_src)
                sources = self.sources + [(v_file, "verilog")]