#endif
template <class Impl>
-AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(params)
+AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(this, params)
{
DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n");
this->thread[i]->setFuncExeInst(0);
}
- // Sets CPU pointers. These must be set at this level because the CPU
- // pointers are defined to be the highest level of CPU class.
- this->fetch.setCPU(this);
- this->decode.setCPU(this);
- this->rename.setCPU(this);
- this->iew.setCPU(this);
- this->commit.setCPU(this);
-
- this->rob.setCPU(this);
- this->regFile.setCPU(this);
-
lockAddr = 0;
lockFlag = false;
}
public:
/** Construct a DefaultCommit with the given parameters. */
- DefaultCommit(Params *params);
+ DefaultCommit(O3CPU *_cpu, Params *params);
/** Returns the name of the DefaultCommit. */
std::string name() const;
/** Registers statistics. */
void regStats();
- /** Sets the CPU pointer. */
- void setCPU(O3CPU *cpu_ptr);
-
/** Sets the list of threads. */
void setThreads(std::vector<Thread *> &threads);
}
template <class Impl>
-DefaultCommit<Impl>::DefaultCommit(Params *params)
- : squashCounter(0),
+DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
+ : cpu(_cpu),
+ squashCounter(0),
iewToCommitDelay(params->iewToCommitDelay),
commitToIEWDelay(params->commitToIEWDelay),
renameToROBDelay(params->renameToROBDelay),
if (policy == "aggressive"){
commitPolicy = Aggressive;
-// DPRINTF(Commit,"Commit Policy set to Aggressive.");
+ DPRINTF(Commit,"Commit Policy set to Aggressive.");
} else if (policy == "roundrobin"){
commitPolicy = RoundRobin;
priority_list.push_back(tid);
}
-// DPRINTF(Commit,"Commit Policy set to Round Robin.");
+ DPRINTF(Commit,"Commit Policy set to Round Robin.");
} else if (policy == "oldestready"){
commitPolicy = OldestReady;
-// DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
+ DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
} else {
assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
"RoundRobin,OldestReady}");
;
}
-template <class Impl>
-void
-DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
-{
- cpu = cpu_ptr;
- DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
-
- // Commit must broadcast the number of free entries it has at the start of
- // the simulation, so it starts as active.
- cpu->activateStage(O3CPU::CommitIdx);
-
- trapLatency = cpu->cycles(trapLatency);
-}
-
template <class Impl>
void
DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
toIEW->commitInfo[i].emptyROB = true;
}
+ // Commit must broadcast the number of free entries it has at the
+ // start of the simulation, so it starts as active.
+ cpu->activateStage(O3CPU::CommitIdx);
+
cpu->activityThisCycle();
+ trapLatency = cpu->cycles(trapLatency);
}
template <class Impl>
}
template <class Impl>
-FullO3CPU<Impl>::FullO3CPU(Params *params)
+FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
: BaseO3CPU(params),
#if FULL_SYSTEM
itb(params->itb),
#endif
tickEvent(this),
removeInstsThisCycle(false),
- fetch(params),
- decode(params),
- rename(params),
- iew(params),
- commit(params),
+ fetch(o3_cpu, params),
+ decode(o3_cpu, params),
+ rename(o3_cpu, params),
+ iew(o3_cpu, params),
+ commit(o3_cpu, params),
- regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
+ regFile(o3_cpu, params->numPhysIntRegs,
+ params->numPhysFloatRegs),
freeList(params->numberOfThreads,
TheISA::NumIntRegs, params->numPhysIntRegs,
TheISA::NumFloatRegs, params->numPhysFloatRegs),
- rob(params->numROBEntries, params->squashWidth,
+ rob(o3_cpu,
+ params->numROBEntries, params->squashWidth,
params->smtROBPolicy, params->smtROBThreshold,
params->numberOfThreads),
typedef typename Impl::CPUPol CPUPolicy;
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::O3CPU O3CPU;
typedef O3ThreadState<Impl> Thread;
public:
/** Constructs a CPU with the given parameters. */
- FullO3CPU(Params *params);
+ FullO3CPU(O3CPU *o3_cpu, Params *params);
/** Destructor. */
~FullO3CPU();
public:
/** DefaultDecode constructor. */
- DefaultDecode(Params *params);
+ DefaultDecode(O3CPU *_cpu, Params *params);
/** Returns the name of decode. */
std::string name() const;
/** Registers statistics. */
void regStats();
- /** Sets CPU pointer. */
- void setCPU(O3CPU *cpu_ptr);
-
/** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
#include "cpu/o3/decode.hh"
template<class Impl>
-DefaultDecode<Impl>::DefaultDecode(Params *params)
- : renameToDecodeDelay(params->renameToDecodeDelay),
+DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, Params *params)
+ : cpu(_cpu),
+ renameToDecodeDelay(params->renameToDecodeDelay),
iewToDecodeDelay(params->iewToDecodeDelay),
commitToDecodeDelay(params->commitToDecodeDelay),
fetchToDecodeDelay(params->fetchToDecodeDelay),
.prereq(decodeSquashedInsts);
}
-template<class Impl>
-void
-DefaultDecode<Impl>::setCPU(O3CPU *cpu_ptr)
-{
- cpu = cpu_ptr;
- DPRINTF(Decode, "Setting CPU pointer.\n");
-}
-
template<class Impl>
void
DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
public:
/** DefaultFetch constructor. */
- DefaultFetch(Params *params);
+ DefaultFetch(O3CPU *_cpu, Params *params);
/** Returns the name of fetch. */
std::string name() const;
/** Returns the icache port. */
Port *getIcachePort() { return icachePort; }
- /** Sets CPU pointer. */
- void setCPU(O3CPU *cpu_ptr);
-
/** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
}
template<class Impl>
-DefaultFetch<Impl>::DefaultFetch(Params *params)
- : branchPred(params),
+DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
+ : cpu(_cpu),
+ branchPred(params),
predecoder(NULL),
decodeToFetchDelay(params->decodeToFetchDelay),
renameToFetchDelay(params->renameToFetchDelay),
// Get the size of an instruction.
instSize = sizeof(TheISA::MachInst);
+
+ // Name is finally available, so create the port.
+ icachePort = new IcachePort(this);
+
+ icachePort->snoopRangeSent = false;
+
+#if USE_CHECKER
+ if (cpu->checker) {
+ cpu->checker->setIcachePort(icachePort);
+ }
+#endif
}
template <class Impl>
branchPred.regStats();
}
-template<class Impl>
-void
-DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
-{
- cpu = cpu_ptr;
- DPRINTF(Fetch, "Setting the CPU pointer.\n");
-
- // Name is finally available, so create the port.
- icachePort = new IcachePort(this);
-
- icachePort->snoopRangeSent = false;
-
-#if USE_CHECKER
- if (cpu->checker) {
- cpu->checker->setIcachePort(icachePort);
- }
-#endif
-
- // Schedule fetch to get the correct PC from the CPU
- // scheduleFetchStartupEvent(1);
-
- // Fetch needs to start fetching instructions at the very beginning,
- // so it must start up in active state.
- switchToActive();
-}
-
template<class Impl>
void
DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
stalls[tid].iew = false;
stalls[tid].commit = false;
}
+
+ // Schedule fetch to get the correct PC from the CPU
+ // scheduleFetchStartupEvent(1);
+
+ // Fetch needs to start fetching instructions at the very beginning,
+ // so it must start up in active state.
+ switchToActive();
}
template<class Impl>
public:
/** Constructs a DefaultIEW with the given parameters. */
- DefaultIEW(Params *params);
+ DefaultIEW(O3CPU *_cpu, Params *params);
/** Returns the name of the DefaultIEW stage. */
std::string name() const;
/** Returns the dcache port. */
Port *getDcachePort() { return ldstQueue.getDcachePort(); }
- /** Sets CPU pointer for IEW, IQ, and LSQ. */
- void setCPU(O3CPU *cpu_ptr);
-
/** Sets main time buffer used for backwards communication. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
/** Scoreboard pointer. */
Scoreboard* scoreboard;
- public:
- /** Instruction queue. */
- IQ instQueue;
-
- /** Load / store queue. */
- LSQ ldstQueue;
-
- /** Pointer to the functional unit pool. */
- FUPool *fuPool;
-
private:
/** CPU pointer. */
O3CPU *cpu;
void printAvailableInsts();
public:
+ /** Instruction queue. */
+ IQ instQueue;
+
+ /** Load / store queue. */
+ LSQ ldstQueue;
+
+ /** Pointer to the functional unit pool. */
+ FUPool *fuPool;
/** Records if the LSQ needs to be updated on the next cycle, so that
* IEW knows if there will be activity on the next cycle.
*/
#include "cpu/o3/iew.hh"
template<class Impl>
-DefaultIEW<Impl>::DefaultIEW(Params *params)
+DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params)
: issueToExecQueue(params->backComSize, params->forwardComSize),
- instQueue(params),
- ldstQueue(params),
+ cpu(_cpu),
+ instQueue(_cpu, this, params),
+ ldstQueue(_cpu, this, params),
fuPool(params->fuPool),
commitToIEWDelay(params->commitToIEWDelay),
renameToIEWDelay(params->renameToIEWDelay),
// Instruction queue needs the queue between issue and execute.
instQueue.setIssueToExecuteQueue(&issueToExecQueue);
- instQueue.setIEW(this);
- ldstQueue.setIEW(this);
-
for (int i=0; i < numThreads; i++) {
dispatchStatus[i] = Running;
stalls[i].commit = false;
toRename->iewInfo[tid].freeLSQEntries =
ldstQueue.numFreeEntries(tid);
}
-}
-
-template<class Impl>
-void
-DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
-{
- cpu = cpu_ptr;
- DPRINTF(IEW, "Setting CPU pointer.\n");
-
- instQueue.setCPU(cpu_ptr);
- ldstQueue.setCPU(cpu_ptr);
cpu->activateStage(O3CPU::IEWIdx);
}
};
/** Constructs an IQ. */
- InstructionQueue(Params *params);
+ InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params);
/** Destructs the IQ. */
~InstructionQueue();
/** Resets all instruction queue state. */
void resetState();
- /** Sets CPU pointer. */
- void setCPU(O3CPU *_cpu) { cpu = _cpu; }
-
/** Sets active threads list. */
void setActiveThreads(std::list<unsigned> *at_ptr);
- /** Sets the IEW pointer. */
- void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
-
/** Sets the timer buffer between issue and execute. */
void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
}
template <class Impl>
-InstructionQueue<Impl>::InstructionQueue(Params *params)
- : fuPool(params->fuPool),
+InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
+ Params *params)
+ : cpu(cpu_ptr),
+ iewStage(iew_ptr),
+ fuPool(params->fuPool),
numEntries(params->numIQEntries),
totalWidth(params->issueWidth),
numPhysIntRegs(params->numPhysIntRegs),
maxEntries[i] = part_amt;
}
-/*
DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
"%i entries per thread.\n",part_amt);
-*/
-
} else if (policy == "threshold") {
iqPolicy = Threshold;
maxEntries[i] = thresholdIQ;
}
-/*
DPRINTF(IQ, "IQ sharing policy set to Threshold:"
"%i entries per thread.\n",thresholdIQ);
-*/
} else {
assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
"Partitioned, Threshold}");
};
/** Constructs an LSQ with the given parameters. */
- LSQ(Params *params);
+ LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params);
/** Returns the name of the LSQ. */
std::string name() const;
/** Sets the pointer to the list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
- /** Sets the CPU pointer. */
- void setCPU(O3CPU *cpu_ptr);
- /** Sets the IEW stage pointer. */
- void setIEW(IEW *iew_ptr);
/** Switches out the LSQ. */
void switchOut();
/** Takes over execution from another CPU's thread. */
template <class T>
Fault write(RequestPtr req, T &data, int store_idx);
+ /** The CPU pointer. */
+ O3CPU *cpu;
+
+ /** The IEW stage pointer. */
+ IEW *iewStage;
+
/** DcachePort class for this LSQ. Handles doing the
* communication with the cache/memory.
*/
public:
/** Default constructor. */
DcachePort(LSQ *_lsq)
- : lsq(_lsq)
+ : Port(_lsq->name() + "-dport"), lsq(_lsq)
{ }
bool snoopRangeSent;
/** The LSQ units for individual threads. */
LSQUnit thread[Impl::MaxThreads];
- /** The CPU pointer. */
- O3CPU *cpu;
-
- /** The IEW stage pointer. */
- IEW *iewStage;
-
/** List of Active Threads in System. */
std::list<unsigned> *activeThreads;
}
template <class Impl>
-LSQ<Impl>::LSQ(Params *params)
- : dcachePort(this), LQEntries(params->LQEntries),
- SQEntries(params->SQEntries), numThreads(params->numberOfThreads),
+LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params)
+ : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this),
+ LQEntries(params->LQEntries),
+ SQEntries(params->SQEntries),
+ numThreads(params->numberOfThreads),
retryTid(-1)
{
dcachePort.snoopRangeSent = false;
maxLQEntries = LQEntries;
maxSQEntries = SQEntries;
-/*
+
DPRINTF(LSQ, "LSQ sharing policy set to Dynamic\n");
-*/
} else if (policy == "partitioned") {
lsqPolicy = Partitioned;
//@todo:make work if part_amt doesnt divide evenly.
maxLQEntries = LQEntries / numThreads;
maxSQEntries = SQEntries / numThreads;
-/*
+
DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: "
"%i entries per LQ | %i entries per SQ",
maxLQEntries,maxSQEntries);
-*/
} else if (policy == "threshold") {
lsqPolicy = Threshold;
//amount of the LSQ
maxLQEntries = params->smtLSQThreshold;
maxSQEntries = params->smtLSQThreshold;
-/*
+
DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
"%i entries per LQ | %i entries per SQ",
maxLQEntries,maxSQEntries);
-*/
-
} else {
assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
"Partitioned, Threshold}");
//Initialize LSQs
for (int tid=0; tid < numThreads; tid++) {
- thread[tid].init(params, this, maxLQEntries, maxSQEntries, tid);
+ thread[tid].init(cpu, iew_ptr, params, this,
+ maxLQEntries, maxSQEntries, tid);
thread[tid].setDcachePort(&dcachePort);
}
}
assert(activeThreads != 0);
}
-template<class Impl>
-void
-LSQ<Impl>::setCPU(O3CPU *cpu_ptr)
-{
- cpu = cpu_ptr;
-
- dcachePort.setName(name());
-
- for (int tid=0; tid < numThreads; tid++) {
- thread[tid].setCPU(cpu_ptr);
- }
-}
-
-template<class Impl>
-void
-LSQ<Impl>::setIEW(IEW *iew_ptr)
-{
- iewStage = iew_ptr;
-
- for (int tid=0; tid < numThreads; tid++) {
- thread[tid].setIEW(iew_ptr);
- }
-}
-
template <class Impl>
void
LSQ<Impl>::switchOut()
LSQUnit();
/** Initializes the LSQ unit with the specified number of entries. */
- void init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
- unsigned maxSQEntries, unsigned id);
+ void init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
+ unsigned maxLQEntries, unsigned maxSQEntries, unsigned id);
/** Returns the name of the LSQ unit. */
std::string name() const;
/** Registers statistics. */
void regStats();
- /** Sets the CPU pointer. */
- void setCPU(O3CPU *cpu_ptr);
-
- /** Sets the IEW stage pointer. */
- void setIEW(IEW *iew_ptr)
- { iewStage = iew_ptr; }
-
/** Sets the pointer to the dcache port. */
- void setDcachePort(Port *dcache_port)
- { dcachePort = dcache_port; }
+ void setDcachePort(Port *dcache_port);
/** Switches out LSQ unit. */
void switchOut();
template<class Impl>
void
-LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
- unsigned maxSQEntries, unsigned id)
+LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
+ unsigned maxLQEntries, unsigned maxSQEntries, unsigned id)
{
-// DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
+ cpu = cpu_ptr;
+ iewStage = iew_ptr;
+
+ DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
switchedOut = false;
blockedLoadSeqNum = 0;
}
-template<class Impl>
-void
-LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
-{
- cpu = cpu_ptr;
-
-#if USE_CHECKER
- if (cpu->checker) {
- cpu->checker->setDcachePort(dcachePort);
- }
-#endif
-}
-
template<class Impl>
std::string
LSQUnit<Impl>::name() const
.desc("Number of times an access to memory failed due to the cache being blocked");
}
+template<class Impl>
+void
+LSQUnit<Impl>::setDcachePort(Port *dcache_port)
+{
+ dcachePort = dcache_port;
+
+#if USE_CHECKER
+ if (cpu->checker) {
+ cpu->checker->setDcachePort(dcachePort);
+ }
+#endif
+}
+
template<class Impl>
void
LSQUnit<Impl>::clearLQ()
* Constructs a physical register file with the specified amount of
* integer and floating point registers.
*/
- PhysRegFile(unsigned _numPhysicalIntRegs,
+ PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
unsigned _numPhysicalFloatRegs);
//Everything below should be pretty well identical to the normal
O3CPU *cpu;
public:
- /** Sets the CPU pointer. */
- void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; }
-
/** Number of physical integer registers. */
unsigned numPhysicalIntRegs;
/** Number of physical floating point registers. */
};
template <class Impl>
-PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
+PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
unsigned _numPhysicalFloatRegs)
- : numPhysicalIntRegs(_numPhysicalIntRegs),
+ : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs),
numPhysicalFloatRegs(_numPhysicalFloatRegs)
{
intRegFile = new IntReg[numPhysicalIntRegs];
public:
/** DefaultRename constructor. */
- DefaultRename(Params *params);
+ DefaultRename(O3CPU *_cpu, Params *params);
/** Returns the name of rename. */
std::string name() const;
/** Registers statistics. */
void regStats();
- /** Sets CPU pointer. */
- void setCPU(O3CPU *cpu_ptr);
-
/** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
#include "cpu/o3/rename.hh"
template <class Impl>
-DefaultRename<Impl>::DefaultRename(Params *params)
- : iewToRenameDelay(params->iewToRenameDelay),
+DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
+ : cpu(_cpu),
+ iewToRenameDelay(params->iewToRenameDelay),
decodeToRenameDelay(params->decodeToRenameDelay),
commitToRenameDelay(params->commitToRenameDelay),
renameWidth(params->renameWidth),
;
}
-template <class Impl>
-void
-DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr)
-{
- cpu = cpu_ptr;
- DPRINTF(Rename, "Setting CPU pointer.\n");
-}
-
template <class Impl>
void
DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
* @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB.
* @param _numThreads The number of active threads.
*/
- ROB(unsigned _numEntries, unsigned _squashWidth, std::string smtROBPolicy,
- unsigned _smtROBThreshold, unsigned _numThreads);
+ ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
+ std::string smtROBPolicy, unsigned _smtROBThreshold,
+ unsigned _numThreads);
std::string name() const;
- /** Function to set the CPU pointer, necessary due to which object the ROB
- * is created within.
- * @param cpu_ptr Pointer to the implementation specific full CPU object.
- */
- void setCPU(O3CPU *cpu_ptr);
-
/** Sets pointer to the list of active threads.
* @param at_ptr Pointer to the list of active threads.
*/
#include <list>
template <class Impl>
-ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
+ROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
std::string _smtROBPolicy, unsigned _smtROBThreshold,
unsigned _numThreads)
- : numEntries(_numEntries),
+ : cpu(_cpu),
+ numEntries(_numEntries),
squashWidth(_squashWidth),
numInstsInROB(0),
numThreads(_numThreads)
} else if (policy == "partitioned") {
robPolicy = Partitioned;
-// DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
+ DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
//@todo:make work if part_amt doesnt divide evenly.
int part_amt = numEntries / numThreads;
} else if (policy == "threshold") {
robPolicy = Threshold;
-// DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
+ DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
int threshold = _smtROBThreshold;;
assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
"Partitioned, Threshold}");
}
-}
-
-template <class Impl>
-std::string
-ROB<Impl>::name() const
-{
- return cpu->name() + ".rob";
-}
-
-template <class Impl>
-void
-ROB<Impl>::setCPU(O3CPU *cpu_ptr)
-{
- cpu = cpu_ptr;
// Set the per-thread iterators to the end of the instruction list.
for (int i=0; i < numThreads;i++) {
tail = instList[0].end();
}
+template <class Impl>
+std::string
+ROB<Impl>::name() const
+{
+ return cpu->name() + ".rob";
+}
+
template <class Impl>
void
ROB<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
projects / gem5.git / commitdiff