gallium/radeon: add depth/stencil_adjusted output to surface computation

This fixes a rare bug with stencil texturing -- seen on Polaris and Tonga,
though it's basically a function of the memory configuration so could affect
other parts as well.

Fixes piglit "unaligned-blit * stencil downsample" and various
"fbo-depth-array *stencil*" tests.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 434bd44fbbb7a19fcc60b644e7ba6e40cc825d43..7763f812141c96eb6d5453cd94eda7fa3f33d10f 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1030,8 +1030,8 @@ r600_texture_create_object(struct pipe_screen *screen,
                if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
                                   R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
                    rscreen->chip_class >= EVERGREEN) {
-                       rtex->can_sample_z = true;
-                       rtex->can_sample_s = true;
+                       rtex->can_sample_z = !rtex->surface.depth_adjusted;
+                       rtex->can_sample_s = !rtex->surface.stencil_adjusted;
                } else {
                        if (rtex->resource.b.b.nr_samples <= 1 &&
                            (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 0bf6fd9753732aeed64e7e5d981f2ed2bb8f6fcf..de25e19aa5b4559d673dedca4e79de2aecefd319 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -401,6 +401,14 @@ struct radeon_surf {
     uint32_t                    macro_tile_index;
     uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 
+    /* Whether the depth miptree or stencil miptree as used by the DB are
+     * adjusted from their TC compatible form to ensure depth/stencil
+     * compatibility. If either is true, the corresponding plane cannot be
+     * sampled from.
+     */
+    bool                        depth_adjusted;
+    bool                        stencil_adjusted;
+
     uint64_t                    dcc_size;
     uint64_t                    dcc_alignment;
 };

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index dd033e087e0a86e42e8a77f98af2b9617572f8d8..cafa75da0b4ace76e71dd28465ffb9be3bda88a0 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -454,6 +454,10 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
          if (r)
             return r;
 
+         /* DB uses the depth pitch for both stencil and depth. */
+         if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
+            surf->stencil_adjusted = true;
+
          if (level == 0) {
             /* For 2D modes only. */
             if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {