---------- Begin Simulation Statistics ----------
-host_inst_rate 632486 # Simulator instruction rate (inst/s)
-host_mem_usage 213180 # Number of bytes of host memory used
-host_seconds 346.62 # Real time elapsed on the host
-host_tick_rate 723985351 # Simulator tick rate (ticks/s)
+host_inst_rate 489241 # Simulator instruction rate (inst/s)
+host_mem_usage 228040 # Number of bytes of host memory used
+host_seconds 448.51 # Real time elapsed on the host
+host_tick_rate 559541126 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 219230323 # Number of instructions simulated
-sim_seconds 0.250946 # Number of seconds simulated
-sim_ticks 250945548000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses)
+sim_insts 219430973 # Number of instructions simulated
+sim_seconds 0.250962 # Number of seconds simulated
+sim_ticks 250961789000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 56682001 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 56649281 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits 56681682 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses
system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 40758.097149 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 77197730 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 77163409 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 77195810 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 77197730 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 77163409 # number of overall hits
+system.cpu.dcache.overall_hits 77195810 # number of overall hits
system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1920 # number of overall misses
system.cpu.dcache.replacements 27 # number of replacements
system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1362.582602 # Cycle average of tags in use
-system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1362.582472 # Cycle average of tags in use
+system.cpu.dcache.total_refs 77195836 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2 # number of writebacks
system.cpu.icache.ReadReq_accesses 173494375 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 39412.334896 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 36412.228377 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 39420.962931 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.252237 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 173489681 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 185001500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 185042000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 170919000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 170928500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 173494375 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 39412.334896 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 36412.228377 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 39420.962931 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 36414.252237 # average overall mshr miss latency
system.cpu.icache.demand_hits 173489681 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 185001500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 185042000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 170919000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 170928500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 173494375 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 39412.334896 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 36412.228377 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 39420.962931 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 36414.252237 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 173489681 # number of overall hits
-system.cpu.icache.overall_miss_latency 185001500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 185042000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
system.cpu.icache.overall_misses 4694 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 170919000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 170928500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 2836 # number of replacements
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1455.283981 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1455.283776 # Cycle average of tags in use
system.cpu.icache.total_refs 173489681 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 5013 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52002.058265 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52005.066498 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 164222500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 164232000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.629962 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3158 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 126320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 6588 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52001.373336 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52003.380520 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 246122500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 246132000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.718427 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4733 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 6588 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52001.373336 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52003.380520 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1855 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 246122500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 246132000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.718427 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4733 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3134 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2033.146717 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2033.146295 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 501891096 # number of cpu cycles simulated
-system.cpu.num_insts 219230323 # Number of instructions executed
+system.cpu.numCycles 501923578 # number of cpu cycles simulated
+system.cpu.num_insts 219430973 # Number of instructions executed
system.cpu.num_refs 77165298 # Number of memory references
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
projects / gem5.git / commitdiff