(no commit message)

diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
index cb41c9191f4b99137541c0120f9ae9d550c7b51f..5def4fb1f85217623bf79f00b0fa1b9878264906 100644 (file)
--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -1,8 +1,8 @@
 # Simple-V (Parallelism Extension Proposal) Vector Block Format
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton
-* Status: DRAFTv0.6
-* Last edited: 13 aug 2019
+* Status: DRAFTv0.7
+* Last edited: 30 aug 2019
 
 [[!toc ]]
 
@@ -191,7 +191,7 @@ The format is as follows:
 
 | 31:30  | 29    | 28:26 | 25:24 | 23:22 | 21   | 20:5  | 4:0   |
 |--------|-------|-------|-------|-------|------|-------|-------|
-| status | vlset | 16xil | pplen | rplen | mode | vlblk | opptr |
+| status | vlset | 16xil | pplen | rplen | mode | vblock2 | opptr |
 | 2      | 1     | 3     | 2     | 2     | 1    | 16    | 5     |
 
 * status is the key field that effectively exposes the inner FSM (Finite
@@ -202,18 +202,23 @@ The format is as follows:
   VBLOCK opcode.
 * status = 0b01 indicates that vlset, 16xil, pplen, rplen and mode have
   all been copied directly from the VBLOCK so that they do not need to be
-  read again from the instruction stream.
+  read again from the instruction stream,
+  and that VBLOCK2 has also been read and stored,  if 16xil was
+  equal to 0b111.
 * status=0b10 indicates that the VL Block has been read from the
-  instruction stream and decoded (and copied into vlblk).
+  instruction stream and actioned.
+  (This means that a SETVL instruction has been created and executed).
 * status=0b11 indicates that the Predicate and Register Blocks have been
   read from the instruction stream (and put into internal Vector Context)
   Simpler implementations are permitted to reset status back to 0b10 and
   re-read the data after return from a trap that happened to occur in the
   middle of a VBLOCK. They are not however permitted to destroy opptr in
   the process, and after re-reading the Predicate and Register Blocks must
-  resume execution pointed to by  opptr.
+  resume execution pointed to by opptr.
 * opptr points to where instructions begin in the VBLOCK. 0 indicates
-  the start of the opcodes, and is in multiples of 16 bits (2 bytes).
+  the start of the opcodes
+  (not the start of the VBLOCK),
+  and is in multiples of 16 bits (2 bytes).
   This is the equivalent of a Program Counter, for VBLOCKs.
 * at the end of a VBLOCK, when the last instruction executes (assuming it
   does not change opptr to earlier in the block), status is reset to 0b00