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fixedlogical: simplify extsw
authorDmitry Selyutin <dmitry.selyutin@3mdeb.com>
Sat, 2 Oct 2021 09:23:42 +0000 (09:23 +0000)
committerDmitry Selyutin <dmitry.selyutin@3mdeb.com>
Wed, 13 Oct 2021 18:08:44 +0000 (18:08 +0000)
openpower/isa/fixedlogical.mdwn patch | blob | history

diff --git a/openpower/isa/fixedlogical.mdwn b/openpower/isa/fixedlogical.mdwn
index 5162dbd488744e66b2bc1765889f40c8def163a3..b1332fe8cb5de07d1e01e27796d1c55a20997abd 100644 (file)
--- a/openpower/isa/fixedlogical.mdwn
+++ b/openpower/isa/fixedlogical.mdwn
@@ -389,9 +389,7 @@ X-Form
 
 Pseudo-code:
 
-    s <- (RS)[XLEN/2]
-    RA[XLEN/2:XLEN-1] <- (RS)[XLEN/2:XLEN-1]
-    RA[0:(XLEN/2)-1] <- [s]*(XLEN/2)
+    RA <- EXTSXL(RS, 32)
 
 Special Registers Altered: