backport wishbone_bram_wrapper changes

diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl
index 51a44677088d3d2e85915b32ca19b6389065672e..9a0358b07114ad8951687f121c747ec8a65858b0 100644 (file)
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@@ -7,6 +7,8 @@ library work;
 use work.utils.all;
 use work.wishbone_types.all;
 
+--- verilator access TODO
+
 --! @brief Simple memory module for use in Wishbone-based systems.
 entity wishbone_bram_wrapper is
     generic(
@@ -26,15 +28,15 @@ entity wishbone_bram_wrapper is
     bram_we : out std_ulogic;
     bram_re : out std_ulogic;
     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
-    bram_di   : inout std_logic_vector(63 downto 0);
-    bram_do   : out std_logic_vector(63 downto 0);
+    bram_di   : out std_logic_vector(63 downto 0);
+    bram_do   : in std_logic_vector(63 downto 0);
     bram_sel  : out std_logic_vector(7 downto 0)
 
        );
 end entity wishbone_bram_wrapper;
 
 architecture behaviour of wishbone_bram_wrapper is
-    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3;
+    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
 
     -- RAM interface
     signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
@@ -46,6 +48,7 @@ architecture behaviour of wishbone_bram_wrapper is
 begin
 
     -- Actual RAM template
+    sim_ram: if SIM_MAIN_BRAM = true generate
     ram_0: entity work.main_bram
        generic map(
            WIDTH => 64,
@@ -62,6 +65,15 @@ begin
            re => ram_re,
            we => ram_we
            );
+       end generate;
+           
+       -- Verilator access to bram signals
+    bram_sel <= wishbone_in.sel;
+    wishbone_out.dat <= bram_do;
+    bram_di <= wishbone_in.dat;
+    bram_addr <= ram_addr;
+    bram_we <= ram_we;
+    bram_re <= ram_re;
 
     -- Wishbone interface
     ram_addr <= wishbone_in.adr(ram_addr_bits - 1 downto 0);