use new EndpointDescription

diff --git a/lib/sata/phy/k7sataphy/ctrl.py b/lib/sata/phy/k7sataphy/ctrl.py
index 3c840d065d5153870b49f03c1f9b5285b011b015..3179416d9107e27836cf6f59e8b568813703e8e2 100644 (file)
--- a/lib/sata/phy/k7sataphy/ctrl.py
+++ b/lib/sata/phy/k7sataphy/ctrl.py
@@ -15,8 +15,8 @@ class K7SATAPHYHostCtrl(Module):
        def __init__(self, gtx, crg, clk_freq):
                self.ready = Signal()
 
-               self.sink = Sink([("data", 32), ("charisk", 4)])
-               self.source = Source([("data", 32), ("charisk", 4)])
+               self.sink = Sink(phy_description(32))
+               self.source = Source(phy_description(32))
 
                self.align_detect = align_detect = Signal()
                align_timeout_cnt = Signal(32)
@@ -171,8 +171,8 @@ class K7SATAPHYDeviceCtrl(Module):
        def __init__(self, gtx, crg, clk_freq):
                self.ready = Signal()
 
-               self.sink = Sink([("data", 32), ("charisk", 4)])
-               self.source = Source([("data", 32), ("charisk", 4)])
+               self.sink = Sink(phy_description(32))
+               self.source = Source(phy_description(32))
 
                align_detect = Signal()
                align_timeout = Signal()

diff --git a/lib/sata/phy/k7sataphy/datapath.py b/lib/sata/phy/k7sataphy/datapath.py
index bd4b6670992540dae1dbd14fa302474d7b779340..922c1f32089c45edb3a80b998c8b41abdb193ecc 100644 (file)
--- a/lib/sata/phy/k7sataphy/datapath.py
+++ b/lib/sata/phy/k7sataphy/datapath.py
@@ -7,8 +7,8 @@ from lib.sata.std import *
 
 class K7SATAPHYDatapathRX(Module):
        def __init__(self):
-               self.sink = Sink([("data", 16), ("charisk", 2)])
-               self.source = Source([("data", 32), ("charisk", 4)])
+               self.sink = Sink(phy_description(16))
+               self.source = Source(phy_description(32))
 
                ###
 
@@ -60,7 +60,7 @@ class K7SATAPHYDatapathRX(Module):
                # requirements:
                # due to the convertion ratio of 2, sys_clk need to be > sata_rx/2
                # source destination is always able to accept data (ack always 1)
-               fifo = AsyncFIFO([("data", 32), ("charisk", 4)], 16)
+               fifo = AsyncFIFO(phy_description(32), 16)
                self.submodules.fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"})
                self.comb += [
                        fifo.sink.stb.eq(valid),
@@ -71,8 +71,8 @@ class K7SATAPHYDatapathRX(Module):
 
 class K7SATAPHYDatapathTX(Module):
        def __init__(self):
-               self.sink = Sink([("data", 32), ("charisk", 4)])
-               self.source = Source([("data", 16), ("charisk", 2)])
+               self.sink = Sink(phy_description(32))
+               self.source = Source(phy_description(16))
 
                ###
 
@@ -82,7 +82,7 @@ class K7SATAPHYDatapathTX(Module):
                # (SATA1) sys_clk to 75MHz sata_tx clk
                # requirements:
                # source destination is always able to accept data (ack always 1)
-               fifo = AsyncFIFO([("data", 32), ("charisk", 4)], 16)
+               fifo = AsyncFIFO(phy_description(32), 16)
                self.submodules.fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"})
                self.comb += Record.connect(self.sink, fifo.sink)
 
@@ -110,8 +110,8 @@ class K7SATAPHYDatapathTX(Module):
 
 class K7SATAPHYDatapath(Module):
        def __init__(self, gtx, ctrl):
-               self.sink = Sink([("data", 32), ("charisk", 4)])
-               self.source = Source([("data", 32), ("charisk", 4)])
+               self.sink = Sink(phy_description(32))
+               self.source = Source(phy_description(32))
 
                ###
 

diff --git a/lib/sata/std.py b/lib/sata/std.py
index 7979b38a74e2ac76bc3a386257f8b9263f768584..a6d4c028246e1753af23c1be74d38fb696b03cde 100644 (file)
--- a/lib/sata/std.py
+++ b/lib/sata/std.py
@@ -1,5 +1,6 @@
 from migen.fhdl.std import *
 from migen.genlib.record import *
+from migen.flow.actor import EndpointDescription
 
 primitives = {
        "ALIGN" :       0x7B4A4ABC,
@@ -20,16 +21,22 @@ primitives = {
 def ones(width):
        return 2**width-1
 
-def phy_layout(dw):
+def phy_description(dw):
+       parameters = {
+               "packetized": False
+       }
        layout = [
-               ("p_packetized", True),
-               ("d", dw)
+               ("data", dw),
+               ("charisk", dw//8),
        ]
-       return layout
+       return EndpointDescription(layout, parameters)
 
-def link_layout(dw):
+def link_description(dw):
+       parameters = {
+               "packetized": True
+       }
        layout = [
-               ("p_packetized", True),
-               ("d", dw)
+               ("d", dw),
+               ("error", 1)
        ]
-       return layout
+       return EndpointDescription(layout, parameters)