#define CPP_PREDEFINES "-D__mn10300__ -D__MN10300__"
+#define CPP_SPEC "%{mam33:-D__AM33__}"
+
/* Run-time compilation parameters selecting different hardware subsets. */
extern int target_flags;
/* Generate code to work around mul/mulq bugs on the mn10300. */
#define TARGET_MULT_BUG (target_flags & 0x1)
+
+/* Generate code for the AM33 processor. */
+#define TARGET_AM33 (target_flags & 0x2)
+
#define TARGET_SWITCHES \
{{ "mult-bug", 0x1, "Work around hardware multiply bug"}, \
{ "no-mult-bug", -0x1, "Do not work around hardware multiply bug"},\
+ { "am33", 0x2}, \
+ { "am33", -(0x1)},\
+ { "no-am33", -0x2}, \
{ "", TARGET_DEFAULT, NULL}}
#ifndef TARGET_DEFAULT
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers. */
-#define FIRST_PSEUDO_REGISTER 10
+#define FIRST_PSEUDO_REGISTER 18
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */
#define FIXED_REGISTERS \
- { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1}
+ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
like. */
#define CALL_USED_REGISTERS \
- { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1}
+ { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0}
#define REG_ALLOC_ORDER \
- { 0, 1, 4, 5, 2, 3, 6, 7, 8, 9}
+ { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9}
+
+#define CONDITIONAL_REGISTER_USAGE \
+{ \
+ if (!TARGET_AM33) \
+ { \
+ for (i = 10; i < 18; i++) \
+ fixed_regs[i] = call_used_regs[i] = 1; \
+ } \
+}
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (REGNO_REG_CLASS (REGNO) == DATA_REGS \
+ ((REGNO_REG_CLASS (REGNO) == DATA_REGS \
+ || (TARGET_AM33 && REGNO_REG_CLASS (REGNO) == ADDRESS_REGS) \
+ || REGNO_REG_CLASS (REGNO) == EXTENDED_REGS) \
? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4 \
: ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
- (MODE1 == MODE2 || (GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4))
+ (TARGET_AM33 \
+ || MODE1 == MODE2 \
+ || (GET_MODE_SIZE (MODE1) <= 4 && GET_MODE_SIZE (MODE2) <= 4))
/* 4 data, and effectively 3 address registers is small as far as I'm
concerned. */
enum reg_class {
NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
+ EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS,
+ SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS,
GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
};
#define REG_CLASS_NAMES \
{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
"SP_REGS", "DATA_OR_ADDRESS_REGS", "SP_OR_ADDRESS_REGS", \
+ "EXTENDED_REGS", \
+ "DATA_OR_EXTENDED_REGS", "ADDRESS_OR_EXTENDED_REGS", \
+ "SP_OR_EXTENDED_REGS", "SP_OR_ADDRESS_OR_EXTENDED_REGS", \
"GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
/* Define which registers fit in which classes.
#define REG_CLASS_CONTENTS \
{ 0, /* No regs */ \
- 0x00f, /* DATA_REGS */ \
- 0x1f0, /* ADDRESS_REGS */ \
- 0x200, /* SP_REGS */ \
- 0x1ff, /* DATA_OR_ADDRESS_REGS */\
- 0x1f0, /* SP_OR_ADDRESS_REGS */\
- 0x1ff, /* GENERAL_REGS */ \
- 0x3ff, /* ALL_REGS */ \
+ 0x0000f, /* DATA_REGS */ \
+ 0x001f0, /* ADDRESS_REGS */ \
+ 0x00200, /* SP_REGS */ \
+ 0x001ff, /* DATA_OR_ADDRESS_REGS */\
+ 0x003f0, /* SP_OR_ADDRESS_REGS */\
+ 0x2fc00, /* EXTENDED_REGS */ \
+ 0x2fc0f, /* DATA_OR_EXTENDED_REGS */ \
+ 0x2fdf0, /* ADDRESS_OR_EXTENDED_REGS */ \
+ 0x2fe00, /* SP_OR_EXTENDED_REGS */ \
+ 0x2fff0, /* SP_OR_ADDRESS_OR_EXTENDED_REGS */ \
+ 0x2fdff, /* GENERAL_REGS */ \
+ 0x2ffff, /* ALL_REGS */ \
}
/* The same information, inverted:
#define REGNO_REG_CLASS(REGNO) \
((REGNO) < 4 ? DATA_REGS : \
(REGNO) < 9 ? ADDRESS_REGS : \
- (REGNO) == 9 ? SP_REGS : 0)
+ (REGNO) == 9 ? SP_REGS : \
+ (REGNO) < 18 ? EXTENDED_REGS : 0)
/* The class value for index registers, and the one for base regs. */
-#define INDEX_REG_CLASS DATA_REGS
+#define INDEX_REG_CLASS DATA_OR_EXTENDED_REGS
#define BASE_REG_CLASS SP_OR_ADDRESS_REGS
/* Get reg_class from a letter such as appears in the machine description. */
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'd' ? DATA_REGS : \
(C) == 'a' ? ADDRESS_REGS : \
+ (C) == 'x' ? EXTENDED_REGS : \
(C) == 'y' ? SP_REGS : NO_REGS)
/* Macros to check register numbers against specific register classes. */
#define REGNO_OK_FOR_INDEX_P(regno) \
(((regno) >= 0 && regno < 4) \
+ || ((regno) >= 10 && regno < 18) \
+ || (reg_renumber[regno] >= 10 && reg_renumber[regno] < 18) \
|| (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4))
in some cases it is preferable to use a more restrictive class. */
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
- (X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
+ (X == stack_pointer_rtx && CLASS != SP_REGS \
+ ? ADDRESS_OR_EXTENDED_REGS : CLASS)
#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) \
- (X == stack_pointer_rtx && CLASS != SP_REGS ? ADDRESS_REGS : CLASS)
+ (X == stack_pointer_rtx && CLASS != SP_REGS \
+ ? ADDRESS_OR_EXTENDED_REGS : CLASS)
#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
- ((MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
+ (!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
secondary_reload_class(CLASS,MODE,IN)
#endif
\f
+#define HAVE_POST_INCREMENT (TARGET_AM33)
+
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
that is a valid memory address for an instruction.
The MODE argument is the machine mode for the MEM expression
goto ADDR; \
if (RTX_OK_FOR_BASE_P (X)) \
goto ADDR; \
+ if (TARGET_AM33 \
+ && GET_CODE (X) == POST_INC \
+ && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
+ && (MODE == SImode || MODE == SFmode || MODE == HImode))\
+ goto ADDR; \
if (GET_CODE (X) == PLUS) \
{ \
rtx base = 0, index = 0; \
/* Go to LABEL if ADDR (a legitimate address expression)
has an effect that depends on the machine mode it is used for. */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
+ if (GET_CODE (ADDR) == POST_INC) \
+ goto LABEL
/* Nonzero if the constant value X is a legitimate general operand.
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
case CONST_DOUBLE: \
return 8;
-
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) (CLASS1 != CLASS2 ? 4 : 2)
+#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
+ ((CLASS1 == CLASS2 && (CLASS1 == ADDRESS_REGS || CLASS1 == DATA_REGS)) ? 2 :\
+ CLASS1 == CLASS2 && CLASS1 == EXTENDED_REGS ? 6 : 4)
/* A crude cut at RTX_COSTS for the MN10300. */
This sequence is indexed by compiler's hard-register-number (see above). */
#define REGISTER_NAMES \
-{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp" }
+{ "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" }
/* Print an instruction operand X on file FILE.
look in mn10300.c for details */
operands[1] = copy_to_mode_reg (QImode, operand1);
}")
+(define_insn ""
+ [(set (match_operand:QI 0 "general_operand" "=dx,a,dx,a,dx,a,dx,a,dxa,m")
+ (match_operand:QI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dxa"))]
+ "TARGET_AM33
+ && (register_operand (operands[0], QImode)
+ || register_operand (operands[1], QImode))"
+ "*
+{
+ switch (which_alternative)
+ {
+ case 0:
+ case 1:
+ return \"nop\";
+ case 2:
+ return \"clr %0\";
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ rtx xoperands[2];
+ xoperands[0] = operands[0];
+ xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+ output_asm_insn (\"mov %1,%0\", xoperands);
+ return \"\";
+ }
+
+ if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
+ && GET_CODE (operands[1]) == CONST_INT)
+ {
+ HOST_WIDE_INT val = INTVAL (operands[1]);
+
+ if (((val & 0x80) && ! (val & 0xffffff00))
+ || ((val & 0x800000) && ! (val & 0xff000000)))
+ return \"movu %1,%0\";
+ }
+ return \"mov %1,%0\";
+ case 8:
+ case 9:
+ return \"movbu %1,%0\";
+ }
+}"
+ [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
+
(define_insn ""
[(set (match_operand:QI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m")
(match_operand:QI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))]
operands[1] = copy_to_mode_reg (HImode, operand1);
}")
+(define_insn ""
+ [(set (match_operand:HI 0 "general_operand" "=dx,a,dx,a,dx,a,dx,a,dxa,m")
+ (match_operand:HI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dxa"))]
+ "TARGET_AM33
+ && (register_operand (operands[0], HImode)
+ || register_operand (operands[1], HImode))"
+ "*
+{
+ switch (which_alternative)
+ {
+ case 0:
+ case 1:
+ return \"nop\";
+ case 2:
+ return \"clr %0\";
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ rtx xoperands[2];
+ xoperands[0] = operands[0];
+ xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+ output_asm_insn (\"mov %1,%0\", xoperands);
+ return \"\";
+ }
+
+ if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
+ && GET_CODE (operands[1]) == CONST_INT)
+ {
+ HOST_WIDE_INT val = INTVAL (operands[1]);
+
+ if (((val & 0x80) && ! (val & 0xffffff00))
+ || ((val & 0x800000) && ! (val & 0xff000000)))
+ return \"movu %1,%0\";
+ }
+ return \"mov %1,%0\";
+ case 8:
+ case 9:
+ return \"movhu %1,%0\";
+ }
+}"
+ [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
+
(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m")
(match_operand:HI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))]
output_asm_insn (\"mov %1,%0\", xoperands);
return \"\";
}
+
+ if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
+ && GET_CODE (operands[1]) == CONST_INT)
+ {
+ HOST_WIDE_INT val = INTVAL (operands[1]);
+
+ if (((val & 0x80) && ! (val & 0xffffff00))
+ || ((val & 0x800000) && ! (val & 0xff000000)))
+ return \"movu %1,%0\";
+ }
return \"mov %1,%0\";
}
}"
case 3:
case 4:
case 5:
+ if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
+ && GET_CODE (operands[1]) == CONST_INT)
+ {
+ HOST_WIDE_INT val = INTVAL (operands[1]);
+
+ if (((val & 0x80) && ! (val & 0xffffff00))
+ || ((val & 0x800000) && ! (val & 0xff000000)))
+ return \"movu %1,%0\";
+ }
return \"mov %1,%0\";
}
}"
else
output_asm_insn (\"mov %L1,%L0\", operands);
}
+ else if ((REGNO_REG_CLASS (true_regnum (operands[0]))
+ == EXTENDED_REGS)
+ && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
+ || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
+ output_asm_insn (\"movu %1,%0\", operands);
else
output_asm_insn (\"mov %L1,%L0\", operands);
|| GET_CODE (operands[1]) == CONST_DOUBLE)
&& val[0] == val[1])
output_asm_insn (\"mov %L0,%H0\", operands);
+ else if ((REGNO_REG_CLASS (true_regnum (operands[0]))
+ == EXTENDED_REGS)
+ && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
+ || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
+ output_asm_insn (\"movu %1,%0\", operands);
else
output_asm_insn (\"mov %H1,%H0\", operands);
return \"\";
else
output_asm_insn (\"mov %L1,%L0\", operands);
}
+ else if ((REGNO_REG_CLASS (true_regnum (operands[0]))
+ == EXTENDED_REGS)
+ && (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
+ || ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
+ output_asm_insn (\"movu %1,%0\", operands);
else
output_asm_insn (\"mov %L1,%L0\", operands);
|| GET_CODE (operands[1]) == CONST_DOUBLE)
&& val[0] == val[1])
output_asm_insn (\"mov %L0,%H0\", operands);
+ else if ((REGNO_REG_CLASS (true_regnum (operands[0]))
+ == EXTENDED_REGS)
+ && (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
+ || ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
+ output_asm_insn (\"movu %1,%0\", operands);
else
output_asm_insn (\"mov %H1,%H0\", operands);
return \"\";
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
+(define_insn ""
+ [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx,!a")))]
+ "TARGET_AM33"
+ "* return output_tst (operands[0], insn);"
+ [(set_attr "cc" "set_znv")])
+
(define_insn ""
[(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))]
""
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
+(define_insn ""
+ [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx,!a")))]
+ "TARGET_AM33"
+ "* return output_tst (operands[0], insn);"
+ [(set_attr "cc" "set_znv")])
+
(define_insn ""
[(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))]
""
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
-
(define_insn "cmpsi"
[(set (cc0)
(compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax")
}
}")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
+ (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
+ (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
+ "TARGET_AM33"
+ "*
+{
+ switch (which_alternative)
+ {
+ case 0:
+ case 1:
+ return \"inc %0\";
+ case 2:
+ return \"inc4 %0\";
+ case 3:
+ case 4:
+ return \"add %2,%0\";
+ case 5:
+ {
+ enum reg_class src1_class, src2_class, dst_class;
+
+ src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
+ src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
+ dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
+
+ /* I'm not sure if this can happen or not. Might as well be prepared
+ and generate the best possible code if it does happen. */
+ if (true_regnum (operands[0]) == true_regnum (operands[1]))
+ return \"add %2,%0\";
+ if (true_regnum (operands[0]) == true_regnum (operands[2]))
+ return \"add %1,%0\";
+
+ /* Catch cases where no extended register was used. These should be
+ handled just like the mn10300. */
+ if (src1_class != EXTENDED_REGS
+ && src2_class != EXTENDED_REGS
+ && dst_class != EXTENDED_REGS)
+ {
+ /* We have to copy one of the sources into the destination, then
+ add the other source to the destination.
+
+ Carefully select which source to copy to the destination; a naive
+ implementation will waste a byte when the source classes are
+ different and the destination is an address register. Selecting
+ the lowest cost register copy will optimize this sequence. */
+ if (REGNO_REG_CLASS (true_regnum (operands[1]))
+ == REGNO_REG_CLASS (true_regnum (operands[0])))
+ return \"mov %1,%0\;add %2,%0\";
+ return \"mov %2,%0\;add %1,%0\";
+ }
+
+ /* At least one register is an extended register. */
+
+ /* The three operand add instruction on the am33 is a win iff the
+ output register is an extended register, or if both source
+ registers are extended registers. */
+ if (dst_class == EXTENDED_REGS
+ || src1_class == src2_class)
+ return \"add %2,%1,%0\";
+
+ /* It is better to copy one of the sources to the destination, then
+ perform a 2 address add. The destination in this case must be
+ an address or data register and one of the sources must be an
+ extended register and the remaining source must not be an extended
+ register.
+
+ The best code for this case is to copy the extended reg to the
+ destination, then emit a two address add. */
+ if (src1_class == EXTENDED_REGS)
+ return \"mov %1,%0\;add %2,%0\";
+ return \"mov %2,%0\;add %1,%0\";
+ }
+ }
+}"
+ [(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dax,!dax")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,dax")
+ (match_operand:SI 2 "nonmemory_operand" "daxi,dax")))]
+ "TARGET_AM33"
+ "*
+{
+ if (true_regnum (operands[0]) == true_regnum (operands[1]))
+ return \"sub %2,%0\";
+ else
+ {
+ enum reg_class src1_class, src2_class, dst_class;
+
+ src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
+ src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
+ dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
+
+ /* If no extended registers are used, then the best way to handle
+ this is to copy the first source operand into the destination
+ and emit a two address subtraction. */
+ if (src1_class != EXTENDED_REGS
+ && src2_class != EXTENDED_REGS
+ && dst_class != EXTENDED_REGS
+ && true_regnum (operands[0]) != true_regnum (operands[2]))
+ return \"mov %1,%0\;sub %2,%0\";
+ return \"sub %2,%1,%0\";
+ }
+}"
+ [(set_attr "cc" "set_zn")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dax")
(minus:SI (match_operand:SI 1 "register_operand" "0")
;; MULTIPLY INSTRUCTIONS
;; ----------------------------------------------------------------------
+(define_insn "mulsidi3"
+ [(set (match_operand:DI 0 "register_operand" "=dax")
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "dax"))
+ (sign_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
+ "TARGET_AM33"
+ "mul %1,%2,%H0,%L0"
+ [(set_attr "cc" "set_zn")])
+
+(define_insn "umulsidi3"
+ [(set (match_operand:DI 0 "register_operand" "=dax")
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "dax"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
+ "TARGET_AM33"
+ "mulu %1,%2,%H0,%L0"
+ [(set_attr "cc" "set_zn")])
+
(define_expand "mulsi3"
[(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "register_operand" "")
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
+ (mult:SI (match_operand:SI 1 "register_operand" "%0,0")
+ (match_operand:SI 2 "nonmemory_operand" "dx,daxi")))]
+ "TARGET_AM33"
+ "*
+{
+ if (TARGET_MULT_BUG)
+ return \"nop\;nop\;mul %2,%0\";
+ else
+ return \"mul %2,%0\";
+}"
+ [(set_attr "cc" "set_zn")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax")
+ (and:SI (match_operand:SI 1 "register_operand" "%0,0,dax")
+ (match_operand:SI 2 "nonmemory_operand" "N,dxi,dax")))]
+ "TARGET_AM33"
+ "*
+{
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
+ return \"extbu %0\";
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
+ return \"exthu %0\";
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
+ return \"add %0,%0\;lsr 1,%0\";
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
+ return \"asl2 %0\;lsr 2,%0\";
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
+ return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
+ return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
+ return \"lsr 1,%0\;add %0,%0\";
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
+ return \"lsr 2,%0\;asl2 %0\";
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
+ return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
+ return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
+ if (REG_P (operands[2]) && REG_P (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[2])
+ && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
+ && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
+ && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
+ return \"mov %1,%0\;and %2,%0\";
+ if (REG_P (operands[2]) && REG_P (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[2]))
+ return \"and %1,%2,%0\";
+ if (REG_P (operands[2]) && REG_P (operands[0])
+ && true_regnum (operands[2]) == true_regnum (operands[0]))
+ return \"and %1,%0\";
+ return \"and %2,%0\";
+}"
+ [(set_attr "cc" "none_0hit,set_znv,set_znv")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx,dx")
(and:SI (match_operand:SI 1 "register_operand" "%0,0")
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
+ (ior:SI (match_operand:SI 1 "register_operand" "%0,dax")
+ (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
+ "TARGET_AM33"
+ "*
+{
+ if (REG_P (operands[2]) && REG_P (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[2])
+ && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
+ && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
+ && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
+ return \"mov %1,%0\;or %2,%0\";
+ if (REG_P (operands[2]) && REG_P (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[2]))
+ return \"or %1,%2,%0\";
+ if (REG_P (operands[2]) && REG_P (operands[0])
+ && true_regnum (operands[2]) == true_regnum (operands[0]))
+ return \"or %1,%0\";
+ return \"or %2,%0\";
+}"
+ [(set_attr "cc" "set_znv")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(ior:SI (match_operand:SI 1 "register_operand" "%0")
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
+ (xor:SI (match_operand:SI 1 "register_operand" "%0,dax")
+ (match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
+ "TARGET_AM33"
+ "*
+{
+ if (REG_P (operands[2]) && REG_P (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[2])
+ && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
+ && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
+ && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
+ return \"mov %1,%0\;xor %2,%0\";
+ if (REG_P (operands[2]) && REG_P (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[1])
+ && true_regnum (operands[0]) != true_regnum (operands[2]))
+ return \"xor %1,%2,%0\";
+ if (REG_P (operands[2]) && REG_P (operands[0])
+ && true_regnum (operands[2]) == true_regnum (operands[0]))
+ return \"xor %1,%0\";
+ return \"xor %2,%0\";
+}"
+ [(set_attr "cc" "set_znv")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(xor:SI (match_operand:SI 1 "register_operand" "%0")
(not:SI (match_operand:SI 1 "register_operand" "")))]
""
"")
-
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
+ (not:SI (match_operand:SI 1 "register_operand" "0,0")))]
+ "TARGET_AM33"
+ "not %0"
+ [(set_attr "cc" "set_znv")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(not:SI (match_operand:SI 1 "register_operand" "0")))]
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx,!dax,!dax,!dax")
+ (zero_extend:SI
+ (match_operand:QI 1 "general_operand" "0,dax,m,0,dax,m")))]
+ "TARGET_AM33"
+ "@
+ extbu %0
+ mov %1,%0\;extbu %0
+ movbu %1,%0
+ extbu %0
+ mov %1,%0\;extbu %0
+ movbu %1,%0"
+ [(set_attr "cc" "none_0hit")])
+
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
(zero_extend:SI
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx,!dax,!dax,!dax")
+ (zero_extend:SI
+ (match_operand:HI 1 "general_operand" "0,dax,m,0,dax,m")))]
+ "TARGET_AM33"
+ "@
+ exthu %0
+ mov %1,%0\;exthu %0
+ movhu %1,%0
+ exthu %0
+ mov %1,%0\;exthu %0
+ movhu %1,%0"
+ [(set_attr "cc" "none_0hit")])
+
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
(zero_extend:SI
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "general_operand" "=dx,dx,!dax,!dax")
+ (sign_extend:SI
+ (match_operand:QI 1 "general_operand" "0,dx,0,dax")))]
+ "TARGET_AM33"
+ "@
+ extb %0
+ mov %1,%0\;extb %0
+ extb %0
+ mov %1,%0\;extb %0"
+ [(set_attr "cc" "none_0hit")])
+
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=dx,dx")
(sign_extend:SI
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "general_operand" "=dx,dx,!dax,!dax")
+ (sign_extend:SI
+ (match_operand:HI 1 "general_operand" "0,dax,0,dax")))]
+ "TARGET_AM33"
+ "@
+ exth %0
+ mov %1,%0\;exth %0
+ exth %0
+ mov %1,%0\;exth %0"
+ [(set_attr "cc" "none_0hit")])
+
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=dx,dx")
(sign_extend:SI
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dax,dx,!dax")
+ (ashift:SI
+ (match_operand:SI 1 "register_operand" "0,0,dax")
+ (match_operand:QI 2 "nonmemory_operand" "J,dxi,dax")))]
+ "TARGET_AM33"
+ "*
+{
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 1)
+ return \"add %0,%0\";
+
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 2)
+ return \"asl2 %0\";
+
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 3
+ && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
+ return \"asl2 %0\;add %0,%0\";
+
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 4
+ && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
+ return \"asl2 %0\;asl2 %0\";
+
+ if (true_regnum (operands[1]) == true_regnum (operands[0]))
+ return \"asl %S2,%0\";
+
+ if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
+ && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
+ && true_regnum (operands[0]) != true_regnum (operands[2]))
+ return \"mov %1,%0\;asl %S2,%0\";
+ return \"asl %2,%1,%0\";
+}"
+ [(set_attr "cc" "set_zn")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
(ashift:SI
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
+ (lshiftrt:SI
+ (match_operand:SI 1 "register_operand" "0,dax")
+ (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
+ "TARGET_AM33"
+ "*
+{
+ if (true_regnum (operands[1]) == true_regnum (operands[0]))
+ return \"lsr %S2,%0\";
+
+ if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
+ && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
+ && true_regnum (operands[0]) != true_regnum (operands[2]))
+ return \"mov %1,%0\;lsr %S2,%0\";
+ return \"lsr %2,%1,%0\";
+}"
+ [(set_attr "cc" "set_zn")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(lshiftrt:SI
""
"")
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
+ (ashiftrt:SI
+ (match_operand:SI 1 "register_operand" "0,dax")
+ (match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
+ "TARGET_AM33"
+ "*
+{
+ if (true_regnum (operands[1]) == true_regnum (operands[0]))
+ return \"asr %S2,%0\";
+
+ if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
+ && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
+ && true_regnum (operands[0]) != true_regnum (operands[2]))
+ return \"mov %1,%0\;asr %S2,%0\";
+ return \"asr %2,%1,%0\";
+}"
+ [(set_attr "cc" "set_zn")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx")
(ashiftrt:SI
{
int i, need_comma;
int d2, d3, a2, a3;
+ int exreg1;
need_comma = 0;
fputs (\"\\tret [\", asm_out_file);
fputs (\"a3\", asm_out_file);
need_comma = 1;
}
+ if (regs_ever_live[14] || regs_ever_live[15]
+ || regs_ever_live[16] || regs_ever_live[17])
+ {
+ if (need_comma)
+ fputc (',', asm_out_file);
+ fputs (\"exreg1\", asm_out_file);
+ need_comma = 1;
+ }
fprintf (asm_out_file, \"],%d\\n\", INTVAL (operands[0]));
return \"\";
}"
{
int i, need_comma;
int d2, d3, a2, a3;
+ int exreg1;
need_comma = 0;
fputs (\"\\tmovm [\", asm_out_file);
fputs (\"a3\", asm_out_file);
need_comma = 1;
}
+ if (regs_ever_live[14] || regs_ever_live[15]
+ || regs_ever_live[16] || regs_ever_live[17])
+ {
+ if (need_comma)
+ fputc (',', asm_out_file);
+ fputs (\"exreg1\", asm_out_file);
+ need_comma = 1;
+ }
fputs (\"],(sp)\\n\", asm_out_file);
return \"\";
}"
projects / gcc.git / commitdiff