* config/alpha/alpha.md (vec_shl_<VEC>, vec_shr_<VEC>): New.

From-SVN: r101434

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9849127504978f180f7c2df3aef1ab5d46b1e407..9bf9bc22cd0d5500ab4145649530d7d365915cad 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2005-06-29  Richard Henderson  <rth@redhat.com>
+
+       * config/alpha/alpha.md (vec_shl_<VEC>, vec_shr_<VEC>): New.
+
 2005-06-29  Richard Henderson  <rth@redhat.com>
 
        * tree-vect-transform.c (vect_min_worthwhile_factor): Declare.

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 157e8caf2d65101b6ecd43a28e3dca00db2cdd15..35cc320ea840e4c04b8b312dd706f68bb59bb446 100644 (file)
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -6361,6 +6361,26 @@
   ""
   "eqv %1,%2,%0"
   [(set_attr "type" "ilog")])
+
+(define_expand "vec_shl_<mode>"
+  [(set (match_operand:VEC 0 "register_operand" "")
+       (ashift:DI (match_operand:VEC 1 "register_operand" "")
+                  (match_operand:DI 2 "reg_or_6bit_operand" "")))]
+  ""
+{
+  operands[0] = gen_lowpart (DImode, operands[0]);
+  operands[1] = gen_lowpart (DImode, operands[1]);
+})
+
+(define_expand "vec_shr_<mode>"
+  [(set (match_operand:VEC 0 "register_operand" "")
+        (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
+                     (match_operand:DI 2 "reg_or_6bit_operand" "")))]
+  ""
+{
+  operands[0] = gen_lowpart (DImode, operands[0]);
+  operands[1] = gen_lowpart (DImode, operands[1]);
+})
 \f
 ;; Bit field extract patterns which use ext[wlq][lh]