radeonsi: clarify documentation of existing SI workaround

Limiting LS-HS to a single wave is required on all SI chips due to an
issue with a power management feature.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index f0ed898cfb0333db157e113edd9ac73a09c2f071..f7190055e3b7b2397e63af78b21257c1e4006968 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -184,8 +184,10 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
         */
        *num_patches = MIN2(*num_patches, 40);
 
-       /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
        if (sctx->b.chip_class == SI) {
+               /* SI bug workaround, related to power management. Limit LS-HS
+                * threadgroups to only one wave.
+                */
                unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
                *num_patches = MIN2(*num_patches, one_wave);