ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
}
-void r600_init_cs(struct r600_context *ctx)
-{
- struct radeon_winsys_cs *cs = ctx->cs;
-
- /* All asics require this one */
- cs->buf[cs->cdw++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
- cs->buf[cs->cdw++] = 0x80000000;
- cs->buf[cs->cdw++] = 0x80000000;
-
- ctx->init_dwords = cs->cdw;
-}
-
/* initialize */
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
boolean count_draw_in)
bool queries_suspended = false;
bool streamout_suspended = false;
- if (cs->cdw == ctx->init_dwords)
+ if (!cs->cdw)
return;
/* suspend queries */
ctx->pm4_dirty_cdwords = 0;
ctx->flags = 0;
- r600_init_cs(ctx);
-
if (streamout_suspended) {
ctx->streamout_start = TRUE;
ctx->streamout_append_bitmask = ~0;
struct radeon_winsys_cs *cs;
unsigned pm4_dirty_cdwords;
- unsigned init_dwords;
/* The list of active queries. Only one query of each type can be active. */
struct list_head active_query_list;
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
+ si_pm4_cmd_add(pm4, 0x80000000);
+ si_pm4_cmd_add(pm4, 0x80000000);
+ si_pm4_cmd_end(pm4, false);
+
si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);