return std::max(wid1, wid2);
}
+void sv_regmap_8to16(union sv_reg_csr_entry8 const& r8,
+ union sv_reg_csr_entry &r16)
+{
+ r16.b.regkey = r8.b.regkey;
+ r16.b.elwidth = r8.b.elwidth;
+ r16.b.type = r8.b.type;
+ r16.b.regidx = r8.b.regkey << 2; // multiply by 4, no room for 6 bits
+ r16.b.isvec = 1; // has to be a vector
+}
+
+void sv_predmap_8to16(union sv_pred_csr_entry8 const& r8,
+ union sv_pred_csr_entry &r16,
+ uint64_t table_idx)
+{
+ r16.b.regkey = r8.b.regkey;
+ r16.b.zero = r8.b.zero;
+ r16.b.inv = r8.b.inv;
+ r16.b.type = r8.b.type;
+ r16.b.regidx = table_idx + 9; // 8-bit format starts at x9
+ r16.b.ffirst = 0; // no room, whoops.
+}
+
/* increments the sub-offset appropriately in a FSM-based
version of a twin-nested for-loop:
for (suboffs = 0; suboffs < subvl; suboffs++) {
unsigned short u;
};
+// the 8-bit (compact) variant
+union sv_reg_csr_entry8 {
+ struct {
+ uint64_t regkey : 5; // 5 bits
+ unsigned int elwidth: 2; // 0=dflt, 1=dflt/2, 2=dflt*2 3=8-bit
+ unsigned int type : 1; // 1=INT, 0=FP
+ } b;
+ unsigned char u;
+};
+
+void sv_regmap_8to16(union sv_reg_csr_entry8 const& r8,
+ union sv_reg_csr_entry8 &r16);
+
// TODO: define separate SV CSRs for M-mode and S-Mode
// M-Mode and S-Mode will need a minimum of 2 for int-only
// platforms, and a minimum of 4 for int/fp.
unsigned short u;
};
+// the 8-bit (compact) variant
+union sv_pred_csr_entry8 {
+ struct {
+ uint64_t regkey: 5; // 5 bits
+ unsigned int zero : 1; // zeroing=1, skipping=0
+ unsigned int inv : 1; // inversion=1
+ unsigned int type : 1; // 1=INT, 0=FP
+ } b;
+ unsigned char u;
+};
+
+void sv_predmap_8to16(union sv_reg_csr_entry8 const& r8,
+ union sv_reg_csr_entry8 &r16,
+ uint64_t table_idx);
+
typedef struct {
uint64_t regkey: 5; // 5 bits
unsigned int zero : 1; // zeroing=1, skipping=0