test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = test_sys.voltage_domain)
+ # Connect the ruby io port to the PIO bus,
+ # assuming that there is just one such port.
+ test_sys.iobus.master = test_sys.ruby._io_port.slave
+
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
- # Connect the ruby io port to the PIO bus,
- # assuming that there is just one such port.
- test_sys.iobus.master = test_sys.ruby._io_port.slave
-
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
- options.use_map = True
Ruby.create_system(options, False, system)
assert(options.num_cpus == len(system.ruby._cpu_ports))