corelogic/roundrobin: fix request width (again)

diff --git a/migen/corelogic/roundrobin.py b/migen/corelogic/roundrobin.py
index 298c7d166aaba9aadda6df98b6337c36824a3b3f..f55b3feeb0ca4b13c35daecc951ed0274431af22 100644 (file)
--- a/migen/corelogic/roundrobin.py
+++ b/migen/corelogic/roundrobin.py
@@ -5,7 +5,7 @@ from migen.fhdl.structure import *
 class RoundRobin:
        def __init__(self, n, switch_policy=SP_WITHDRAW):
                self.n = n
-               self.request = Signal(nbits=self.n)
+               self.request = Signal(self.n)
                self.grant = Signal(max=self.n)
                self.switch_policy = switch_policy
                if self.switch_policy == SP_CE: