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diff --git a/openpower/ISA_WG/Board_letter_26mar2021.mdwn b/openpower/ISA_WG/Board_letter_26mar2021.mdwn
index a1083636067217906eb8ebf68a302caa35371004..bd7a6628f2a527f49bedc47c96b722f341bd4788 100644 (file)
--- a/openpower/ISA_WG/Board_letter_26mar2021.mdwn
+++ b/openpower/ISA_WG/Board_letter_26mar2021.mdwn
@@ -22,7 +22,7 @@ to be sent to:
 
 Dear OPF Board,
 
-As you know the LibreSOC team have been working for over 3 years on a massive conceptual upgrade to the OpenPOWER ISA, based on Cray-Style Vectors, which will modernise it for today's 3D and VPU workloads, with an incidental side-effect of upgrading it for future supercomputing needs.  RISC-V has RVV, ARM has SVE2, x86 has AVX512, whilst OpenPOWER has an out-of-date SIMD ISA. It goes without saying that over the decades, SIMD has been demonstrated to be harmful.
+As you know the LibreSOC team have been working for over 3 years on a massive conceptual upgrade to the OpenPOWER ISA, based on Cray-Style Vectors, which will modernise it for today's 3D and VPU workloads, with an incidental side-effect of upgrading it for future supercomputing needs over the next few decades in a clean and elegant fashion.  RISC-V has RVV, ARM has SVE2, x86 has AVX512, whilst OpenPOWER has an out-of-date SIMD ISA. It goes without saying that over the decades, SIMD has been demonstrated to be harmful.
 
 https://www.sigarch.org/simd-instructions-considered-harmful/