sim/verilator: add multithread support (default=1)

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 4673569f3ad69a74180009f0aab48619a59388ea..f925525069594ce63d0856532b019de348c8587a 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -144,6 +144,8 @@ def main():
     parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
     builder_args(parser)
     soc_sdram_args(parser)
+    parser.add_argument("--threads", default=1,
+                        help="set number of threads (default=1)")
     parser.add_argument("--rom-init", default=None,
                         help="rom_init file")
     parser.add_argument("--ram-init", default=None,
@@ -183,10 +185,10 @@ def main():
         **soc_kwargs)
     builder_kwargs["csr_csv"] = "csr.csv"
     builder = Builder(soc, **builder_kwargs)
-    vns = builder.build(run=False, sim_config=sim_config)
+    vns = builder.build(run=False, threads=args.threads, sim_config=sim_config)
     if args.with_analyzer:
         soc.analyzer.export_csv(vns, "analyzer.csv")
-    builder.build(build=False, sim_config=sim_config)
+    builder.build(build=False, threads=args.threads, sim_config=sim_config)
 
 
 if __name__ == "__main__":

diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile
index 733ea531bb003df9b75e15f103be9abac28c2e7e..daba3ddac1b993e2ee2babecffd6b63375013593 100644 (file)
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@ -27,6 +27,7 @@ sim: mkdir $(OBJS_SIM)
        verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
                $(SRCS_SIM_CPP) $(OBJS_SIM) \
                --top-module dut \
+               --threads $(THREADS) \
                -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
                -LDFLAGS "$(LDFLAGS)" \
                -trace $(INC_DIR)

diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 1e6176eaad74d5f122a635bef18d24c8187216f2..833685e1d80d47e1a7f9e600800fc999dfc41060 100644 (file)
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -103,13 +103,13 @@ def _generate_sim_config(config):
     tools.write_to_file("sim_config.js", content)
 
 
-def _build_sim(platform, build_name, verbose):
+def _build_sim(platform, build_name, threads, verbose):
     makefile = os.path.join(core_directory, 'Makefile')
     build_script_contents = """\
 rm -rf obj_dir/
-make -C . -f {}
+make -C . -f {} THREADS={}
 mkdir -p modules && cp obj_dir/*.so modules
-""".format(makefile)
+""".format(makefile, threads)
     build_script_file = "build_" + build_name + ".sh"
     tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
 
@@ -145,8 +145,8 @@ def _run_sim(build_name, as_root=False):
 
 class SimVerilatorToolchain:
     def build(self, platform, fragment, build_dir="build", build_name="dut",
-            toolchain_path=None, serial="console", build=True, run=True, verbose=True,
-            sim_config=None):
+            toolchain_path=None, serial="console", build=True, run=True, threads=1,
+            verbose=True, sim_config=None):
 
         os.makedirs(build_dir, exist_ok=True)
         os.chdir(build_dir)
@@ -173,7 +173,7 @@ class SimVerilatorToolchain:
             if sim_config:
                 _generate_sim_config(sim_config)
 
-            _build_sim(platform, build_name, verbose)
+            _build_sim(platform, build_name, threads, verbose)
 
         if run:
             _run_sim(build_name, as_root=sim_config.has_module("ethernet"))