altivec.md (xorv4sf3): New.

        * config/rs6000/altivec.md (xorv4sf3): New.
        (negv4sf2, neg<mode>2): Likewise.

From-SVN: r103335

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ab5bb6a022ed3900dab901aea8cc843d34a7cd42..968c435ca8b64c98b3c72d3ee7e11ba9f4664ed7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2005-08-22 Ira Rosen <irar@il.ibm.com>
+
+       * config/rs6000/altivec.md (xorv4sf3): New.
+       (negv4sf2, neg<mode>2): Likewise.
+
 2005-08-21  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/23485

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 025243557039a3599108e12e2d2af929da27329d..9016b0d09a0589ce9281a8045e2e4a2adfc4b92b 100644 (file)
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1039,6 +1039,14 @@
   "vxor %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
+(define_insn "xorv4sf3"
+  [(set (match_operand:V4SF 0 "register_operand" "=v")
+        (xor:V4SF (match_operand:V4SF 1 "register_operand" "v")
+                  (match_operand:V4SF 2 "register_operand" "v")))]
+  "TARGET_ALTIVEC"
+  "vxor %0,%1,%2" 
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "one_cmpl<mode>2"
   [(set (match_operand:VI 0 "register_operand" "=v")
         (not:VI (match_operand:VI 1 "register_operand" "v")))]
@@ -2161,3 +2169,37 @@
   "TARGET_ALTIVEC"
   "vperm %0,%1,%2,%3"
   [(set_attr "type" "vecperm")])
+
+(define_expand "neg<mode>2"
+  [(use (match_operand:VI 0 "register_operand" ""))
+   (use (match_operand:VI 1 "register_operand" ""))]
+  "TARGET_ALTIVEC"
+  "
+{
+  rtx vzero;
+
+  vzero = gen_reg_rtx (GET_MODE (operands[0]));
+  emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
+  emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1])); 
+  
+  DONE;
+}")
+
+(define_expand "negv4sf2"
+  [(use (match_operand:V4SF 0 "register_operand" ""))
+   (use (match_operand:V4SF 1 "register_operand" ""))]
+  "TARGET_ALTIVEC"
+  "
+{
+  rtx neg0;
+
+  /* Generate [-0.0, -0.0, -0.0, -0.0].  */
+  neg0 = gen_reg_rtx (V4SFmode);
+  emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
+  emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
+
+  /* XOR */
+  emit_insn (gen_xorv4sf3 (operands[0], neg0, operands[1])); 
+    
+  DONE;
+}")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1fb2989b716ca3283b956d5e74519a0bc1605484..518c6a00496ea2842282613a5941e58dcf2bb4c3 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2005-08-22  Ira Rosen  <irar@il.ibm.com>   
+
+       * gcc.dg/vect/vect-22.c: Add test for float. All four loops
+       are vectorizable.
+
 2005-08-21  Tobias Schl"uter  <tobias.schlueter@physik.uni-muenchen.de>
        
        * d_lines_1.f, d_lines_2.f, d_lines_3.f, d_lines_4.f,

diff --git a/gcc/testsuite/gcc.dg/vect/vect-22.c b/gcc/testsuite/gcc.dg/vect/vect-22.c
index f15a4ff50fcf4775e9878d20b9cd24e41cbab5ac..af46e8216ed8932fe4c014a20359ff9a8b27cb2f 100644 (file)
--- a/gcc/testsuite/gcc.dg/vect/vect-22.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-22.c
@@ -42,6 +42,17 @@ main1 ()
      1,1,0,0,1,0,1,0,
      1,1,0,0,1,0,1,0};
 
+  float fa[N];
+  float fb[N] =
+    {1,1,0,0,1,0,1,0,
+     1,1,0,0,1,0,1,0,
+     1,1,0,0,1,0,1,0,
+     1,1,0,0,1,0,1,0,
+     1,1,0,0,1,0,1,0,
+     1,1,0,0,1,0,1,0,
+     1,1,0,0,1,0,1,0,
+     1,1,0,0,1,0,1,0};
+
   /* Check ints.  */
 
   for (i = 0; i < N; i++)
@@ -84,6 +95,20 @@ main1 ()
         abort ();
     }
 
+  /* Check floats.  */
+
+  for (i = 0; i < N; i++)
+    {
+      fa[i] = -fb[i];
+    }
+
+  /* check results:  */
+  for (i = 0; i <N; i++)
+    {
+      if (fa[i] != -fb[i])
+        abort ();
+    }
+
   return 0;
 }
 
@@ -94,7 +119,7 @@ int main (void)
   return main1 ();
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" { xfail *-*-* } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" } } */
 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
 
 /* { dg-final { cleanup-tree-dump "vect" } } */