return src;
}
-/* Need to declare all constants if indirect addressing is used,
- * otherwise we could scan the shader to determine the maximum.
- * TODO: It doesn't really matter for nv50 so I won't do the scan,
- * but radeon drivers might care, if they don't infer it from TGSI.
- */
-static void
-tx_decl_constants(struct shader_translator *tx)
-{
- unsigned i, n = 0;
-
- for (i = 0; i < NINE_MAX_CONST_F; ++i)
- ureg_DECL_constant(tx->ureg, n++);
- for (i = 0; i < NINE_MAX_CONST_I; ++i)
- ureg_DECL_constant(tx->ureg, n++);
- for (i = 0; i < (NINE_MAX_CONST_B / 4); ++i)
- ureg_DECL_constant(tx->ureg, n++);
-}
-
static INLINE void
tx_temp_alloc(struct shader_translator *tx, INT idx)
{
struct shader_translator *tx;
HRESULT hr = D3D_OK;
const unsigned processor = tgsi_processor_from_type(info->type);
- unsigned slot_max;
+ unsigned s, slot_max;
user_assert(processor != ~0, D3DERR_INVALIDCALL);
hr = E_OUTOFMEMORY;
goto out;
}
- tx_decl_constants(tx);
tx->native_integers = GET_SHADER_CAP(INTEGERS);
tx->inline_subroutines = !GET_SHADER_CAP(SUBROUTINES);
if (IS_VS && !ureg_dst_is_undef(tx->regs.oPts))
info->point_size = TRUE;
- if (debug_get_bool_option("NINE_TGSI_DUMP", FALSE)) {
- unsigned count;
- const struct tgsi_token *toks = ureg_get_tokens(tx->ureg, &count);
- tgsi_dump(toks, 0);
- ureg_free_tokens(toks);
- }
-
/* record local constants */
if (tx->num_lconstf && tx->indirect_const_access) {
struct nine_range *ranges;
info->const_float_slots;
info->const_used_size = sizeof(float[4]) * slot_max; /* slots start from 1 */
+ for (s = 0; s < slot_max; s++)
+ ureg_DECL_constant(tx->ureg, s);
+
+ if (debug_get_bool_option("NINE_TGSI_DUMP", FALSE)) {
+ unsigned count;
+ const struct tgsi_token *toks = ureg_get_tokens(tx->ureg, &count);
+ tgsi_dump(toks, 0);
+ ureg_free_tokens(toks);
+ }
+
info->cso = ureg_create_shader_and_destroy(tx->ureg, device->pipe);
if (!info->cso) {
hr = D3DERR_DRIVERINTERNALERROR;