re PR target/71720 (initialization of a vector of floats generates incorrect code...

[gcc]
2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71720
	* config/rs6000/vsx.md (vsx_splat_v4sf_internal): When splitting
	the insns, use vsx_xxspltw_v4sf_direct which does not check for
	little endian.

[gcc/testsuite]
2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71720
	* gcc.target/powerpc/pr71720.c: New test.

From-SVN: r237920

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4020a4e37d4046d68f990eaf166088ace9f15db2..a2fccf51852ae4dee6440b9c8a1b1bb63f4ee199 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/71720
+       * config/rs6000/vsx.md (vsx_splat_v4sf_internal): When splitting
+       the insns, use vsx_xxspltw_v4sf_direct which does not check for
+       little endian.
+
 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 
        * varasm.c (get_variable_section): Validate initializer in

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 2e1d41d61431b9cd8bd02a8e92eb3c5aec22c7e0..861b1479a2e1db896ddb966f8d06ec36f22d221a 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2512,9 +2512,8 @@
   [(set (match_dup 0)
        (unspec:V4SF [(match_dup 1)] UNSPEC_VSX_CVDPSPN))
    (set (match_dup 0)
-       (vec_duplicate:V4SF
-        (vec_select:SF (match_dup 0)
-                       (parallel [(const_int 0)]))))]
+       (unspec:V4SF [(match_dup 0)
+                     (const_int 0)] UNSPEC_VSX_XXSPLTW))]
   ""
   [(set_attr "type" "vecload,vecperm,mftgpr")
    (set_attr "length" "4,8,4")])

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 382c172c77800f3aede4bcf3805822e96fd7ebb9..a1255a0763f291fde8efba9e1eb775d6e4d59711 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-07-01  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/71720
+       * gcc.target/powerpc/pr71720.c: New test.
+
 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 
        * gcc.dg/bss.c: New.

diff --git a/gcc/testsuite/gcc.target/powerpc/pr71720.c b/gcc/testsuite/gcc.target/powerpc/pr71720.c
new file mode 100644 (file)
index 0000000..a0c330d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr71720.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+
+/* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat.  */
+
+vector float
+splat_v4sf (float f)
+{
+  return (vector float) { f, f, f, f };
+}
+
+/* { dg-final { scan-assembler "xscvdpspn "      } } */
+/* { dg-final { scan-assembler "xxspltw .*,.*,0" } } */