[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal feature...

This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)

This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

    * config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a.
    * doc/c-aarch64.texi: Add documentation for the same.

*** include/ChnageLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

    * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
    (AARCH64_ARCH_V8_5): New.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

    * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
    (ARMV8_5, V8_5_INSN): New.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b531980df53788b29d8d69a4f6945e16560ec91d..bed87c9048e1d8939e48c52910ffe681c7cfacea 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a.
+       * doc/c-aarch64.texi: Add documentation for the same.
+
 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 
+
        * testsuite/gas/i386/se1.s: Add enclv.
        * testsuite/gas/i386/x86-64-se1.s: Likewise.
        * testsuite/gas/i386/se1.d: Updated.

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 085ffa26f0e4594fe97b50d19d79e27f742f34e6..9ae05e05b166aed12d82dd26d27103238b6d1777 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8694,6 +8694,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
   {"armv8.2-a", AARCH64_ARCH_V8_2},
   {"armv8.3-a", AARCH64_ARCH_V8_3},
   {"armv8.4-a", AARCH64_ARCH_V8_4},
+  {"armv8.5-a", AARCH64_ARCH_V8_5},
   {NULL, AARCH64_ARCH_NONE}
 };
 

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index b659b8ba5971b964fbdf3357c97093471227db67..bac0f7775e51e8ac97bf88408d9ad53d9cac7a3e 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -91,7 +91,8 @@ This option specifies the target architecture.  The assembler will
 issue an error message if an attempt is made to assemble an
 instruction which will not execute on the target architecture.  The
 following architecture names are recognized: @code{armv8-a},
-@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a} and @code{armv8.4-a}.
+@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
+and @code{armv8.5-a}.
 
 If both @option{-mcpu} and @option{-march} are specified, the
 assembler will use the setting for @option{-mcpu}.  If neither are

diff --git a/include/ChangeLog b/include/ChangeLog
index ce95a616627d088b5b9c3586ac0c9aea63510976..2ccf741842880144b1c95388d173637668bffa62 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
+       (AARCH64_ARCH_V8_5): New.
+
 2018-10-08  Alan Modra  <amodra@gmail.com>
 
        * bfdlink.h (struct bfd_link_info): Add load_phdrs field.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f66ee8608ad2be3671708a4b8904c96191e96e6a..f8ae42fca8e6cba3328a777fa66ebc2e73a39614 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -62,6 +62,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_COMPNUM        0x40000000      /* Complex # instructions.  */
 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
 #define AARCH64_FEATURE_F16_FML        0x1000000000ULL /* v8.2 FP16FML ins.  */
+#define AARCH64_FEATURE_V8_5   0x2000000000ULL /* ARMv8.5 processors.  */
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8                AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -85,6 +86,9 @@ typedef uint32_t aarch64_insn;
                                                 AARCH64_FEATURE_V8_4   \
                                                 | AARCH64_FEATURE_DOTPROD \
                                                 | AARCH64_FEATURE_F16_FML)
+#define AARCH64_ARCH_V8_5      AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
+                                                AARCH64_FEATURE_V8_5)
+
 
 #define AARCH64_ARCH_NONE      AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY            AARCH64_FEATURE (-1, 0) /* Any basic core.  */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 64070471c440ae5db6a3b61d86bdd162c1751839..2b13be58af29fa9b81c049b53de36eb7da07fa6f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
+       (ARMV8_5, V8_5_INSN): New.
+
 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 
        * aarch64-opc.c (verify_constraints): Use memset instead of {0}.

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 825324efbee1cbe03bc14ac168babc5a41194747..50a9a4946c4587ddd7d603d810723626a4d0c1fb 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2159,6 +2159,9 @@ static const aarch64_feature_set aarch64_feature_sha3 =
 static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
   AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F16_FML
                   | AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
+static const aarch64_feature_set aarch64_feature_v8_5 =
+  AARCH64_FEATURE (AARCH64_FEATURE_V8_5, 0);
+
 
 #define CORE           &aarch64_feature_v8
 #define FP             &aarch64_feature_fp
@@ -2186,6 +2189,7 @@ static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
 #define CRYPTO_V8_2    &aarch64_feature_crypto_v8_2
 #define FP_F16_V8_2    &aarch64_feature_fp_16_v8_2
 #define DOTPROD                &aarch64_feature_dotprod
+#define ARMV8_5                &aarch64_feature_v8_5
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2237,6 +2241,8 @@ static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
   { NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define V8_5_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_5, OPS, QUALS, FLAGS, 0, 0, NULL }
 
 struct aarch64_opcode aarch64_opcode_table[] =
 {