Add more info

diff --git a/meetings/sync_up/sync_up_2023-11-28.mdwn b/meetings/sync_up/sync_up_2023-11-28.mdwn
index 86dcdadbecbe1ebec7bdd6688703b208fd0ee1c5..9c377256cc4912bbe1261d14bbca405a60d714e4 100644 (file)
--- a/meetings/sync_up/sync_up_2023-11-28.mdwn
+++ b/meetings/sync_up/sync_up_2023-11-28.mdwn
@@ -24,6 +24,10 @@
   See [[meetings/dmitry_2023-11-24]] notes for more context.
 
 - RISC-V example extension: <https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc>
+- The first step is to make modifications to `svanalysis.py` to classify the RISC-V instructions.
+- Standard RISC-V opcode format: <https://github.com/riscv/riscv-opcodes>
+- Invent an opcode format?
+
 
 # Dmitry