re PR target/49621 (ICE in trunc_int_for_mode, at explow.c:57)
authorJakub Jelinek <jakub@redhat.com>
Fri, 8 Jul 2011 20:09:58 +0000 (22:09 +0200)
committerJakub Jelinek <jakub@gcc.gnu.org>
Fri, 8 Jul 2011 20:09:58 +0000 (22:09 +0200)
PR target/49621
* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Use
CONST0_RTX (dest_mode) instead of const0_rtx as second operand
of NE.
* config/rs6000/vector.md (vector_select_<mode>,
vector_select_<mode>_uns): Change second operand of NE to
CONST0_RTX (<MODE>mode) instead of const0_rtx.
* config/rs6000/altivec.md (*altivec_vsel<mode>,
*altivec_vsel<mode>_uns): Expect second operand of NE to be
zero_constant of the corresponding vector mode.
* config/rs6000/vsx.md (*vsx_xxsel<mode>, *vsx_xxsel<mode>_uns):
Likewise.

* gcc.target/powerpc/altivec-34.c: New test.

From-SVN: r176063

gcc/ChangeLog
gcc/config/rs6000/altivec.md
gcc/config/rs6000/rs6000.c
gcc/config/rs6000/vector.md
gcc/config/rs6000/vsx.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/powerpc/altivec-34.c [new file with mode: 0644]

index 60412b237ebf224a17d58942ab5b19c57fce01f5..8ad805822fe32d96f49b0eb91094bccc76b10f43 100644 (file)
@@ -1,3 +1,18 @@
+2011-07-08  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/49621
+       * config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Use
+       CONST0_RTX (dest_mode) instead of const0_rtx as second operand
+       of NE.
+       * config/rs6000/vector.md (vector_select_<mode>,
+       vector_select_<mode>_uns): Change second operand of NE to
+       CONST0_RTX (<MODE>mode) instead of const0_rtx.
+       * config/rs6000/altivec.md (*altivec_vsel<mode>,
+       *altivec_vsel<mode>_uns): Expect second operand of NE to be
+       zero_constant of the corresponding vector mode.
+       * config/rs6000/vsx.md (*vsx_xxsel<mode>, *vsx_xxsel<mode>_uns):
+       Likewise.
+
 2011-07-08  Sebastian Pop  <sebastian.pop@amd.com>
 
        * graphite-dependences.c (build_alias_set_powerset): Remove
index 5e803f61727c215038f1d42b659432bbef2425a4..9e7437ed0fe995dbc1a118e766d0e10d1a058788 100644 (file)
   [(set (match_operand:VM 0 "altivec_register_operand" "=v")
        (if_then_else:VM
         (ne:CC (match_operand:VM 1 "altivec_register_operand" "v")
-               (const_int 0))
+               (match_operand:VM 4 "zero_constant" ""))
         (match_operand:VM 2 "altivec_register_operand" "v")
         (match_operand:VM 3 "altivec_register_operand" "v")))]
   "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
   [(set (match_operand:VM 0 "altivec_register_operand" "=v")
        (if_then_else:VM
         (ne:CCUNS (match_operand:VM 1 "altivec_register_operand" "v")
-                  (const_int 0))
+                  (match_operand:VM 4 "zero_constant" ""))
         (match_operand:VM 2 "altivec_register_operand" "v")
         (match_operand:VM 3 "altivec_register_operand" "v")))]
   "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
index 65de2e3f2fd422c9cf0799c3200c64320ae1f4de..475c10485f8c1226dd50e47f4aca0865037714b3 100644 (file)
@@ -16888,7 +16888,7 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
       op_false = tmp;
     }
 
-  cond2 = gen_rtx_fmt_ee (NE, cc_mode, mask, const0_rtx);
+  cond2 = gen_rtx_fmt_ee (NE, cc_mode, mask, CONST0_RTX (dest_mode));
   emit_insn (gen_rtx_SET (VOIDmode,
                          dest,
                          gen_rtx_IF_THEN_ELSE (dest_mode,
index c0112507a6e49723416a46021b8c239c050fc5f7..4799ff29e0a099040f79c238c4f87f21133f58ca 100644 (file)
   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
        (if_then_else:VEC_L
         (ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
-               (const_int 0))
+               (match_dup 4))
         (match_operand:VEC_L 2 "vlogical_operand" "")
         (match_operand:VEC_L 1 "vlogical_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "")
+  "operands[4] = CONST0_RTX (<MODE>mode);")
 
 (define_expand "vector_select_<mode>_uns"
   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
        (if_then_else:VEC_L
         (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
-                  (const_int 0))
+                  (match_dup 4))
         (match_operand:VEC_L 2 "vlogical_operand" "")
         (match_operand:VEC_L 1 "vlogical_operand" "")))]
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
-  "")
+  "operands[4] = CONST0_RTX (<MODE>mode);")
 
 ;; Expansions that compare vectors producing a vector result and a predicate,
 ;; setting CR6 to indicate a combined status
index d4f529676e42b000007e0001e4d659f775a2ab5d..b4d1e8b750991a359c1c3b7b3ff8c0daaab9e6f2 100644 (file)
   [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
        (if_then_else:VSX_L
         (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
-               (const_int 0))
+               (match_operand:VSX_L 4 "zero_constant" ""))
         (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
         (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
   [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
        (if_then_else:VSX_L
         (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
-                  (const_int 0))
+                  (match_operand:VSX_L 4 "zero_constant" ""))
         (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
         (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
index 21e6d8d84b1c7393cda612411773c49bafda9861..fc6931a24d22897a7a534b45b84a6c4f1bc4184a 100644 (file)
@@ -1,3 +1,8 @@
+2011-07-08  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/49621
+       * gcc.target/powerpc/altivec-34.c: New test.
+
 2011-07-08  Jason Merrill  <jason@redhat.com>
 
        PR c++/45603
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-34.c b/gcc/testsuite/gcc.target/powerpc/altivec-34.c
new file mode 100644 (file)
index 0000000..8e6372b
--- /dev/null
@@ -0,0 +1,24 @@
+/* PR target/49621 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -maltivec" } */
+
+#include <altivec.h>
+
+int
+foo (void)
+{
+  vector unsigned a, b, c;
+  unsigned k = 1;
+
+  a = (vector unsigned) { 0, 0, 0, 1 };
+  b = c = (vector unsigned) { 0, 0, 0, 0 };
+
+  a = vec_add (a, vec_splats (k));
+  b = vec_add (b, a);
+  c = vec_sel (c, a, b);
+
+  if (vec_any_eq (b, c))
+    return 1;
+
+  return 0;
+}