{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
struct pipe_driver_query_info list[] = {
+ {"num-compilations", R600_QUERY_NUM_COMPILATIONS, {0}, PIPE_DRIVER_QUERY_TYPE_UINT64,
+ PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE},
{"draw-calls", R600_QUERY_DRAW_CALLS, {0}},
{"requested-VRAM", R600_QUERY_REQUESTED_VRAM, {rscreen->info.vram_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
{"requested-GTT", R600_QUERY_REQUESTED_GTT, {rscreen->info.gart_size}, PIPE_DRIVER_QUERY_TYPE_BYTES},
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
num_queries = Elements(list);
else
- num_queries = 8;
+ num_queries = 9;
if (!info)
return num_queries;
#define R600_QUERY_CURRENT_GPU_SCLK (PIPE_QUERY_DRIVER_SPECIFIC + 9)
#define R600_QUERY_CURRENT_GPU_MCLK (PIPE_QUERY_DRIVER_SPECIFIC + 10)
#define R600_QUERY_GPU_LOAD (PIPE_QUERY_DRIVER_SPECIFIC + 11)
+#define R600_QUERY_NUM_COMPILATIONS (PIPE_QUERY_DRIVER_SPECIFIC + 12)
#define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
#define R600_CONTEXT_PRIVATE_FLAG (1u << 1)
uint32_t *trace_ptr;
unsigned cs_count;
+ /* This must be in the screen, because UE4 uses one context for
+ * compilation and another one for rendering.
+ */
+ unsigned num_compilations;
+
/* GPU load thread. */
pipe_mutex gpu_load_mutex;
pipe_thread gpu_load_thread;
case R600_QUERY_CURRENT_GPU_SCLK:
case R600_QUERY_CURRENT_GPU_MCLK:
case R600_QUERY_GPU_LOAD:
+ case R600_QUERY_NUM_COMPILATIONS:
return NULL;
}
case R600_QUERY_CURRENT_GPU_SCLK:
case R600_QUERY_CURRENT_GPU_MCLK:
case R600_QUERY_GPU_LOAD:
+ case R600_QUERY_NUM_COMPILATIONS:
skip_allocation = true;
break;
default:
case R600_QUERY_GPU_LOAD:
rquery->begin_result = r600_gpu_load_begin(rctx->screen);
return true;
+ case R600_QUERY_NUM_COMPILATIONS:
+ rquery->begin_result = p_atomic_read(&rctx->screen->num_compilations);
+ return true;
}
/* Discard the old query buffers. */
case R600_QUERY_GPU_LOAD:
rquery->end_result = r600_gpu_load_end(rctx->screen, rquery->begin_result);
return;
+ case R600_QUERY_NUM_COMPILATIONS:
+ rquery->end_result = p_atomic_read(&rctx->screen->num_compilations);
+ return;
}
r600_emit_query_end(rctx, rquery);
case R600_QUERY_GPU_TEMPERATURE:
case R600_QUERY_CURRENT_GPU_SCLK:
case R600_QUERY_CURRENT_GPU_MCLK:
+ case R600_QUERY_NUM_COMPILATIONS:
result->u64 = query->end_result - query->begin_result;
return TRUE;
case R600_QUERY_GPU_LOAD:
}
si_shader_init_pm4_state(shader);
sel->num_shaders++;
+ p_atomic_inc(&sctx->screen->b.num_compilations);
}
return 0;