* addr reg value can be:
*/
ctx->so->constlen = MAX2(ctx->so->constlen,
- ctx->so->shader->ubo_state.size / 16);
+ const_state->ubo_state.size / 16);
}
break;
/* num_driver_params is scalar, align to vec4: */
const_state->num_driver_params = align(const_state->num_driver_params, 4);
- debug_assert((shader->ubo_state.size % 16) == 0);
- unsigned constoff = shader->ubo_state.size / 16;
+ debug_assert((const_state->ubo_state.size % 16) == 0);
+ unsigned constoff = const_state->ubo_state.size / 16;
unsigned ptrsz = ir3_pointer_size(compiler);
if (const_state->num_ubos > 0) {
bool
ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader *shader)
{
- struct ir3_ubo_analysis_state *state = &shader->ubo_state;
+ struct ir3_ubo_analysis_state *state = &shader->const_state.ubo_state;
memset(state, 0, sizeof(*state));
for (int i = 0; i < IR3_MAX_UBO_PUSH_RANGES; i++) {
#define IR3_MAX_UBO_PUSH_RANGES 32
+struct ir3_ubo_range {
+ uint32_t offset; /* start offset to push in the const register file */
+ uint32_t block; /* Which constant block */
+ uint32_t start, end; /* range of block that's actually used */
+ uint16_t bindless_base; /* For bindless, which base register is used */
+ bool bindless;
+};
+
+struct ir3_ubo_analysis_state {
+ struct ir3_ubo_range range[IR3_MAX_UBO_PUSH_RANGES];
+ uint32_t num_enabled;
+ uint32_t size;
+ uint32_t lower_count;
+ uint32_t cmdstream_size; /* for per-gen backend to stash required cmdstream size */
+};
+
/**
* Describes the layout of shader consts. This includes:
* + User consts + driver lowered UBO ranges
struct {
uint32_t val[4];
} *immediates;
+
+ /* State of ubo access lowered to push consts: */
+ struct ir3_ubo_analysis_state ubo_state;
};
/**
}
}
-struct ir3_ubo_range {
- uint32_t offset; /* start offset to push in the const register file */
- uint32_t block; /* Which constant block */
- uint32_t start, end; /* range of block that's actually used */
- uint16_t bindless_base; /* For bindless, which base register is used */
- bool bindless;
-};
-
-struct ir3_ubo_analysis_state {
- struct ir3_ubo_range range[IR3_MAX_UBO_PUSH_RANGES];
- uint32_t num_enabled;
- uint32_t size;
- uint32_t lower_count;
- uint32_t cmdstream_size; /* for per-gen backend to stash required cmdstream size */
-};
-
struct ir3_shader {
gl_shader_stage type;
struct ir3_compiler *compiler;
- struct ir3_ubo_analysis_state ubo_state;
-
/* Number of UBOs loaded by LDC, as opposed to LDG through pointers in
* ubo_state.
*/
{
const struct tu_program_descriptor_linkage *link =
&pipeline->program.link[type];
- const struct ir3_ubo_analysis_state *state = &link->ubo_state;
+ const struct ir3_ubo_analysis_state *state = &link->const_state.ubo_state;
if (link->push_consts.count > 0) {
unsigned num_units = link->push_consts.count;
struct tu_shader *shader,
struct ir3_shader_variant *v)
{
- link->ubo_state = v->shader->ubo_state;
link->const_state = *ir3_const_state(v);
link->constlen = v->constlen;
link->push_consts = shader->push_consts;
struct tu_program_descriptor_linkage
{
- struct ir3_ubo_analysis_state ubo_state;
struct ir3_const_state const_state;
uint32_t constlen;
static unsigned
user_consts_cmdstream_size(struct ir3_shader_variant *v)
{
- struct ir3_ubo_analysis_state *ubo_state = &v->shader->ubo_state;
+ struct ir3_ubo_analysis_state *ubo_state = &ir3_const_state(v)->ubo_state;
if (unlikely(!ubo_state->cmdstream_size)) {
unsigned packets, size;
ir3_emit_user_consts(struct fd_screen *screen, const struct ir3_shader_variant *v,
struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
{
- struct ir3_ubo_analysis_state *state;
- state = &v->shader->ubo_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
+ const struct ir3_ubo_analysis_state *state = &const_state->ubo_state;
for (unsigned i = 0; i < state->num_enabled; i++) {
assert(!state->range[i].bindless);