-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
class Example(Module):
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.complex import *
from migen.fhdl import verilog
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.fsm import FSM
from random import Random
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.cdc import GrayCounter
from migen.sim.generic import Simulator
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.divider import Divider
-from migen.fhdl.structure import Fragment
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
class Example(Module):
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.fhdl import verilog
-from migen.fhdl.module import Module
from migen.genlib.misc import optree
def gen_list(n):
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.fhdl.specials import SynthesisDirective
from migen.fhdl import verilog
from migen.genlib.cdc import *
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.record import *
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.cdc import MultiReg
from migen.bank import description, csrgen
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Tristate
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
class Example(Module):
def __init__(self, n=6):
self.pad = Signal(n)
- self.o = Signal(n)
- self.oe = Signal()
- self.i = Signal(n)
-
- self.specials += Tristate(self.pad, self.o, self.oe, self.i)
+ self.t = TSTriple(n)
+ self.specials += self.t.get_tristate(self.pad)
e = Example()
-print(verilog.convert(e, ios={e.pad, e.o, e.oe, e.i}))
+print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
+from migen.fhdl.std import *
from migen.fhdl import verilog
-from migen.fhdl.module import Module
from migen.genlib import divider
class Example(Module):
from random import Random
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.network import *
from migen.flow.transactions import *
from migen.actorlib import dma_wishbone, dma_asmi
from migen.pytholite.transel import Register
from migen.pytholite.compiler import Pytholite
from migen.sim.generic import Simulator
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.fhdl import verilog
layout = [("r", 32)]
-# Copyright (C) 2012 Vermeer Manufacturing Co.
-# License: GPLv3 with additional permissions (see README).
-
from random import Random
-from migen.fhdl.structure import *
-from migen.fhdl import autofragment
+from migen.fhdl.std import *
from migen.bus.transactions import *
from migen.bus import wishbone, asmibus
from migen.sim.generic import Simulator
# Copyright (C) 2012 Vermeer Manufacturing Co.
# License: GPLv3 with additional permissions (see README).
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.sim.generic import Simulator
# Our simple counter, which increments at every cycle
# Copyright (C) 2012 Vermeer Manufacturing Co.
# License: GPLv3 with additional permissions (see README).
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.sim.generic import Simulator, TopLevel
# A slightly improved counter.
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.flow.actor import *
from migen.flow.transactions import *
from migen.flow.network import *
from scipy import signal
import matplotlib.pyplot as plt
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.misc import optree
from migen.sim.generic import Simulator
# Copyright (C) 2012 Vermeer Manufacturing Co.
# License: GPLv3 with additional permissions (see README).
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.sim.generic import Simulator
class Mem:
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.actor import *
from migen.genlib.buffers import ReorderBuffer
###
- tag_width = len(port.tag_call)
+ tag_width = flen(port.tag_call)
data_width = port.hub.dw
depth = len(port.slots)
rob = ReorderBuffer(tag_width, data_width, depth)
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bus import wishbone
from migen.flow.actor import *
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.record import *
from migen.genlib.fsm import *
from migen.flow.actor import *
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.actor import *
from migen.flow.transactions import *
# Simple Processor Interface
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.bank.description import *
from migen.flow.actor import *
from migen.flow.network import *
class DMAReadController(_DMAController):
def __init__(self, bus_accessor, *args, **kwargs):
- bus_aw = len(bus_accessor.address.payload.a)
- bus_dw = len(bus_accessor.data.payload.d)
+ bus_aw = flen(bus_accessor.address.payload.a)
+ bus_dw = flen(bus_accessor.data.payload.d)
_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
g = DataFlowGraph()
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.actor import *
def _rawbits_layout(l):
sigs_to = self.source.payload.flatten()
if reverse_to:
sigs_to = list(reversed(sigs_to))
- if sum(len(s) for s in sigs_from) != sum(len(s) for s in sigs_to):
+ if sum(flen(s) for s in sigs_from) != sum(flen(s) for s in sigs_to):
raise TypeError
self.comb += Cat(*sigs_to).eq(Cat(*sigs_from))
from operator import itemgetter
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bus import csr
from migen.bank.description import *
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import *
+from migen.fhdl.std import *
from migen.fhdl.tracer import get_obj_var_name
class _CSRBase(HUID):
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.misc import optree
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module, FinalizeError
+from migen.fhdl.std import *
+from migen.fhdl.module import FinalizeError
from migen.genlib.misc import optree
from migen.genlib import roundrobin
from migen.bus.transactions import *
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bus.transactions import *
from migen.bank.description import CSRStorage
from migen.genlib.record import *
]
if self._page is None:
- self.comb += port.adr.eq(self.bus.adr[word_bits:len(port.adr)])
+ self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)])
else:
pv = self._page.storage
- self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:len(port.adr)-len(pv)], pv))
+ self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv))
def get_csrs(self):
if self._page is None:
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.record import *
def phase_description(a, ba, d):
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bus.transactions import *
def _byte_mask(orig, dat_w, sel):
-from migen.fhdl.structure import bits_for
+from migen.fhdl.std import *
class Transaction:
def __init__(self, address, data=0, sel=None, busname=None):
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib import roundrobin
from migen.genlib.record import *
from migen.genlib.misc import optree
]
# mux (1-hot) slave data return
- masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
+ masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)]
self.comb += master.dat_r.eq(optree("|", masked))
class InterconnectShared(Module):
for i in range(4)]
# address and data
self.comb += [
- port.adr.eq(self.bus.adr[:len(port.adr)]),
+ port.adr.eq(self.bus.adr[:flen(port.adr)]),
self.bus.dat_r.eq(port.dat_r)
]
if not read_only:
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.bus import wishbone
from migen.genlib.fsm import FSM
from migen.genlib.misc import split, displacer, chooser
+from migen.fhdl.std import *
from migen.bus import wishbone
from migen.bus import csr
-from migen.fhdl.structure import *
from migen.genlib.misc import timeline
-class WB2CSR:
+class WB2CSR(Module):
def __init__(self):
self.wishbone = wishbone.Interface()
self.csr = csr.Interface()
- def get_fragment(self):
- sync = [
+ ###
+
+ self.sync += [
self.csr.we.eq(0),
self.csr.dat_w.eq(self.wishbone.dat_w[:csr.data_width]),
self.csr.adr.eq(self.wishbone.adr[:14]),
self.wishbone.dat_r.eq(self.csr.dat_r)
]
- sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
+ self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [
(1, [self.csr.we.eq(self.wishbone.we)]),
(2, [self.wishbone.ack.eq(1)]),
(3, [self.wishbone.ack.eq(0)])
])
- return Fragment(sync=sync)
--- /dev/null
+from migen.fhdl import structure as f
+
+def log2_int(n, need_pow2=True):
+ l = 1
+ r = 0
+ while l < n:
+ l *= 2
+ r += 1
+ if need_pow2 and l != n:
+ raise ValueError("Not a power of 2")
+ return r
+
+def bits_for(n, require_sign_bit=False):
+ if n > 0:
+ r = log2_int(n + 1, False)
+ else:
+ require_sign_bit = True
+ r = log2_int(-n, False)
+ if require_sign_bit:
+ r += 1
+ return r
+
+def value_bits_sign(v):
+ if isinstance(v, bool):
+ return 1, False
+ elif isinstance(v, int):
+ return bits_for(v), v < 0
+ elif isinstance(v, f.Signal):
+ return v.nbits, v.signed
+ elif isinstance(v, (f.ClockSignal, f.ResetSignal)):
+ return 1, False
+ elif isinstance(v, f._Operator):
+ obs = list(map(value_bits_sign, v.operands))
+ if v.op == "+" or v.op == "-":
+ if not obs[0][1] and not obs[1][1]:
+ # both operands unsigned
+ return max(obs[0][0], obs[1][0]) + 1, False
+ elif obs[0][1] and obs[1][1]:
+ # both operands signed
+ return max(obs[0][0], obs[1][0]) + 1, True
+ elif not obs[0][1] and obs[1][1]:
+ # first operand unsigned (add sign bit), second operand signed
+ return max(obs[0][0] + 1, obs[1][0]) + 1, True
+ else:
+ # first signed, second operand unsigned (add sign bit)
+ return max(obs[0][0], obs[1][0] + 1) + 1, True
+ elif v.op == "*":
+ if not obs[0][1] and not obs[1][1]:
+ # both operands unsigned
+ return obs[0][0] + obs[1][0]
+ elif obs[0][1] and obs[1][1]:
+ # both operands signed
+ return obs[0][0] + obs[1][0] - 1
+ else:
+ # one operand signed, the other unsigned (add sign bit)
+ return obs[0][0] + obs[1][0] + 1 - 1
+ elif v.op == "<<<":
+ if obs[1][1]:
+ extra = 2**(obs[1][0] - 1) - 1
+ else:
+ extra = 2**obs[1][0] - 1
+ return obs[0][0] + extra, obs[0][1]
+ elif v.op == ">>>":
+ if obs[1][1]:
+ extra = 2**(obs[1][0] - 1)
+ else:
+ extra = 0
+ return obs[0][0] + extra, obs[0][1]
+ elif v.op == "&" or v.op == "^" or v.op == "|":
+ if not obs[0][1] and not obs[1][1]:
+ # both operands unsigned
+ return max(obs[0][0], obs[1][0]), False
+ elif obs[0][1] and obs[1][1]:
+ # both operands signed
+ return max(obs[0][0], obs[1][0]), True
+ elif not obs[0][1] and obs[1][1]:
+ # first operand unsigned (add sign bit), second operand signed
+ return max(obs[0][0] + 1, obs[1][0]), True
+ else:
+ # first signed, second operand unsigned (add sign bit)
+ return max(obs[0][0], obs[1][0] + 1), True
+ elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
+ or v.op == ">" or v.op == ">=":
+ return 1, False
+ elif v.op == "~":
+ return obs[0]
+ else:
+ raise TypeError
+ elif isinstance(v, f._Slice):
+ return v.stop - v.start, value_bits_sign(v.value)[1]
+ elif isinstance(v, f.Cat):
+ return sum(value_bits_sign(sv)[0] for sv in v.l), False
+ elif isinstance(v, f.Replicate):
+ return (value_bits_sign(v.v)[0])*v.n, False
+ elif isinstance(v, f._ArrayProxy):
+ bsc = map(value_bits_sign, v.choices)
+ return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
+ else:
+ raise TypeError
+
+def flen(v):
+ return value_bits_sign(v)[0]
from migen.fhdl.structure import *
+from migen.fhdl.size import bits_for, value_bits_sign
from migen.fhdl.tools import *
from migen.fhdl.tracer import get_obj_var_name
from migen.fhdl.verilog import _printexpr as verilog_printexpr
--- /dev/null
+from migen.fhdl.structure import *
+from migen.fhdl.module import Module
+from migen.fhdl.specials import TSTriple, Instance, Memory
+from migen.fhdl.size import log2_int, bits_for, flen
from migen.fhdl import tracer
-def log2_int(n, need_pow2=True):
- l = 1
- r = 0
- while l < n:
- l *= 2
- r += 1
- if need_pow2 and l != n:
- raise ValueError("Not a power of 2")
- return r
-
-def bits_for(n, require_sign_bit=False):
- if n > 0:
- r = log2_int(n + 1, False)
- else:
- require_sign_bit = True
- r = log2_int(-n, False)
- if require_sign_bit:
- r += 1
- return r
-
class HUID:
__next_uid = 0
def __init__(self):
def __getitem__(self, key):
+ from migen.fhdl.size import flen
+
if isinstance(key, int):
if key < 0:
- key += len(self)
+ key += flen(self)
return _Slice(self, key, key+1)
elif isinstance(key, slice):
start = key.start or 0
- stop = key.stop or len(self)
+ stop = key.stop or flen(self)
if start < 0:
- start += len(self)
+ start += flen(self)
if stop < 0:
- stop += len(self)
- if stop > len(self):
- stop = len(self)
+ stop += flen(self)
+ if stop > flen(self):
+ stop = flen(self)
if key.step != None:
raise KeyError
return _Slice(self, start, stop)
def eq(self, r):
return _Assign(self, r)
-
- def __len__(self):
- return value_bits_sign(self)[0]
def __hash__(self):
return HUID.__hash__(self)
class Signal(Value):
def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None):
+ from migen.fhdl.size import bits_for
+
Value.__init__(self)
# determine number of bits and signedness
self.clock_domains + other.clock_domains,
self.sim + other.sim)
-def value_bits_sign(v):
- if isinstance(v, bool):
- return 1, False
- elif isinstance(v, int):
- return bits_for(v), v < 0
- elif isinstance(v, Signal):
- return v.nbits, v.signed
- elif isinstance(v, (ClockSignal, ResetSignal)):
- return 1, False
- elif isinstance(v, _Operator):
- obs = list(map(value_bits_sign, v.operands))
- if v.op == "+" or v.op == "-":
- if not obs[0][1] and not obs[1][1]:
- # both operands unsigned
- return max(obs[0][0], obs[1][0]) + 1, False
- elif obs[0][1] and obs[1][1]:
- # both operands signed
- return max(obs[0][0], obs[1][0]) + 1, True
- elif not obs[0][1] and obs[1][1]:
- # first operand unsigned (add sign bit), second operand signed
- return max(obs[0][0] + 1, obs[1][0]) + 1, True
- else:
- # first signed, second operand unsigned (add sign bit)
- return max(obs[0][0], obs[1][0] + 1) + 1, True
- elif v.op == "*":
- if not obs[0][1] and not obs[1][1]:
- # both operands unsigned
- return obs[0][0] + obs[1][0]
- elif obs[0][1] and obs[1][1]:
- # both operands signed
- return obs[0][0] + obs[1][0] - 1
- else:
- # one operand signed, the other unsigned (add sign bit)
- return obs[0][0] + obs[1][0] + 1 - 1
- elif v.op == "<<<":
- if obs[1][1]:
- extra = 2**(obs[1][0] - 1) - 1
- else:
- extra = 2**obs[1][0] - 1
- return obs[0][0] + extra, obs[0][1]
- elif v.op == ">>>":
- if obs[1][1]:
- extra = 2**(obs[1][0] - 1)
- else:
- extra = 0
- return obs[0][0] + extra, obs[0][1]
- elif v.op == "&" or v.op == "^" or v.op == "|":
- if not obs[0][1] and not obs[1][1]:
- # both operands unsigned
- return max(obs[0][0], obs[1][0]), False
- elif obs[0][1] and obs[1][1]:
- # both operands signed
- return max(obs[0][0], obs[1][0]), True
- elif not obs[0][1] and obs[1][1]:
- # first operand unsigned (add sign bit), second operand signed
- return max(obs[0][0] + 1, obs[1][0]), True
- else:
- # first signed, second operand unsigned (add sign bit)
- return max(obs[0][0], obs[1][0] + 1), True
- elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \
- or v.op == ">" or v.op == ">=":
- return 1, False
- elif v.op == "~":
- return obs[0]
- else:
- raise TypeError
- elif isinstance(v, _Slice):
- return v.stop - v.start, value_bits_sign(v.value)[1]
- elif isinstance(v, Cat):
- return sum(value_bits_sign(sv)[0] for sv in v.l), False
- elif isinstance(v, Replicate):
- return (value_bits_sign(v.v)[0])*v.n, False
- elif isinstance(v, _ArrayProxy):
- bsc = map(value_bits_sign, v.choices)
- return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc)
- else:
- raise TypeError
from migen.fhdl.structure import *
from migen.fhdl.structure import _Slice, _Assign
from migen.fhdl.visit import NodeVisitor, NodeTransformer
+from migen.fhdl.size import value_bits_sign
def bitreverse(s):
length, signed = value_bits_sign(s)
from migen.fhdl.structure import *
from migen.fhdl.structure import _Operator, _Slice, _Assign
from migen.fhdl.tools import *
+from migen.fhdl.size import bits_for, flen
from migen.fhdl.namer import Namespace, build_namespace
def _printsig(ns, s):
n = "signed "
else:
n = ""
- if len(s) > 1:
- n += "[" + str(len(s)-1) + ":0] "
+ if flen(s) > 1:
+ n += "[" + str(flen(s)-1) + ":0] "
n += ns.get_name(s)
return n
elif isinstance(node, _Slice):
# Verilog does not like us slicing non-array signals...
if isinstance(node.value, Signal) \
- and len(node.value) == 1 \
+ and flen(node.value) == 1 \
and node.start == 0 and node.stop == 1:
return _printexpr(ns, node.value)
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.misc import optree
from migen.genlib.record import *
from collections import defaultdict
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.actor import *
class EndpointSimHook(Module):
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.bank.description import *
from migen.flow.hooks import DFGHook
from networkx import MultiDiGraph
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.genlib.misc import optree
from migen.flow.actor import *
from migen.flow import plumbing
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.flow.actor import *
from migen.genlib.record import *
from migen.genlib.misc import optree
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
class ReorderSlot:
def __init__(self, tag_width, data_width):
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
+from migen.fhdl.size import value_bits_sign
from migen.fhdl.specials import Special
from migen.fhdl.tools import list_signals
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
class Complex:
def __init__(self, real, imag):
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-class Divider:
+class Divider(Module):
def __init__(self, w):
- self.w = w
-
self.start_i = Signal()
self.dividend_i = Signal(w)
self.divisor_i = Signal(w)
self.quotient_o = Signal(w)
self.remainder_o = Signal(w)
- def get_fragment(self):
- w = self.w
+ ###
qr = Signal(2*w)
counter = Signal(max=w+1)
divisor_r = Signal(w)
diff = Signal(w+1)
- comb = [
+ self.comb += [
self.quotient_o.eq(qr[:w]),
self.remainder_o.eq(qr[w:]),
self.ready_o.eq(counter == 0),
diff.eq(self.remainder_o - divisor_r)
]
- sync = [
+ self.sync += [
If(self.start_i,
counter.eq(w),
qr.eq(self.dividend_i),
counter.eq(counter - 1)
)
]
- return Fragment(comb, sync)
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
def _inc(signal, modulo):
- if modulo == 2**len(signal):
+ if modulo == 2**flen(signal):
return signal.eq(signal + 1)
else:
return If(signal == (modulo - 1),
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
class FSM:
def __init__(self, *states, delayed_enters=[]):
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.flow.actor import *
from migen.flow.actor import _Endpoint
from migen.flow.transactions import *
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.fhdl.structure import _Operator
def optree(op, operands, lb=None, ub=None, default=None):
def displacer(signal, shift, output, n=None, reverse=False):
if n is None:
- n = 2**len(shift)
- w = len(signal)
+ n = 2**flen(shift)
+ w = flen(signal)
if reverse:
r = reversed(range(n))
else:
def chooser(signal, shift, output, n=None, reverse=False):
if n is None:
- n = 2**len(shift)
- w = len(output)
+ n = 2**flen(shift)
+ w = flen(output)
cases = {}
for i in range(n):
if reverse:
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
from migen.fhdl.tracer import get_obj_var_name
from migen.genlib.misc import optree
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
(SP_WITHDRAW, SP_CE) = range(2)
-class RoundRobin:
+class RoundRobin(Module):
def __init__(self, n, switch_policy=SP_WITHDRAW):
- self.n = n
- self.request = Signal(self.n)
- self.grant = Signal(max=self.n)
+ self.request = Signal(n)
+ self.grant = Signal(max=n)
self.switch_policy = switch_policy
if self.switch_policy == SP_CE:
self.ce = Signal()
- def get_fragment(self):
- if self.n > 1:
+ ###
+
+ if n > 1:
cases = {}
- for i in range(self.n):
+ for i in range(n):
switch = []
- for j in reversed(range(i+1,i+self.n)):
- t = j % self.n
+ for j in reversed(range(i+1,i+n)):
+ t = j % n
switch = [
If(self.request[t],
self.grant.eq(t)
statement = Case(self.grant, cases)
if self.switch_policy == SP_CE:
statement = If(self.ce, statement)
- return Fragment(sync=[statement])
+ self.sync += statement
else:
- return Fragment([self.grant.eq(0)])
+ self.comb += self.grant.eq(0)
import ast
from itertools import zip_longest
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.flow.actor import Source, Sink
from migen.flow.transactions import *
from migen.bus import wishbone
from operator import itemgetter
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
from migen.fhdl import visit as fhdl
class AbstractLoad:
-# Copyright (C) 2012 Vermeer Manufacturing Co.
-# License: GPLv3 with additional permissions (see README).
-
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
+from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.sim.ipc import *
from migen.sim import icarus
nbits = item.width
else:
signed = item.signed
- nbits = len(item)
+ nbits = flen(item)
value = reply.value & (2**nbits - 1)
if signed and (value & 2**(nbits - 1)):
value -= 2**nbits
if isinstance(item, Memory):
nbits = item.width
else:
- nbits = len(item)
+ nbits = flen(item)
if value < 0:
value += 2**nbits
assert(value >= 0 and value < 2**nbits)
projects / litex.git / commitdiff