O3: Update regressions for mem block caching change.
authorAli Saidi <Ali.Saidi@ARM.com>
Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)
committerAli Saidi <Ali.Saidi@ARM.com>
Fri, 18 Mar 2011 00:20:19 +0000 (19:20 -0500)
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

index b96a832864f3df484521663593a470611ba9f8bf..80aefb4cf7169500602c28eca9e441ec471ccbca 100644 (file)
@@ -10,12 +10,12 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -142,6 +142,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -440,6 +441,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -573,6 +575,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -871,6 +874,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -922,7 +926,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -942,7 +946,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -967,6 +971,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -998,6 +1003,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
@@ -1068,7 +1074,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
index dcb4e3644909851fdfe7ad7c42541616f10989ea..66e1dd01f6102cd9863f80baa4c22fa1e0402543 100755 (executable)
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Mar 15 2011 18:10:57
+M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip
+M5 started Mar 15 2011 18:10:59
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 118370500
-Exiting @ tick 1900831034500 because m5_exit instruction encountered
+Exiting @ tick 1900831106500 because m5_exit instruction encountered
index 3a665541f5d8d283a1e7a45d8ea96f20d2f274c5..6dbfe53f2160b9f5d85d4f5ff29bf91161687391 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  67358                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 313516                       # Number of bytes of host memory used
-host_seconds                                   846.09                       # Real time elapsed on the host
-host_tick_rate                             2246601111                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 185731                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 330796                       # Number of bytes of host memory used
+host_seconds                                   306.85                       # Real time elapsed on the host
+host_tick_rate                             6194726969                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    56990797                       # Number of instructions simulated
+sim_insts                                    56990828                       # Number of instructions simulated
 sim_seconds                                  1.900831                       # Number of seconds simulated
-sim_ticks                                1900831034500                       # Number of ticks simulated
+sim_ticks                                1900831106500                       # Number of ticks simulated
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.BTBHits                 5875698                       # Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups             11164328                       # Number of BTB lookups
-system.cpu0.BPredUnit.RASInCorrect              27744                       # Number of incorrect RAS predictions.
-system.cpu0.BPredUnit.condIncorrect            509294                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted          10430748                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups                12489171                       # Number of BP lookups
-system.cpu0.BPredUnit.usedRAS                  879952                       # Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches               7522146                       # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events           923087                       # number cycles where commit BW limit reached
+system.cpu0.BPredUnit.BTBHits                 5875746                       # Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups             11164335                       # Number of BTB lookups
+system.cpu0.BPredUnit.RASInCorrect              27734                       # Number of incorrect RAS predictions.
+system.cpu0.BPredUnit.condIncorrect            509345                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.condPredicted          10431005                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups                12489231                       # Number of BP lookups
+system.cpu0.BPredUnit.usedRAS                  879926                       # Number of times the RAS was used to get a target.
+system.cpu0.commit.COM:branches               7522155                       # Number of branches committed
+system.cpu0.commit.COM:bw_lim_events           922955                       # number cycles where commit BW limit reached
 system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples     78252168                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean     0.636069                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev     1.403085                       # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples     78251630                       # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean     0.636074                       # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev     1.403101                       # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0     56997236     72.84%     72.84% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1      9310198     11.90%     84.74% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2      5423748      6.93%     91.67% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3      2443659      3.12%     94.79% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4      1857092      2.37%     97.16% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5       632524      0.81%     97.97% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6       342942      0.44%     98.41% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7       321682      0.41%     98.82% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8       923087      1.18%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0     56997001     72.84%     72.84% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1      9309948     11.90%     84.74% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2      5423861      6.93%     91.67% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3      2443172      3.12%     94.79% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4      1857246      2.37%     97.16% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::5       632479      0.81%     97.97% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::6       343172      0.44%     98.41% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::7       321796      0.41%     98.82% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::8       922955      1.18%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total     78252168                       # Number of insts commited each cycle
-system.cpu0.commit.COM:count                 49773781                       # Number of instructions committed
+system.cpu0.commit.COM:committed_per_cycle::total     78251630                       # Number of insts commited each cycle
+system.cpu0.commit.COM:count                 49773809                       # Number of instructions committed
 system.cpu0.commit.COM:fp_insts                245595                       # Number of committed floating point instructions.
-system.cpu0.commit.COM:function_calls          636046                       # Number of function calls committed.
-system.cpu0.commit.COM:int_insts             46098576                       # Number of committed integer instructions.
-system.cpu0.commit.COM:loads                  7894849                       # Number of loads committed
+system.cpu0.commit.COM:function_calls          636047                       # Number of function calls committed.
+system.cpu0.commit.COM:int_insts             46098602                       # Number of committed integer instructions.
+system.cpu0.commit.COM:loads                  7894859                       # Number of loads committed
 system.cpu0.commit.COM:membars                 191655                       # Number of memory barriers committed
-system.cpu0.commit.COM:refs                  13318728                       # Number of memory references committed
+system.cpu0.commit.COM:refs                  13318738                       # Number of memory references committed
 system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts           652792                       # The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts      49773781                       # The number of committed instructions
-system.cpu0.commit.commitNonSpecStalls         564764                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts        7279166                       # The number of squashed insts skipped by commit
-system.cpu0.committedInsts                   46913211                       # Number of Instructions Simulated
-system.cpu0.committedInsts_total             46913211                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.403631                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.403631                       # CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses::0       178258                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       178258                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14381.476316                       # average LoadLockedReq miss latency
+system.cpu0.commit.branchMispredicts           652841                       # The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts      49773809                       # The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls         564763                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts        7279602                       # The number of squashed insts skipped by commit
+system.cpu0.committedInsts                   46913237                       # Number of Instructions Simulated
+system.cpu0.committedInsts_total             46913237                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.403611                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.403611                       # CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses::0       178261                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       178261                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.272201                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10558.033333                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0       158899                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       158899                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency    278411000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.108601                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0        19359                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19359                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_hits         4359                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    158370500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084148                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10560.425277                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits::0       158904                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       158904                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency    278417000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.108588                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0        19357                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        19357                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_hits         4355                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    158427500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084157                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        15000                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0        8018067                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8018067                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.598189                       # average ReadReq miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses        15002                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses::0        8017759                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8017759                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 23757.902186                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.786651                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.503104                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0            6640677                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6640677                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency   32719346000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0      0.171786                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0          1377390                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1377390                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits           392262                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency  23413327000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122864                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_hits::0            6640640                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6640640                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency   32717458500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate::0      0.171759                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0          1377119                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1377119                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits           391971                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency  23413523000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122871                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses         985128                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    920863000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_misses         985148                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    920844000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.StoreCondReq_accesses::0       185114                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       185114                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13329.315068                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13326.438356                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10326.164384                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10323.150685                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_hits::0        181464                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       181464                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency     48652000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency     48641500                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_rate::0     0.019718                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_misses::0         3650                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total         3650                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency     37690500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency     37679500                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.019718                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_misses         3650                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.WriteReq_accesses::0       5223711                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total      5223711                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 32400.753552                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 32402.197389                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.522294                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.574400                       # average WriteReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::0           3606992                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3606992                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency  52382913882                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::0     0.309496                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0         1616719                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1616719                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits         1353304                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency   8058002430                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.050427                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_hits::0           3607020                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3607020                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency  52384340899                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate::0     0.309491                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0         1616691                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1616691                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits         1353284                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency   8057771431                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.050425                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses        263415                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1320187498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8768.456221                       # average number of cycles each access was blocked
+system.cpu0.dcache.WriteReq_mshr_misses        263407                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1320171998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8769.741125                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs                  8.499270                       # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs            83762                       # number of cycles access was blocked
+system.cpu0.dcache.avg_refs                  8.499136                       # Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs            83743                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs    734463430                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs    734404431                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets       150500                       # number of cycles access was blocked
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses::0        13241778                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::0        13241470                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     13241778                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 28423.233717                       # average overall miss latency
+system.cpu0.dcache.demand_accesses::total     13241470                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 28425.918612                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.444175                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0            10247669                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.173882                       # average overall mshr miss latency
+system.cpu0.dcache.demand_hits::0            10247660                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10247669                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency    85102259882                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0       0.226111                       # miss rate for demand accesses
+system.cpu0.dcache.demand_hits::total        10247660                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency    85101799399                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate::0       0.226093                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0           2994109                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::0           2993810                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2994109                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits           1745566                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency  31471329430                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.094288                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_misses::total       2993810                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits           1745255                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency  31471294431                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate::0     0.094291                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses         1248543                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses         1248555                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0                  0.973184                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_%::0                  0.973190                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_%::1                 -0.001953                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0           498.270236                       # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::0           498.273055                       # Average occupied blocks per context
 system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses::0       13241778                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::0       13241470                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     13241778                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency::0 28423.233717                       # average overall miss latency
+system.cpu0.dcache.overall_accesses::total     13241470                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency::0 28425.918612                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.444175                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.173882                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0           10247669                       # number of overall hits
+system.cpu0.dcache.overall_hits::0           10247660                       # number of overall hits
 system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10247669                       # number of overall hits
-system.cpu0.dcache.overall_miss_latency   85102259882                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0      0.226111                       # miss rate for overall accesses
+system.cpu0.dcache.overall_hits::total       10247660                       # number of overall hits
+system.cpu0.dcache.overall_miss_latency   85101799399                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate::0      0.226093                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0          2994109                       # number of overall misses
+system.cpu0.dcache.overall_misses::0          2993810                       # number of overall misses
 system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2994109                       # number of overall misses
-system.cpu0.dcache.overall_mshr_hits          1745566                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency  31471329430                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.094288                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_misses::total      2993810                       # number of overall misses
+system.cpu0.dcache.overall_mshr_hits          1745255                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency  31471294431                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate::0     0.094291                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses        1248543                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2241050498                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_misses        1248555                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency   2241015998                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements               1246737                       # number of replacements
-system.cpu0.dcache.sampled_refs               1247249                       # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements               1246755                       # number of replacements
+system.cpu0.dcache.sampled_refs               1247267                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse               497.270236                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                10600706                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               497.273055                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                10600692                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks                  721582                       # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles      33790460                       # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:BranchMispred         33337                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DECODE:BranchResolved       520850                       # Number of times decode resolved a branch
-system.cpu0.decode.DECODE:DecodedInsts       62592464                       # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles         32176672                       # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles          11304141                       # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles        1271125                       # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:SquashedInsts        100674                       # Number of squashed instructions handled by decode
-system.cpu0.decode.DECODE:UnblockCycles        980894                       # Number of cycles decode is unblocking
-system.cpu0.dtb.data_accesses                  795039                       # DTB accesses
-system.cpu0.dtb.data_acv                          690                       # DTB access violations
-system.cpu0.dtb.data_hits                    14240441                       # DTB hits
-system.cpu0.dtb.data_misses                     32243                       # DTB misses
+system.cpu0.dcache.writebacks                  721595                       # number of writebacks
+system.cpu0.decode.DECODE:BlockedCycles      33789769                       # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:BranchMispred         33336                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DECODE:BranchResolved       520770                       # Number of times decode resolved a branch
+system.cpu0.decode.DECODE:DecodedInsts       62593203                       # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles         32176765                       # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles          11304168                       # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles        1271210                       # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:SquashedInsts        100660                       # Number of squashed instructions handled by decode
+system.cpu0.decode.DECODE:UnblockCycles        980927                       # Number of cycles decode is unblocking
+system.cpu0.dtb.data_accesses                  794756                       # DTB accesses
+system.cpu0.dtb.data_acv                          688                       # DTB access violations
+system.cpu0.dtb.data_hits                    14240512                       # DTB hits
+system.cpu0.dtb.data_misses                     32288                       # DTB misses
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.read_accesses                  599364                       # DTB read accesses
-system.cpu0.dtb.read_acv                          521                       # DTB read access violations
-system.cpu0.dtb.read_hits                     8656203                       # DTB read hits
-system.cpu0.dtb.read_misses                     26609                       # DTB read misses
-system.cpu0.dtb.write_accesses                 195675                       # DTB write accesses
+system.cpu0.dtb.read_accesses                  599054                       # DTB read accesses
+system.cpu0.dtb.read_acv                          519                       # DTB read access violations
+system.cpu0.dtb.read_hits                     8656143                       # DTB read hits
+system.cpu0.dtb.read_misses                     26649                       # DTB read misses
+system.cpu0.dtb.write_accesses                 195702                       # DTB write accesses
 system.cpu0.dtb.write_acv                         169                       # DTB write access violations
-system.cpu0.dtb.write_hits                    5584238                       # DTB write hits
-system.cpu0.dtb.write_misses                     5634                       # DTB write misses
-system.cpu0.fetch.Branches                   12489171                       # Number of branches that fetch encountered
-system.cpu0.fetch.CacheLines                  7790772                       # Number of cache lines fetched
-system.cpu0.fetch.Cycles                     12447663                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.IcacheSquashes               374479                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.Insts                      63679882                       # Number of instructions fetch has processed
-system.cpu0.fetch.MiscStallCycles               30613                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.SquashCycles                 745308                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.branchRate                 0.110757                       # Number of branch fetches per cycle
-system.cpu0.fetch.icacheStallCycles           7790769                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.predictedBranches           6755650                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.rate                       0.564728                       # Number of inst fetches per cycle
-system.cpu0.fetch.rateDist::samples          79523293                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.800770                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.103978                       # Number of instructions fetched each cycle (Total)
+system.cpu0.dtb.write_hits                    5584369                       # DTB write hits
+system.cpu0.dtb.write_misses                     5639                       # DTB write misses
+system.cpu0.fetch.Branches                   12489231                       # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines                  7790870                       # Number of cache lines fetched
+system.cpu0.fetch.Cycles                     12447773                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes               374462                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts                      63680808                       # Number of instructions fetch has processed
+system.cpu0.fetch.MiscStallCycles               30775                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.SquashCycles                 745389                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate                 0.110758                       # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles           7790867                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches           6755672                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate                       0.564741                       # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist::samples          79522840                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.800786                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.103997                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                67075630     84.35%     84.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  894785      1.13%     85.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1774565      2.23%     87.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  813228      1.02%     88.73% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2745570      3.45%     92.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  583311      0.73%     92.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  681126      0.86%     93.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  829932      1.04%     94.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4125146      5.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                67075067     84.35%     84.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  894690      1.13%     85.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1774768      2.23%     87.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  813051      1.02%     88.73% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2745482      3.45%     92.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  583376      0.73%     92.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  681368      0.86%     93.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  829891      1.04%     94.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4125147      5.19%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            79523293                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fp_regfile_reads                   120916                       # number of floating regfile reads
+system.cpu0.fetch.rateDist::total            79522840                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fp_regfile_reads                   120909                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                  122710                       # number of floating regfile writes
-system.cpu0.icache.ReadReq_accesses::0        7790772                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7790772                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_accesses::0        7790870                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7790870                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.877874                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.512006                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits::0            6933292                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        6933292                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency   12919571500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate::0      0.110064                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses::0           857480                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       857480                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_hits            36653                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_miss_latency   9863477500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.105359                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.582299                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits::0            6933419                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6933419                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency   12919109500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate::0      0.110058                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses::0           857451                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       857451                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_hits            36636                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_miss_latency   9863391000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.105356                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses         820827                       # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 11372.727273                       # average number of cycles each access was blocked
+system.cpu0.icache.ReadReq_mshr_misses         820815                       # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 11214.285714                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs                  8.447909                       # Average number of references to valid blocks.
-system.cpu0.icache.blocked::no_mshrs               55                       # number of cycles access was blocked
+system.cpu0.icache.avg_refs                  8.448187                       # Average number of references to valid blocks.
+system.cpu0.icache.blocked::no_mshrs               56                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs       625500                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_mshrs       628000                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses::0         7790772                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::0         7790870                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7790772                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency::0 15066.907100                       # average overall miss latency
+system.cpu0.icache.demand_accesses::total      7790870                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency::0 15066.877874                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 12016.512006                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits::0             6933292                       # number of demand (read+write) hits
+system.cpu0.icache.demand_avg_mshr_miss_latency 12016.582299                       # average overall mshr miss latency
+system.cpu0.icache.demand_hits::0             6933419                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         6933292                       # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency    12919571500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate::0       0.110064                       # miss rate for demand accesses
+system.cpu0.icache.demand_hits::total         6933419                       # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency    12919109500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate::0       0.110058                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses::0            857480                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::0            857451                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        857480                       # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits             36653                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency   9863477500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate::0     0.105359                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_misses::total        857451                       # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits             36636                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency   9863391000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate::0     0.105356                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses          820827                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses          820815                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.occ_%::0                  0.995823                       # Average percentage of cache occupancy
 system.cpu0.icache.occ_blocks::0           509.861442                       # Average occupied blocks per context
-system.cpu0.icache.overall_accesses::0        7790772                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::0        7790870                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7790772                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency::0 15066.907100                       # average overall miss latency
+system.cpu0.icache.overall_accesses::total      7790870                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency::0 15066.877874                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 12016.512006                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 12016.582299                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits::0            6933292                       # number of overall hits
+system.cpu0.icache.overall_hits::0            6933419                       # number of overall hits
 system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.icache.overall_hits::total        6933292                       # number of overall hits
-system.cpu0.icache.overall_miss_latency   12919571500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate::0      0.110064                       # miss rate for overall accesses
+system.cpu0.icache.overall_hits::total        6933419                       # number of overall hits
+system.cpu0.icache.overall_miss_latency   12919109500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate::0      0.110058                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses::0           857480                       # number of overall misses
+system.cpu0.icache.overall_misses::0           857451                       # number of overall misses
 system.cpu0.icache.overall_misses::1                0                       # number of overall misses
-system.cpu0.icache.overall_misses::total       857480                       # number of overall misses
-system.cpu0.icache.overall_mshr_hits            36653                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency   9863477500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate::0     0.105359                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_misses::total       857451                       # number of overall misses
+system.cpu0.icache.overall_mshr_hits            36636                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency   9863391000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate::0     0.105356                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses         820827                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses         820815                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements                820200                       # number of replacements
-system.cpu0.icache.sampled_refs                820711                       # Sample count of references to valid blocks.
+system.cpu0.icache.replacements                820188                       # number of replacements
+system.cpu0.icache.sampled_refs                820699                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu0.icache.tagsinuse               509.861442                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 6933292                       # Total number of references to valid blocks.
+system.cpu0.icache.total_refs                 6933419                       # Total number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           24435382000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks                     107                       # number of writebacks
-system.cpu0.idleCycles                       33238734                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.iew.EXEC:branches                 8088887                       # Number of branches executed
-system.cpu0.iew.EXEC:nop                      3190702                       # number of nop insts executed
+system.cpu0.icache.writebacks                     160                       # number of writebacks
+system.cpu0.idleCycles                       33238338                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.iew.EXEC:branches                 8088609                       # Number of branches executed
+system.cpu0.iew.EXEC:nop                      3190653                       # number of nop insts executed
 system.cpu0.iew.EXEC:rate                    0.446643                       # Inst execution rate
-system.cpu0.iew.EXEC:refs                    14307235                       # number of memory reference insts executed
-system.cpu0.iew.EXEC:stores                   5602635                       # Number of stores executed
+system.cpu0.iew.EXEC:refs                    14307346                       # number of memory reference insts executed
+system.cpu0.iew.EXEC:stores                   5602769                       # Number of stores executed
 system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu0.iew.WB:consumers                 31606218                       # num instructions consuming a value
-system.cpu0.iew.WB:count                     49988672                       # cumulative count of insts written-back
-system.cpu0.iew.WB:fanout                    0.757998                       # average fanout of values written-back
+system.cpu0.iew.WB:consumers                 31606079                       # num instructions consuming a value
+system.cpu0.iew.WB:count                     49988014                       # cumulative count of insts written-back
+system.cpu0.iew.WB:fanout                    0.757991                       # average fanout of values written-back
 system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
 system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.iew.WB:producers                 23957449                       # num instructions producing a value
-system.cpu0.iew.WB:rate                      0.443311                       # insts written-back per cycle
-system.cpu0.iew.WB:sent                      50070625                       # cumulative count of insts sent to commit
-system.cpu0.iew.branchMispredicts              711853                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewBlockCycles                9019183                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewDispLoadInsts              9134564                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispNonSpecInsts           1512032                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewDispSquashedInsts           755923                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispStoreInsts             5843380                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispatchedInsts           57163450                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewExecLoadInsts              8704600                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           462366                       # Number of squashed instructions skipped in execute
-system.cpu0.iew.iewExecutedInsts             50364381                       # Number of executed instructions
-system.cpu0.iew.iewIQFullEvents                 59583                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.WB:producers                 23957137                       # num instructions producing a value
+system.cpu0.iew.WB:rate                      0.443309                       # insts written-back per cycle
+system.cpu0.iew.WB:sent                      50069991                       # cumulative count of insts sent to commit
+system.cpu0.iew.branchMispredicts              711883                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewBlockCycles                9018658                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewDispLoadInsts              9134985                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispNonSpecInsts           1511781                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispSquashedInsts           755973                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispStoreInsts             5843371                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispatchedInsts           57163675                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewExecLoadInsts              8704577                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           462590                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts             50363992                       # Number of executed instructions
+system.cpu0.iew.iewIQFullEvents                 59575                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewLSQFullEvents                 7004                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.iewSquashCycles               1271125                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewUnblockCycles               547384                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewLSQFullEvents                 7002                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles               1271210                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewUnblockCycles               547356                       # Number of cycles IEW is unblocking
 system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread.0.cacheBlocked       122021                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.lsq.thread.0.forwLoads         410783                       # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread.0.ignoredResponses        10667                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread.0.cacheBlocked       122264                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.forwLoads         410769                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread.0.ignoredResponses        10661                       # Number of memory responses ignored because the instruction is squashed
 system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread.0.memOrderViolation        38522                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread.0.rescheduledLoads        18606                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread.0.squashedLoads      1239715                       # Number of loads squashed
-system.cpu0.iew.lsq.thread.0.squashedStores       419501                       # Number of stores squashed
-system.cpu0.iew.memOrderViolationEvents         38522                       # Number of memory order violations
-system.cpu0.iew.predictedNotTakenIncorrect       332064                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.predictedTakenIncorrect        379789                       # Number of branches that were predicted taken incorrectly
-system.cpu0.int_regfile_reads                66329266                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               36276231                       # number of integer regfile writes
-system.cpu0.ipc                              0.416037                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.416037                       # IPC: Total IPC of All Threads
+system.cpu0.iew.lsq.thread.0.memOrderViolation        38527                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread.0.rescheduledLoads        18607                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread.0.squashedLoads      1240126                       # Number of loads squashed
+system.cpu0.iew.lsq.thread.0.squashedStores       419492                       # Number of stores squashed
+system.cpu0.iew.memOrderViolationEvents         38527                       # Number of memory order violations
+system.cpu0.iew.predictedNotTakenIncorrect       332123                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect        379760                       # Number of branches that were predicted taken incorrectly
+system.cpu0.int_regfile_reads                66329017                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               36275514                       # number of integer regfile writes
+system.cpu0.ipc                              0.416041                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.416041                       # IPC: Total IPC of All Threads
 system.cpu0.iq.ISSUE:FU_type_0::No_OpClass         3762      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntAlu       35322205     69.50%     69.50% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntMult         55712      0.11%     69.61% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntAlu       35321880     69.49%     69.50% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntMult         55711      0.11%     69.61% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     69.61% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::FloatAdd        15323      0.03%     69.64% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     69.64% # Type of FU issued
@@ -417,15 +417,15 @@ system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     69.65%
 system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     69.65% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     69.65% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     69.65% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemRead       9003021     17.71%     87.36% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemWrite      5645656     11.11%     98.47% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IprAccess       779190      1.53%    100.00% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemRead       9003030     17.71%     87.36% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemWrite      5645816     11.11%     98.47% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IprAccess       779182      1.53%    100.00% # Type of FU issued
 system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::total        50826749                       # Type of FU issued
-system.cpu0.iq.ISSUE:fu_busy_cnt               382289                       # FU busy when requested
+system.cpu0.iq.ISSUE:FU_type_0::total        50826584                       # Type of FU issued
+system.cpu0.iq.ISSUE:fu_busy_cnt               382291                       # FU busy when requested
 system.cpu0.iq.ISSUE:fu_busy_rate            0.007521                       # FU busy rate (busy events/executed inst)
 system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntAlu            40958     10.71%     10.71% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntAlu            40945     10.71%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     10.71% # attempts to use FU when none available
@@ -454,51 +454,51 @@ system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     10.71% #
 system.cpu0.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     10.71% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     10.71% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemRead          226307     59.20%     69.91% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemWrite         115024     30.09%    100.00% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemRead          226304     59.20%     69.91% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemWrite         115042     30.09%    100.00% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples     79523293                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.639143                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.209985                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::samples     79522840                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.639144                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.209964                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0     54765331     68.87%     68.87% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1     12086611     15.20%     84.07% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2      5449422      6.85%     90.92% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3      3416951      4.30%     95.22% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::4      2222762      2.80%     98.01% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5       992615      1.25%     99.26% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::6       434574      0.55%     99.81% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::7       111342      0.14%     99.95% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::8        43685      0.05%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::0     54765189     68.87%     68.87% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::1     12085919     15.20%     84.07% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::2      5449520      6.85%     90.92% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::3      3416832      4.30%     95.21% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::4      2223696      2.80%     98.01% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::5       992162      1.25%     99.26% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::6       434798      0.55%     99.81% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::7       111045      0.14%     99.95% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::8        43679      0.05%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total     79523293                       # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate                    0.450743                       # Inst issue rate
-system.cpu0.iq.fp_alu_accesses                 260476                       # Number of floating point alu accesses
-system.cpu0.iq.fp_inst_queue_reads             508189                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       246844                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_writes            251997                       # Number of floating instruction queue writes
-system.cpu0.iq.int_alu_accesses              50944800                       # Number of integer alu accesses
-system.cpu0.iq.int_inst_queue_reads         181074941                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_wakeup_accesses     49741828                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.int_inst_queue_writes         60494151                       # Number of integer instruction queue writes
-system.cpu0.iq.iqInstsAdded                  52250537                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqInstsIssued                 50826749                       # Number of instructions issued
-system.cpu0.iq.iqNonSpecInstsAdded            1722211                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqSquashedInstsExamined        6740578                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedInstsIssued            24052                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedNonSpecRemoved       1157447                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.iqSquashedOperandsExamined      3424469                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.ISSUE:issued_per_cycle::total     79522840                       # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:rate                    0.450745                       # Inst issue rate
+system.cpu0.iq.fp_alu_accesses                 260468                       # Number of floating point alu accesses
+system.cpu0.iq.fp_inst_queue_reads             508171                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       246837                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_writes            251931                       # Number of floating instruction queue writes
+system.cpu0.iq.int_alu_accesses              50944645                       # Number of integer alu accesses
+system.cpu0.iq.int_inst_queue_reads         181074223                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_wakeup_accesses     49741177                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.int_inst_queue_writes         60494022                       # Number of integer instruction queue writes
+system.cpu0.iq.iqInstsAdded                  52251057                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued                 50826584                       # Number of instructions issued
+system.cpu0.iq.iqNonSpecInstsAdded            1721965                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqSquashedInstsExamined        6740106                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued            24097                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedNonSpecRemoved       1157202                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedOperandsExamined      3425536                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_hits                           0                       # DTB hits
 system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.fetch_accesses                 951927                       # ITB accesses
-system.cpu0.itb.fetch_acv                         732                       # ITB acv
-system.cpu0.itb.fetch_hits                     922973                       # ITB hits
-system.cpu0.itb.fetch_misses                    28954                       # ITB misses
+system.cpu0.itb.fetch_accesses                 951932                       # ITB accesses
+system.cpu0.itb.fetch_acv                         733                       # ITB acv
+system.cpu0.itb.fetch_hits                     923000                       # ITB hits
+system.cpu0.itb.fetch_misses                    28932                       # ITB misses
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
 system.cpu0.itb.read_hits                           0                       # DTB read hits
@@ -515,7 +515,7 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.22% # nu
 system.cpu0.kern.callpal::swpctx                 3287      2.03%      2.25% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      43      0.03%      2.27% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.28% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               147045     90.75%     93.03% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               147044     90.75%     93.03% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6369      3.93%     96.96% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.96% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     96.96% # number of callpals executed
@@ -524,45 +524,45 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.96% # nu
 system.cpu0.kern.callpal::rti                    4450      2.75%     99.71% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 330      0.20%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                162037                       # number of callpals executed
+system.cpu0.kern.callpal::total                162036                       # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    176106                       # number of hwrei instructions executed
+system.cpu0.kern.inst.hwrei                    176105                       # number of hwrei instructions executed
 system.cpu0.kern.inst.quiesce                    6624                       # number of quiesce instructions executed
 system.cpu0.kern.ipl_count::0                   62137     40.37%     40.37% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    238      0.15%     40.53% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1925      1.25%     41.78% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                    254      0.17%     41.94% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  89359     58.06%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              153913                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  89358     58.06%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              153912                       # number of times we switched to this ipl
 system.cpu0.kern.ipl_good::0                    61267     49.13%     49.13% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     238      0.19%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1925      1.54%     50.87% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                     254      0.20%     51.07% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   61013     48.93%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               124697                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1862706719500     97.99%     97.99% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               96293500      0.01%     98.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              398446500      0.02%     98.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              103381000      0.01%     98.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            37525343500      1.97%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1900830184000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1862707102000     97.99%     97.99% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               96290500      0.01%     98.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              398437500      0.02%     98.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              103382500      0.01%     98.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            37525043500      1.97%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1900830256000                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.985999                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.682785                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good::kernel               1172                      
-system.cpu0.kern.mode_good::user                 1173                      
+system.cpu0.kern.ipl_used::31                0.682793                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good::kernel               1171                      
+system.cpu0.kern.mode_good::user                 1172                      
 system.cpu0.kern.mode_good::idle                    0                      
 system.cpu0.kern.mode_switch::kernel             6890                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1173                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1172                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_switch_good::kernel     0.170102                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.169956                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1898860791500     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1969384500      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel      1898861301500     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1968946500      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    3288                       # number of times the context was actually changed
 system.cpu0.kern.syscall::2                         6      2.99%      2.99% # number of syscalls executed
@@ -595,526 +595,526 @@ system.cpu0.kern.syscall::132                       1      0.50%     98.51% # nu
 system.cpu0.kern.syscall::144                       1      0.50%     99.00% # number of syscalls executed
 system.cpu0.kern.syscall::147                       2      1.00%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   201                       # number of syscalls executed
-system.cpu0.memDep0.conflictingLoads          2324520                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1920330                       # Number of conflicting stores.
-system.cpu0.memDep0.insertedLoads             9134564                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5843380                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.misc_regfile_reads                1626369                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                787165                       # number of misc regfile writes
-system.cpu0.numCycles                       112762027                       # number of cpu cycles simulated
+system.cpu0.memDep0.conflictingLoads          2323915                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1919788                       # Number of conflicting stores.
+system.cpu0.memDep0.insertedLoads             9134985                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5843371                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.misc_regfile_reads                1626355                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                787160                       # number of misc regfile writes
+system.cpu0.numCycles                       112761178                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.rename.RENAME:BlockCycles        12784616                       # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps      33979042                       # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IQFullEvents        1006695                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.RENAME:IdleCycles         33581656                       # Number of cycles rename is idle
-system.cpu0.rename.RENAME:LSQFullEvents       1371330                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:ROBFullEvents         43310                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.RENAME:RenameLookups      72537525                       # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts       59326371                       # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands     39979107                       # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles          11035754                       # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles        1271125                       # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles       3987965                       # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps          6000063                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:fp_rename_lookups       359001                       # Number of floating rename lookups
-system.cpu0.rename.RENAME:int_rename_lookups     72178524                       # Number of integer rename lookups
-system.cpu0.rename.RENAME:serializeStallCycles     16862175                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts      1393641                       # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts          10087757                       # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts       207582                       # count of temporary serializing insts renamed
-system.cpu0.rob.rob_reads                   134196739                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  115376344                       # The number of ROB writes
-system.cpu0.timesIdled                        1187239                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.rename.RENAME:BlockCycles        12784143                       # Number of cycles rename is blocking
+system.cpu0.rename.RENAME:CommittedMaps      33979065                       # Number of HB maps that are committed
+system.cpu0.rename.RENAME:IQFullEvents        1006573                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.RENAME:IdleCycles         33581705                       # Number of cycles rename is idle
+system.cpu0.rename.RENAME:LSQFullEvents       1371242                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RENAME:ROBFullEvents         43321                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.RENAME:RenameLookups      72539076                       # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts       59327188                       # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands     39979686                       # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles          11035795                       # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles        1271210                       # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:UnblockCycles       3987790                       # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UndoneMaps          6000619                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:fp_rename_lookups       358919                       # Number of floating rename lookups
+system.cpu0.rename.RENAME:int_rename_lookups     72180157                       # Number of integer rename lookups
+system.cpu0.rename.RENAME:serializeStallCycles     16862195                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts      1393628                       # count of serializing insts renamed
+system.cpu0.rename.RENAME:skidInsts          10087517                       # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts       207585                       # count of temporary serializing insts renamed
+system.cpu0.rob.rob_reads                   134196797                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  115377386                       # The number of ROB writes
+system.cpu0.timesIdled                        1187168                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.BTBHits                 1159872                       # Number of BTB hits
-system.cpu1.BPredUnit.BTBLookups              2699541                       # Number of BTB lookups
-system.cpu1.BPredUnit.RASInCorrect               8252                       # Number of incorrect RAS predictions.
+system.cpu1.BPredUnit.BTBHits                 1161804                       # Number of BTB hits
+system.cpu1.BPredUnit.BTBLookups              2701483                       # Number of BTB lookups
+system.cpu1.BPredUnit.RASInCorrect               8265                       # Number of incorrect RAS predictions.
 system.cpu1.BPredUnit.condIncorrect            107435                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.condPredicted           2484356                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.lookups                 2997970                       # Number of BP lookups
-system.cpu1.BPredUnit.usedRAS                  209804                       # Number of times the RAS was used to get a target.
-system.cpu1.commit.COM:branches               1520810                       # Number of branches committed
-system.cpu1.commit.COM:bw_lim_events           200192                       # number cycles where commit BW limit reached
+system.cpu1.BPredUnit.condPredicted           2484023                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.lookups                 2997822                       # Number of BP lookups
+system.cpu1.BPredUnit.usedRAS                  209923                       # Number of times the RAS was used to get a target.
+system.cpu1.commit.COM:branches               1520807                       # Number of branches committed
+system.cpu1.commit.COM:bw_lim_events           198341                       # number cycles where commit BW limit reached
 system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle::samples     17838555                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::mean     0.594502                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::stdev     1.408069                       # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::samples     17840200                       # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::mean     0.594448                       # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::stdev     1.407345                       # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::0     13455309     75.43%     75.43% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::1      2068240     11.59%     87.02% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::2       796982      4.47%     91.49% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::3       568404      3.19%     94.68% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::4       398869      2.24%     96.91% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::5       150882      0.85%     97.76% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::6       111519      0.63%     98.38% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::7        88158      0.49%     98.88% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::8       200192      1.12%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::0     13454331     75.42%     75.42% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::1      2070557     11.61%     87.02% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::2       797281      4.47%     91.49% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::3       568657      3.19%     94.68% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::4       399402      2.24%     96.92% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::5       150078      0.84%     97.76% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::6       111624      0.63%     98.38% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::7        89929      0.50%     98.89% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::8       198341      1.11%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::total     17838555                       # Number of insts commited each cycle
-system.cpu1.commit.COM:count                 10605058                       # Number of instructions committed
+system.cpu1.commit.COM:committed_per_cycle::total     17840200                       # Number of insts commited each cycle
+system.cpu1.commit.COM:count                 10605063                       # Number of instructions committed
 system.cpu1.commit.COM:fp_insts                116296                       # Number of committed floating point instructions.
 system.cpu1.commit.COM:function_calls          166623                       # Number of function calls committed.
-system.cpu1.commit.COM:int_insts              9814589                       # Number of committed integer instructions.
-system.cpu1.commit.COM:loads                  1991974                       # Number of loads committed
+system.cpu1.commit.COM:int_insts              9814594                       # Number of committed integer instructions.
+system.cpu1.commit.COM:loads                  1991971                       # Number of loads committed
 system.cpu1.commit.COM:membars                  52733                       # Number of memory barriers committed
-system.cpu1.commit.COM:refs                   3376359                       # Number of memory references committed
+system.cpu1.commit.COM:refs                   3376356                       # Number of memory references committed
 system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
-system.cpu1.commit.branchMispredicts           164468                       # The number of times a branch was mispredicted
-system.cpu1.commit.commitCommittedInsts      10605058                       # The number of committed instructions
+system.cpu1.commit.branchMispredicts           164474                       # The number of times a branch was mispredicted
+system.cpu1.commit.commitCommittedInsts      10605063                       # The number of committed instructions
 system.cpu1.commit.commitNonSpecStalls         163004                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.commitSquashedInsts        1721791                       # The number of squashed insts skipped by commit
-system.cpu1.committedInsts                   10077586                       # Number of Instructions Simulated
-system.cpu1.committedInsts_total             10077586                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.948890                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.948890                       # CPI: Total CPI of All Threads
-system.cpu1.dcache.LoadLockedReq_accesses::0        46378                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        46378                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11069.539376                       # average LoadLockedReq miss latency
+system.cpu1.commit.commitSquashedInsts        1721637                       # The number of squashed insts skipped by commit
+system.cpu1.committedInsts                   10077591                       # Number of Instructions Simulated
+system.cpu1.committedInsts_total             10077591                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.948947                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.948947                       # CPI: Total CPI of All Threads
+system.cpu1.dcache.LoadLockedReq_accesses::0        46373                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        46373                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11076.917360                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7993.965806                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits::0        39648                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        39648                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency     74498000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.145112                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::0         6730                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         6730                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_hits          764                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     47692000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.128639                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  7999.664711                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits::0        39645                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        39645                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency     74525500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.145084                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses::0         6728                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         6728                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_hits          763                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     47718000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.128631                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses         5966                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses::0        2062902                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2062902                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 15016.821540                       # average ReadReq miss latency
+system.cpu1.dcache.LoadLockedReq_mshr_misses         5965                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses::0        2063020                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2063020                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 15006.932779                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11679.389313                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11671.409798                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits::0            1868657                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1868657                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency    2916942500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate::0      0.094161                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::0           194245                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       194245                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_hits            99139                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_miss_latency   1110780000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.046103                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_hits::0            1868365                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1868365                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency    2921174500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate::0      0.094354                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses::0           194655                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       194655                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_hits            99535                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_miss_latency   1110184500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.046107                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses          95106                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses          95120                       # number of ReadReq MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     17677500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.dcache.StoreCondReq_accesses::0        43196                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        43196                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13130.603783                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13132.452048                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10135.856884                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits::0         39337                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        39337                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency     50671000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.089337                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0         3859                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         3859                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency     39094000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.089291                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10137.707469                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits::0         39338                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        39338                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency     50665000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate::0     0.089314                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0         3858                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         3858                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency     39091000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.089268                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses         3857                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses         3856                       # number of StoreCondReq MSHR misses
 system.cpu1.dcache.WriteReq_accesses::0       1334800                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total      1334800                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 21227.985433                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 21239.554449                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18769.279348                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18778.969096                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits::0           1085325                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1085325                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency   5295851666                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate::0     0.186901                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0          249475                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       249475                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_hits          201005                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_miss_latency    909746970                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.036313                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_hits::0           1085291                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1085291                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency   5299459991                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate::0     0.186926                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses::0          249509                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       249509                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_hits          201036                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_miss_latency    910272969                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.036315                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses         48470                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    377654500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs  9972.984645                       # average number of cycles each access was blocked
+system.cpu1.dcache.WriteReq_mshr_misses         48473                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    377656000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs  9801.734092                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs                 22.879556                       # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs             5275                       # number of cycles access was blocked
+system.cpu1.dcache.avg_refs                 22.873773                       # Average number of references to valid blocks.
+system.cpu1.dcache.blocked::no_mshrs             5359                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs     52607494                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_mshrs     52527493                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses::0         3397702                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::0         3397820                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3397702                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 18508.956473                       # average overall miss latency
+system.cpu1.dcache.demand_accesses::total      3397820                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency::0 18508.106220                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 14072.874088                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0             2953982                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_avg_mshr_miss_latency 14070.723984                       # average overall mshr miss latency
+system.cpu1.dcache.demand_hits::0             2953656                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         2953982                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency     8212794166                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0       0.130594                       # miss rate for demand accesses
+system.cpu1.dcache.demand_hits::total         2953656                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency     8220634491                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate::0       0.130720                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0            443720                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::0            444164                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        443720                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits            300144                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency   2020526970                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.042257                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_misses::total        444164                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits            300571                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency   2020457469                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate::0     0.042260                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses          143576                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses          143593                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0                  0.933238                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0           477.817937                       # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses::0        3397702                       # number of overall (read+write) accesses
+system.cpu1.dcache.occ_%::0                  0.933239                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0           477.818308                       # Average occupied blocks per context
+system.cpu1.dcache.overall_accesses::0        3397820                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3397702                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency::0 18508.956473                       # average overall miss latency
+system.cpu1.dcache.overall_accesses::total      3397820                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency::0 18508.106220                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 14072.874088                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 14070.723984                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0            2953982                       # number of overall hits
+system.cpu1.dcache.overall_hits::0            2953656                       # number of overall hits
 system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        2953982                       # number of overall hits
-system.cpu1.dcache.overall_miss_latency    8212794166                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::0      0.130594                       # miss rate for overall accesses
+system.cpu1.dcache.overall_hits::total        2953656                       # number of overall hits
+system.cpu1.dcache.overall_miss_latency    8220634491                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate::0      0.130720                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0           443720                       # number of overall misses
+system.cpu1.dcache.overall_misses::0           444164                       # number of overall misses
 system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       443720                       # number of overall misses
-system.cpu1.dcache.overall_mshr_hits           300144                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency   2020526970                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.042257                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_misses::total       444164                       # number of overall misses
+system.cpu1.dcache.overall_mshr_hits           300571                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency   2020457469                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate::0     0.042260                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses         143576                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency    395332000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_misses         143593                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency    395333500                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements                132522                       # number of replacements
-system.cpu1.dcache.sampled_refs                132916                       # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements                132541                       # number of replacements
+system.cpu1.dcache.sampled_refs                132935                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse               477.817937                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 3041059                       # Total number of references to valid blocks.
+system.cpu1.dcache.tagsinuse               477.818308                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 3040725                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle          1877659429000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks                   88703                       # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles       6965197                       # Number of cycles decode is blocked
-system.cpu1.decode.DECODE:BranchMispred          7952                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DECODE:BranchResolved       127936                       # Number of times decode resolved a branch
-system.cpu1.decode.DECODE:DecodedInsts       13953075                       # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles          8268454                       # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles           2505615                       # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles         305805                       # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:SquashedInsts         23745                       # Number of squashed instructions handled by decode
-system.cpu1.decode.DECODE:UnblockCycles         99288                       # Number of cycles decode is unblocking
-system.cpu1.dtb.data_accesses                  453627                       # DTB accesses
-system.cpu1.dtb.data_acv                          183                       # DTB access violations
-system.cpu1.dtb.data_hits                     3614601                       # DTB hits
-system.cpu1.dtb.data_misses                     12965                       # DTB misses
+system.cpu1.dcache.writebacks                   88729                       # number of writebacks
+system.cpu1.decode.DECODE:BlockedCycles       6964749                       # Number of cycles decode is blocked
+system.cpu1.decode.DECODE:BranchMispred          7942                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DECODE:BranchResolved       127908                       # Number of times decode resolved a branch
+system.cpu1.decode.DECODE:DecodedInsts       13950494                       # Number of instructions handled by decode
+system.cpu1.decode.DECODE:IdleCycles          8268833                       # Number of cycles decode is idle
+system.cpu1.decode.DECODE:RunCycles           2507185                       # Number of cycles decode is running
+system.cpu1.decode.DECODE:SquashCycles         305915                       # Number of cycles decode is squashing
+system.cpu1.decode.DECODE:SquashedInsts         23718                       # Number of squashed instructions handled by decode
+system.cpu1.decode.DECODE:UnblockCycles         99432                       # Number of cycles decode is unblocking
+system.cpu1.dtb.data_accesses                  453938                       # DTB accesses
+system.cpu1.dtb.data_acv                          180                       # DTB access violations
+system.cpu1.dtb.data_hits                     3612649                       # DTB hits
+system.cpu1.dtb.data_misses                     12920                       # DTB misses
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.read_accesses                  321686                       # DTB read accesses
+system.cpu1.dtb.read_accesses                  321913                       # DTB read accesses
 system.cpu1.dtb.read_acv                           80                       # DTB read access violations
-system.cpu1.dtb.read_hits                     2187439                       # DTB read hits
-system.cpu1.dtb.read_misses                     10558                       # DTB read misses
-system.cpu1.dtb.write_accesses                 131941                       # DTB write accesses
-system.cpu1.dtb.write_acv                         103                       # DTB write access violations
-system.cpu1.dtb.write_hits                    1427162                       # DTB write hits
-system.cpu1.dtb.write_misses                     2407                       # DTB write misses
-system.cpu1.fetch.Branches                    2997970                       # Number of branches that fetch encountered
-system.cpu1.fetch.CacheLines                  1676515                       # Number of cache lines fetched
-system.cpu1.fetch.Cycles                      2637646                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.IcacheSquashes               103832                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.Insts                      14205200                       # Number of instructions fetch has processed
-system.cpu1.fetch.MiscStallCycles                9114                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.SquashCycles                 191574                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.branchRate                 0.152645                       # Number of branch fetches per cycle
-system.cpu1.fetch.icacheStallCycles           1676514                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.predictedBranches           1369676                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.rate                       0.723275                       # Number of inst fetches per cycle
-system.cpu1.fetch.rateDist::samples          18144360                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.782899                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.130950                       # Number of instructions fetched each cycle (Total)
+system.cpu1.dtb.read_hits                     2185375                       # DTB read hits
+system.cpu1.dtb.read_misses                     10510                       # DTB read misses
+system.cpu1.dtb.write_accesses                 132025                       # DTB write accesses
+system.cpu1.dtb.write_acv                         100                       # DTB write access violations
+system.cpu1.dtb.write_hits                    1427274                       # DTB write hits
+system.cpu1.dtb.write_misses                     2410                       # DTB write misses
+system.cpu1.fetch.Branches                    2997822                       # Number of branches that fetch encountered
+system.cpu1.fetch.CacheLines                  1676432                       # Number of cache lines fetched
+system.cpu1.fetch.Cycles                      2639364                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.IcacheSquashes               103824                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.Insts                      14202816                       # Number of instructions fetch has processed
+system.cpu1.fetch.MiscStallCycles                9160                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.SquashCycles                 191448                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.branchRate                 0.152633                       # Number of branch fetches per cycle
+system.cpu1.fetch.icacheStallCycles           1676430                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.predictedBranches           1371727                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.rate                       0.723132                       # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist::samples          18146115                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.782692                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.130549                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                15506714     85.46%     85.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  209351      1.15%     86.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  321604      1.77%     88.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  202250      1.11%     89.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  379744      2.09%     91.60% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  126923      0.70%     92.30% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  169833      0.94%     93.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  250226      1.38%     94.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                  977715      5.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                15506751     85.45%     85.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  211557      1.17%     86.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  323359      1.78%     88.40% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  200500      1.10%     89.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  379117      2.09%     91.60% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  126850      0.70%     92.30% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  170740      0.94%     93.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  250045      1.38%     94.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                  977196      5.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            18144360                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fp_regfile_reads                    63103                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   63156                       # number of floating regfile writes
-system.cpu1.icache.ReadReq_accesses::0        1676515                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1676515                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413                       # average ReadReq miss latency
+system.cpu1.fetch.rateDist::total            18146115                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fp_regfile_reads                    63126                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   63154                       # number of floating regfile writes
+system.cpu1.icache.ReadReq_accesses::0        1676432                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1676432                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.725411                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.822702                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits::0            1412481                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1412481                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency    3874364000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate::0      0.157490                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses::0           264034                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       264034                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_hits             8194                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_miss_latency   2975118000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.152602                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11629.810943                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits::0            1412386                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1412386                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency    3874538500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate::0      0.157505                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses::0           264046                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       264046                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_hits             8197                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_miss_latency   2975475500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.152615                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses         255840                       # number of ReadReq MSHR misses
-system.cpu1.icache.avg_blocked_cycles::no_mshrs         5000                       # average number of cycles each access was blocked
+system.cpu1.icache.ReadReq_mshr_misses         255849                       # number of ReadReq MSHR misses
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  5555.555556                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs                  5.522142                       # Average number of references to valid blocks.
-system.cpu1.icache.blocked::no_mshrs                8                       # number of cycles access was blocked
+system.cpu1.icache.avg_refs                  5.521576                       # Average number of references to valid blocks.
+system.cpu1.icache.blocked::no_mshrs                9                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs        40000                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_mshrs        50000                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses::0         1676515                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::0         1676432                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1676515                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency::0 14673.731413                       # average overall miss latency
+system.cpu1.icache.demand_accesses::total      1676432                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency::0 14673.725411                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11628.822702                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits::0             1412481                       # number of demand (read+write) hits
+system.cpu1.icache.demand_avg_mshr_miss_latency 11629.810943                       # average overall mshr miss latency
+system.cpu1.icache.demand_hits::0             1412386                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1412481                       # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency     3874364000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate::0       0.157490                       # miss rate for demand accesses
+system.cpu1.icache.demand_hits::total         1412386                       # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency     3874538500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate::0       0.157505                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
 system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses::0            264034                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::0            264046                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        264034                       # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits              8194                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency   2975118000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate::0     0.152602                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_misses::total        264046                       # number of demand (read+write) misses
+system.cpu1.icache.demand_mshr_hits              8197                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_miss_latency   2975475500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate::0     0.152615                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses          255840                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses          255849                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.occ_%::0                  0.900434                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0           461.022394                       # Average occupied blocks per context
-system.cpu1.icache.overall_accesses::0        1676515                       # number of overall (read+write) accesses
+system.cpu1.icache.occ_blocks::0           461.022397                       # Average occupied blocks per context
+system.cpu1.icache.overall_accesses::0        1676432                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1676515                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency::0 14673.731413                       # average overall miss latency
+system.cpu1.icache.overall_accesses::total      1676432                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency::0 14673.725411                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11628.822702                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11629.810943                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits::0            1412481                       # number of overall hits
+system.cpu1.icache.overall_hits::0            1412386                       # number of overall hits
 system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1412481                       # number of overall hits
-system.cpu1.icache.overall_miss_latency    3874364000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate::0      0.157490                       # miss rate for overall accesses
+system.cpu1.icache.overall_hits::total        1412386                       # number of overall hits
+system.cpu1.icache.overall_miss_latency    3874538500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate::0      0.157505                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
 system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses::0           264034                       # number of overall misses
+system.cpu1.icache.overall_misses::0           264046                       # number of overall misses
 system.cpu1.icache.overall_misses::1                0                       # number of overall misses
-system.cpu1.icache.overall_misses::total       264034                       # number of overall misses
-system.cpu1.icache.overall_mshr_hits             8194                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency   2975118000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate::0     0.152602                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_misses::total       264046                       # number of overall misses
+system.cpu1.icache.overall_mshr_hits             8197                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_miss_latency   2975475500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate::0     0.152615                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses         255840                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses         255849                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements                255273                       # number of replacements
-system.cpu1.icache.sampled_refs                255785                       # Sample count of references to valid blocks.
+system.cpu1.icache.replacements                255282                       # number of replacements
+system.cpu1.icache.sampled_refs                255794                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse               461.022394                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 1412481                       # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1897915849000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks                      13                       # number of writebacks
-system.cpu1.idleCycles                        1495744                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches                 1630347                       # Number of branches executed
-system.cpu1.iew.EXEC:nop                       601729                       # number of nop insts executed
-system.cpu1.iew.EXEC:rate                    0.552052                       # Inst execution rate
-system.cpu1.iew.EXEC:refs                     3644132                       # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores                   1436628                       # Number of stores executed
+system.cpu1.icache.tagsinuse               461.022397                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 1412386                       # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1897915594000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.writebacks                      23                       # number of writebacks
+system.cpu1.idleCycles                        1494579                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.iew.EXEC:branches                 1630757                       # Number of branches executed
+system.cpu1.iew.EXEC:nop                       601681                       # number of nop insts executed
+system.cpu1.iew.EXEC:rate                    0.552014                       # Inst execution rate
+system.cpu1.iew.EXEC:refs                     3642117                       # number of memory reference insts executed
+system.cpu1.iew.EXEC:stores                   1436733                       # Number of stores executed
 system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
-system.cpu1.iew.WB:consumers                  6274106                       # num instructions consuming a value
-system.cpu1.iew.WB:count                     10735003                       # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout                    0.735138                       # average fanout of values written-back
+system.cpu1.iew.WB:consumers                  6271876                       # num instructions consuming a value
+system.cpu1.iew.WB:count                     10737023                       # cumulative count of insts written-back
+system.cpu1.iew.WB:fanout                    0.735626                       # average fanout of values written-back
 system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
 system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers                  4612335                       # num instructions producing a value
-system.cpu1.iew.WB:rate                      0.546586                       # insts written-back per cycle
-system.cpu1.iew.WB:sent                      10758148                       # cumulative count of insts sent to commit
-system.cpu1.iew.branchMispredicts              178810                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewBlockCycles                 256636                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewDispLoadInsts              2309588                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispNonSpecInsts            500342                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewDispSquashedInsts           209309                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispStoreInsts             1512714                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispatchedInsts           12409933                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewExecLoadInsts              2207504                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           107468                       # Number of squashed instructions skipped in execute
-system.cpu1.iew.iewExecutedInsts             10842361                       # Number of executed instructions
-system.cpu1.iew.iewIQFullEvents                  2486                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.WB:producers                  4613753                       # num instructions producing a value
+system.cpu1.iew.WB:rate                      0.546672                       # insts written-back per cycle
+system.cpu1.iew.WB:sent                      10760010                       # cumulative count of insts sent to commit
+system.cpu1.iew.branchMispredicts              178779                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewBlockCycles                 257448                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewDispLoadInsts              2307630                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispNonSpecInsts            500245                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewDispSquashedInsts           209270                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispStoreInsts             1513195                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispatchedInsts           12409620                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewExecLoadInsts              2205384                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           107607                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts             10841947                       # Number of executed instructions
+system.cpu1.iew.iewIQFullEvents                  2515                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewLSQFullEvents                 4828                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.iewSquashCycles                305805                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewUnblockCycles                10156                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewLSQFullEvents                 4902                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                305915                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewUnblockCycles                10123                       # Number of cycles IEW is unblocking
 system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread.0.cacheBlocked        22318                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.lsq.thread.0.forwLoads          68189                       # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread.0.ignoredResponses         2236                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread.0.cacheBlocked        20397                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread.0.forwLoads          68108                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread.0.ignoredResponses         2244                       # Number of memory responses ignored because the instruction is squashed
 system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread.0.memOrderViolation        10653                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread.0.rescheduledLoads          380                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread.0.squashedLoads       317614                       # Number of loads squashed
-system.cpu1.iew.lsq.thread.0.squashedStores       128329                       # Number of stores squashed
-system.cpu1.iew.memOrderViolationEvents         10653                       # Number of memory order violations
-system.cpu1.iew.predictedNotTakenIncorrect       104816                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.predictedTakenIncorrect         73994                       # Number of branches that were predicted taken incorrectly
-system.cpu1.int_regfile_reads                13933756                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                7611585                       # number of integer regfile writes
-system.cpu1.ipc                              0.513113                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.513113                       # IPC: Total IPC of All Threads
+system.cpu1.iew.lsq.thread.0.memOrderViolation        10644                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread.0.rescheduledLoads          381                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread.0.squashedLoads       315659                       # Number of loads squashed
+system.cpu1.iew.lsq.thread.0.squashedStores       128810                       # Number of stores squashed
+system.cpu1.iew.memOrderViolationEvents         10644                       # Number of memory order violations
+system.cpu1.iew.predictedNotTakenIncorrect       104770                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.predictedTakenIncorrect         74009                       # Number of branches that were predicted taken incorrectly
+system.cpu1.int_regfile_reads                13934200                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                7613029                       # number of integer regfile writes
+system.cpu1.ipc                              0.513098                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.513098                       # IPC: Total IPC of All Threads
 system.cpu1.iq.ISSUE:FU_type_0::No_OpClass         3524      0.03%      0.03% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntAlu        6870860     62.75%     62.78% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntMult         18138      0.17%     62.95% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     62.95% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        11432      0.10%     63.05% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     63.05% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     63.05% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     63.05% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1762      0.02%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     63.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemRead       2282503     20.85%     83.91% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemWrite      1453754     13.28%     97.19% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntAlu        6872542     62.77%     62.80% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntMult         18152      0.17%     62.96% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     62.96% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        11432      0.10%     63.07% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     63.07% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1762      0.02%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     63.08% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemRead       2280411     20.83%     83.91% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemWrite      1453875     13.28%     97.19% # Type of FU issued
 system.cpu1.iq.ISSUE:FU_type_0::IprAccess       307856      2.81%    100.00% # Type of FU issued
 system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::total        10949829                       # Type of FU issued
-system.cpu1.iq.ISSUE:fu_busy_cnt               154910                       # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate            0.014147                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.ISSUE:FU_type_0::total        10949554                       # Type of FU issued
+system.cpu1.iq.ISSUE:fu_busy_cnt               155065                       # FU busy when requested
+system.cpu1.iq.ISSUE:fu_busy_rate            0.014162                       # FU busy rate (busy events/executed inst)
 system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntAlu             4092      2.64%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.64% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemRead           90881     58.67%     61.31% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemWrite          59937     38.69%    100.00% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntAlu             4030      2.60%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.60% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemRead           91114     58.76%     61.36% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemWrite          59921     38.64%    100.00% # attempts to use FU when none available
 system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples     18144360                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.603484                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.209438                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::samples     18146115                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.603410                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.208341                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0     12920190     71.21%     71.21% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1      2565455     14.14%     85.35% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::2      1066502      5.88%     91.22% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::3       689185      3.80%     95.02% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4       526783      2.90%     97.93% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::5       236336      1.30%     99.23% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::6        93675      0.52%     99.75% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::7        36919      0.20%     99.95% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::8         9315      0.05%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::0     12918859     71.19%     71.19% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::1      2566374     14.14%     85.34% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::2      1069941      5.90%     91.23% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::3       687798      3.79%     95.02% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::4       527186      2.91%     97.93% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::5       238422      1.31%     99.24% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::6        93189      0.51%     99.76% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::7        34852      0.19%     99.95% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::8         9494      0.05%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total     18144360                       # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate                    0.557524                       # Inst issue rate
-system.cpu1.iq.fp_alu_accesses                 125165                       # Number of floating point alu accesses
-system.cpu1.iq.fp_inst_queue_reads             243017                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       117535                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_writes            119622                       # Number of floating instruction queue writes
-system.cpu1.iq.int_alu_accesses              10976050                       # Number of integer alu accesses
-system.cpu1.iq.int_inst_queue_reads          39966063                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_wakeup_accesses     10617468                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.int_inst_queue_writes         13352810                       # Number of integer instruction queue writes
-system.cpu1.iq.iqInstsAdded                  11252421                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqInstsIssued                 10949829                       # Number of instructions issued
-system.cpu1.iq.iqNonSpecInstsAdded             555783                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqSquashedInstsExamined        1655590                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedInstsIssued            10152                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedNonSpecRemoved        392779                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.iqSquashedOperandsExamined       854299                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.ISSUE:issued_per_cycle::total     18146115                       # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:rate                    0.557493                       # Inst issue rate
+system.cpu1.iq.fp_alu_accesses                 125187                       # Number of floating point alu accesses
+system.cpu1.iq.fp_inst_queue_reads             243060                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       117556                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_writes            119680                       # Number of floating instruction queue writes
+system.cpu1.iq.int_alu_accesses              10975908                       # Number of integer alu accesses
+system.cpu1.iq.int_inst_queue_reads          39967405                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_wakeup_accesses     10619467                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.int_inst_queue_writes         13352100                       # Number of integer instruction queue writes
+system.cpu1.iq.iqInstsAdded                  11252265                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqInstsIssued                 10949554                       # Number of instructions issued
+system.cpu1.iq.iqNonSpecInstsAdded             555674                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqSquashedInstsExamined        1655179                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsIssued            10177                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedNonSpecRemoved        392670                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.iqSquashedOperandsExamined       852165                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_hits                           0                       # DTB hits
 system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.fetch_accesses                 448461                       # ITB accesses
-system.cpu1.itb.fetch_acv                         279                       # ITB acv
-system.cpu1.itb.fetch_hits                     439821                       # ITB hits
-system.cpu1.itb.fetch_misses                     8640                       # ITB misses
+system.cpu1.itb.fetch_accesses                 448608                       # ITB accesses
+system.cpu1.itb.fetch_acv                         274                       # ITB acv
+system.cpu1.itb.fetch_hits                     439933                       # ITB hits
+system.cpu1.itb.fetch_misses                     8675                       # ITB misses
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
 system.cpu1.itb.read_hits                           0                       # DTB read hits
@@ -1154,11 +1154,11 @@ system.cpu1.kern.ipl_good::22                    1922      4.55%     52.28% # nu
 system.cpu1.kern.ipl_good::30                     351      0.83%     53.11% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::31                   19806     46.89%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good::total                42236                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1870770703000     98.44%     98.44% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              347961500      0.02%     98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              137588500      0.01%     98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            29223568000      1.54%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1900479821000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0            1870770905000     98.44%     98.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              347965500      0.02%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              137591500      0.01%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            29223562000      1.54%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1900480024000                       # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_used::0                 0.975465                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
@@ -1173,9 +1173,9 @@ system.cpu1.kern.mode_switch_good::kernel     0.480747                       # f
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.108619                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::total     1.589366                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        6317362000      0.33%      0.33% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1020701000      0.05%      0.39% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1893129288000     99.61%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel        6317215000      0.33%      0.33% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1021115000      0.05%      0.39% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1893129227000     99.61%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                    1451                       # number of times the context was actually changed
 system.cpu1.kern.syscall::2                         2      1.60%      1.60% # number of syscalls executed
 system.cpu1.kern.syscall::3                        13     10.40%     12.00% # number of syscalls executed
@@ -1200,37 +1200,37 @@ system.cpu1.kern.syscall::92                        2      1.60%     96.80% # nu
 system.cpu1.kern.syscall::132                       3      2.40%     99.20% # number of syscalls executed
 system.cpu1.kern.syscall::144                       1      0.80%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                   125                       # number of syscalls executed
-system.cpu1.memDep0.conflictingLoads           496033                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          413880                       # Number of conflicting stores.
-system.cpu1.memDep0.insertedLoads             2309588                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1512714                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.misc_regfile_reads                 594436                       # number of misc regfile reads
+system.cpu1.memDep0.conflictingLoads           495102                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          416651                       # Number of conflicting stores.
+system.cpu1.memDep0.insertedLoads             2307630                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1513195                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.misc_regfile_reads                 594453                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                255211                       # number of misc regfile writes
-system.cpu1.numCycles                        19640104                       # number of cpu cycles simulated
+system.cpu1.numCycles                        19640694                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.rename.RENAME:BlockCycles          522822                       # Number of cycles rename is blocking
-system.cpu1.rename.RENAME:CommittedMaps       7159583                       # Number of HB maps that are committed
-system.cpu1.rename.RENAME:IQFullEvents          32718                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RENAME:IdleCycles          8500925                       # Number of cycles rename is idle
-system.cpu1.rename.RENAME:LSQFullEvents        256778                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:ROBFullEvents         15506                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.RENAME:RenameLookups      15473473                       # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts       12930857                       # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands      8489204                       # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles           2359874                       # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles         305805                       # Number of cycles rename is squashing
-system.cpu1.rename.RENAME:UnblockCycles        801183                       # Number of cycles rename is unblocking
-system.cpu1.rename.RENAME:UndoneMaps          1329621                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:fp_rename_lookups       171444                       # Number of floating rename lookups
-system.cpu1.rename.RENAME:int_rename_lookups     15302029                       # Number of integer rename lookups
-system.cpu1.rename.RENAME:serializeStallCycles      5653749                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RENAME:serializingInsts       515468                       # count of serializing insts renamed
-system.cpu1.rename.RENAME:skidInsts           2303190                       # count of insts added to the skid buffer
-system.cpu1.rename.RENAME:tempSerializingInsts        52722                       # count of temporary serializing insts renamed
-system.cpu1.rob.rob_reads                    29861070                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   24957765                       # The number of ROB writes
-system.cpu1.timesIdled                         194766                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.rename.RENAME:BlockCycles          523712                       # Number of cycles rename is blocking
+system.cpu1.rename.RENAME:CommittedMaps       7159591                       # Number of HB maps that are committed
+system.cpu1.rename.RENAME:IQFullEvents          32710                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.RENAME:IdleCycles          8501498                       # Number of cycles rename is idle
+system.cpu1.rename.RENAME:LSQFullEvents        256763                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RENAME:ROBFullEvents         15504                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.RENAME:RenameLookups      15470992                       # Number of register rename lookups that rename has made
+system.cpu1.rename.RENAME:RenamedInsts       12928500                       # Number of instructions processed by rename
+system.cpu1.rename.RENAME:RenamedOperands      8487290                       # Number of destination operands rename has renamed
+system.cpu1.rename.RENAME:RunCycles           2361527                       # Number of cycles rename is running
+system.cpu1.rename.RENAME:SquashCycles         305915                       # Number of cycles rename is squashing
+system.cpu1.rename.RENAME:UnblockCycles        801170                       # Number of cycles rename is unblocking
+system.cpu1.rename.RENAME:UndoneMaps          1327699                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:fp_rename_lookups       171482                       # Number of floating rename lookups
+system.cpu1.rename.RENAME:int_rename_lookups     15299510                       # Number of integer rename lookups
+system.cpu1.rename.RENAME:serializeStallCycles      5652291                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RENAME:serializingInsts       515456                       # count of serializing insts renamed
+system.cpu1.rename.RENAME:skidInsts           2302074                       # count of insts added to the skid buffer
+system.cpu1.rename.RENAME:tempSerializingInsts        52719                       # count of temporary serializing insts renamed
+system.cpu1.rob.rob_reads                    29864417                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   24957573                       # The number of ROB writes
+system.cpu1.timesIdled                         194633                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1261,37 +1261,37 @@ system.iocache.ReadReq_mshr_misses                172                       # nu
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137704.871149                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137701.983202                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85701.289902                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5721912806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85698.425972                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5721792806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3561059998                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3560940996                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6175.549096                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6175.644708                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64590068                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64591068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::1               41724                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41724                       # number of demand (read+write) accesses
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137612.376666                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137609.500623                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85608.810181                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85605.958058                       # average overall mshr miss latency
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5741738804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5741618804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
@@ -1299,7 +1299,7 @@ system.iocache.demand_misses::0                     0                       # nu
 system.iocache.demand_misses::1                 41724                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41724                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3571941996                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3571822994                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
@@ -1313,14 +1313,14 @@ system.iocache.overall_accesses::0                  0                       # nu
 system.iocache.overall_accesses::1              41724                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41724                       # number of overall (read+write) accesses
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137612.376666                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137609.500623                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85608.810181                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85605.958058                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5741738804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5741618804                       # number of overall miss cycles
 system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
@@ -1328,7 +1328,7 @@ system.iocache.overall_misses::0                    0                       # nu
 system.iocache.overall_misses::1                41724                       # number of overall misses
 system.iocache.overall_misses::total            41724                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3571941996                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3571822994                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
@@ -1342,55 +1342,55 @@ system.iocache.tagsinuse                     0.467303                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle              1711286190000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41520                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               257294                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                42294                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           299588                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 55984.033368                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 838025.398663                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               257283                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                42295                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           299578                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 55985.536569                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 837818.012343                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40323.668210                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                   140895                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    34518                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               175413                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency          6516485500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.452397                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.183856                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 116399                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                   7776                       # number of ReadExReq misses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40324.759412                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                   140886                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1                    34517                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               175403                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          6516548500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.452408                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.183899                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 116397                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                   7778                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             124175                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency     5007191500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       0.482619                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       2.935996                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_latency     5007327000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.482640                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       2.935926                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_misses               124175                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                1807450                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 343665                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2151115                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52801.925207                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   3681603.345555                       # average ReadReq miss latency
+system.l2c.ReadReq_accesses::0                1807428                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                 343680                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2151108                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52801.503186                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   3683358.780376                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40018.264766                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40018.194749                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1503171                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     339301                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1842472                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           16066517000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.168347                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.012698                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   304279                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     4364                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               308643                       # number of ReadReq misses
+system.l2c.ReadReq_hits::0                    1503141                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                     339318                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1842459                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           16066811000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.168354                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.012692                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   304287                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     4362                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               308649                       # number of ReadReq misses
 system.l2c.ReadReq_mshr_hits                       16                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency      12350717000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.170753                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.898046                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_latency      12350935500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.170758                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         0.898024                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 308627                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    840465500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_misses                 308633                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    840464000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.SCUpgradeReq_accesses::0               609                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::1               601                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total          1210                       # number of SCUpgradeReq accesses(hits+misses)
@@ -1414,120 +1414,120 @@ system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.886855                       # m
 system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_misses              1134                       # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0                2885                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                2883                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::1                1622                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4507                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            4505                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_avg_miss_latency::0  5855.677656                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 12557.737628                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 12567.610063                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.987260                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                     155                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                     349                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 504                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.991504                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                     153                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                     350                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 503                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_miss_latency           15986000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.946274                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.784834                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.946930                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.784217                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_misses::0                  2730                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  1273                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4003                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency     160188000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0      1.387522                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      2.467941                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::1                  1272                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              4002                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency     160148000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      1.388137                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      2.467324                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses                4003                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                4002                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1532818498                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               810405                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           810405                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   810405                       # number of Writeback hits
-system.l2c.Writeback_hits::total               810405                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1532817998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               810507                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           810507                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   810507                       # number of Writeback hits
+system.l2c.Writeback_hits::total               810507                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          5.657708                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          5.658014                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2064744                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  385959                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2064711                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                  385975                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2450703                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    53682.394848                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    1860214.373970                       # average overall miss latency
+system.l2c.demand_accesses::total             2450686                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    53682.477822                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    1860243.780890                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40105.887912                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1644066                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      373819                       # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency  40106.149840                       # average overall mshr miss latency
+system.l2c.demand_hits::0                     1644027                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                      373835                       # number of demand (read+write) hits
 system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2017885                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            22583002500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.203743                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.031454                       # miss rate for demand accesses
+system.l2c.demand_hits::total                 2017862                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            22583359500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.203750                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.031453                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    420678                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                    420684                       # number of demand (read+write) misses
 system.l2c.demand_misses::1                     12140                       # number of demand (read+write) misses
 system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                432818                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                432824                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                        16                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       17357908500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.209615                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.121368                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_latency       17358262500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.209622                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          1.121337                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  432802                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses                  432808                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.187715                       # Average percentage of cache occupancy
+system.l2c.occ_%::0                          0.187716                       # Average percentage of cache occupancy
 system.l2c.occ_%::1                          0.005740                       # Average percentage of cache occupancy
 system.l2c.occ_%::2                          0.351851                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                 12302.114841                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   376.171902                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 23058.891094                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                2064744                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 385959                       # number of overall (read+write) accesses
+system.l2c.occ_blocks::0                 12302.143800                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                   376.171509                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                 23058.900248                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2064711                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                 385975                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2450703                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   53682.394848                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   1860214.373970                       # average overall miss latency
+system.l2c.overall_accesses::total            2450686                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   53682.477822                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   1860243.780890                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40105.887912                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40106.149840                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1644066                       # number of overall hits
-system.l2c.overall_hits::1                     373819                       # number of overall hits
+system.l2c.overall_hits::0                    1644027                       # number of overall hits
+system.l2c.overall_hits::1                     373835                       # number of overall hits
 system.l2c.overall_hits::2                          0                       # number of overall hits
-system.l2c.overall_hits::total                2017885                       # number of overall hits
-system.l2c.overall_miss_latency           22583002500                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.203743                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.031454                       # miss rate for overall accesses
+system.l2c.overall_hits::total                2017862                       # number of overall hits
+system.l2c.overall_miss_latency           22583359500                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.203750                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.031453                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   420678                       # number of overall misses
+system.l2c.overall_misses::0                   420684                       # number of overall misses
 system.l2c.overall_misses::1                    12140                       # number of overall misses
 system.l2c.overall_misses::2                        0                       # number of overall misses
-system.l2c.overall_misses::total               432818                       # number of overall misses
+system.l2c.overall_misses::total               432824                       # number of overall misses
 system.l2c.overall_mshr_hits                       16                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      17357908500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         0.209615                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.121368                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency      17358262500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.209622                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         1.121337                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 432802                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   2373283998                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses                 432808                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   2373281998                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        395562                       # number of replacements
-system.l2c.sampled_refs                        431632                       # Sample count of references to valid blocks.
+system.l2c.replacements                        395559                       # number of replacements
+system.l2c.sampled_refs                        431638                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     35737.177838                       # Cycle average of tags in use
-system.l2c.total_refs                         2442048                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     35737.215556                       # Cycle average of tags in use
+system.l2c.total_refs                         2442214                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                    9270445000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          121361                       # number of writebacks
+system.l2c.writebacks                          121360                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
index 838d9a364c8b92d4339288d088764e30a2cb4a70..a3d5d358664cea3b71c388f32490aeb18c277725 100644 (file)
@@ -10,12 +10,12 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -142,6 +142,7 @@ assoc=4
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -440,6 +441,7 @@ assoc=1
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
@@ -491,7 +493,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -511,7 +513,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -536,6 +538,7 @@ assoc=8
 block_size=64
 forward_snoops=false
 hash_delay=1
+is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
@@ -567,6 +570,7 @@ assoc=8
 block_size=64
 forward_snoops=true
 hash_delay=1
+is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
@@ -637,7 +641,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
index bdb8a98f83d0b3ba50ae17ade751419774099a64..9021122e37bf31badeb41a6569eb87a5914e2aa1 100755 (executable)
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb  7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Mar 15 2011 18:10:57
+M5 revision ee89694ad8dc 8081 default ext/mem_block_transfer_O3_regressions.patch tip qtip
+M5 started Mar 15 2011 18:10:59
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1866702838500 because m5_exit instruction encountered
+Exiting @ tick 1865724648500 because m5_exit instruction encountered
index e3a6bbb06251e7ca571fbd51f690aa195c07b353..2e169bdbb78867bf4d297d125f3d5e0e677588ad 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  66360                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 311288                       # Number of bytes of host memory used
-host_seconds                                   799.45                       # Real time elapsed on the host
-host_tick_rate                             2334981918                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 180508                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 328492                       # Number of bytes of host memory used
+host_seconds                                   293.90                       # Real time elapsed on the host
+host_tick_rate                             6348189027                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    53051251                       # Number of instructions simulated
-sim_seconds                                  1.866703                       # Number of seconds simulated
-sim_ticks                                1866702838500                       # Number of ticks simulated
+sim_insts                                    53051011                       # Number of instructions simulated
+sim_seconds                                  1.865725                       # Number of seconds simulated
+sim_ticks                                1865724648500                       # Number of ticks simulated
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits                  6623157                       # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups              12789444                       # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect               40569                       # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect             601028                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted           11937575                       # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups                 14339384                       # Number of BP lookups
-system.cpu.BPredUnit.usedRAS                  1014923                       # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches                8457250                       # Number of branches committed
-system.cpu.commit.COM:bw_lim_events           1007675                       # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits                  6620966                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups              12786893                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect               40572                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect             600914                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted           11937031                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                 14338397                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                  1014681                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches                8457274                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events           1008616                       # number cycles where commit BW limit reached
 system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples     89231545                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean     0.630319                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev     1.393269                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples     89227396                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.630345                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.393343                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0     65110491     72.97%     72.97% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1     10643752     11.93%     84.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2      6057329      6.79%     91.68% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3      2842358      3.19%     94.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4      2098441      2.35%     97.22% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5       701144      0.79%     98.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6       394504      0.44%     98.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7       375851      0.42%     98.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8      1007675      1.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0     65107231     72.97%     72.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1     10642774     11.93%     84.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2      6057714      6.79%     91.68% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3      2842201      3.19%     94.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4      2098462      2.35%     97.22% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5       700908      0.79%     98.01% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6       394479      0.44%     98.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7       375011      0.42%     98.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8      1008616      1.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total     89231545                       # Number of insts commited each cycle
-system.cpu.commit.COM:count                  56244349                       # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total     89227396                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                  56244072                       # Number of instructions committed
 system.cpu.commit.COM:fp_insts                 324384                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls           744090                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts              52084301                       # Number of committed integer instructions.
-system.cpu.commit.COM:loads                   9107235                       # Number of loads committed
-system.cpu.commit.COM:membars                  227951                       # Number of memory barriers committed
-system.cpu.commit.COM:refs                   15496318                       # Number of memory references committed
+system.cpu.commit.COM:function_calls           744089                       # Number of function calls committed.
+system.cpu.commit.COM:int_insts              52084090                       # Number of committed integer instructions.
+system.cpu.commit.COM:loads                   9107066                       # Number of loads committed
+system.cpu.commit.COM:membars                  227958                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                   15496059                       # Number of memory references committed
 system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts            771510                       # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts       56244349                       # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls          667563                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts         8699299                       # The number of squashed insts skipped by commit
-system.cpu.committedInsts                    53051251                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              53051251                       # Number of Instructions Simulated
-system.cpu.cpi                               2.358137                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.358137                       # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses::0       215722                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       215722                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14725.540425                       # average LoadLockedReq miss latency
+system.cpu.commit.branchMispredicts            771395                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts       56244072                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls          667553                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts         8698928                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                    53051011                       # Number of Instructions Simulated
+system.cpu.committedInsts_total              53051011                       # Number of Instructions Simulated
+system.cpu.cpi                               2.358035                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.358035                       # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses::0       215741                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       215741                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14722.823889                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11882.875143                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0        193471                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       193471                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency    327658000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11882.359679                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits::0        193488                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       193488                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency    327627000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_rate::0     0.103147                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0        22251                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22251                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits         4791                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    207475000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.080938                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0        22253                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22253                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits         4793                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    207466000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.080930                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_misses        17460                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0         9297964                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9297964                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 22717.133732                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses::0         9298482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9298482                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 22717.267883                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.439279                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.415740                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0             7723736                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7723736                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    35761948000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0       0.169309                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0           1574228                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1574228                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits            490302                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency  24691226500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.116577                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0             7724340                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7724340                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    35760205500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0       0.169290                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0           1574142                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1574142                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits            490275                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency  24689857000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.116564                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1083926                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency    905134500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0       219685                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       219685                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_mshr_misses         1083867                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency    905506500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0       219687                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       219687                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_avg_miss_latency::0        14000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency        11000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits::0         219682                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       219682                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::0         219684                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       219684                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_miss_latency        42000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_rate::0     0.000014                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_misses::0            3                       # number of StoreCondReq misses
@@ -107,287 +107,287 @@ system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000014
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_misses            3                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::0        6154252                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6154252                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 29747.302403                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses::0        6154158                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6154158                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 29745.716858                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28091.080381                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28090.291333                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0            4299090                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4299090                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   55186065021                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0      0.301444                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0          1855162                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1855162                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits          1555538                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency   8416761868                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.048686                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0            4298986                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4298986                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   55183421035                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0      0.301450                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0          1855172                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1855172                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits          1555560                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency   8416188367                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.048684                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         299624                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1235207998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  8963.151072                       # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_mshr_misses         299612                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1235453998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  8964.775985                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                   8.877326                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs             83371                       # number of cycles access was blocked
+system.cpu.dcache.avg_refs                   8.878146                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs             83356                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs    747266868                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs    747267867                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::0         15452216                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0         15452640                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15452216                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 26520.172107                       # average overall miss latency
+system.cpu.dcache.demand_accesses::total     15452640                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 26519.480729                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23929.737536                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0             12022826                       # number of demand (read+write) hits
+system.cpu.dcache.demand_avg_mshr_miss_latency 23929.561177                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0             12023326                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         12022826                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     90948013021                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0        0.221935                       # miss rate for demand accesses
+system.cpu.dcache.demand_hits::total         12023326                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     90943626535                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0        0.221924                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0            3429390                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0            3429314                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3429390                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits            2045840                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  33107988368                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0     0.089537                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_misses::total        3429314                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits            2045835                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency  33106045367                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0     0.089530                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1383550                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses          1383479                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.occ_%::0                   0.999991                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0            511.995490                       # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0        15452216                       # number of overall (read+write) accesses
+system.cpu.dcache.occ_blocks::0            511.995488                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0        15452640                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15452216                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 26520.172107                       # average overall miss latency
+system.cpu.dcache.overall_accesses::total     15452640                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 26519.480729                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23929.737536                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23929.561177                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0            12022826                       # number of overall hits
+system.cpu.dcache.overall_hits::0            12023326                       # number of overall hits
 system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        12022826                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    90948013021                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0       0.221935                       # miss rate for overall accesses
+system.cpu.dcache.overall_hits::total        12023326                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    90943626535                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0       0.221924                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0           3429390                       # number of overall misses
+system.cpu.dcache.overall_misses::0           3429314                       # number of overall misses
 system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3429390                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits           2045840                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  33107988368                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0     0.089537                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_misses::total       3429314                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits           2045835                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency  33106045367                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0     0.089530                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1383550                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency   2140342498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_misses         1383479                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency   2140960498                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements                1400366                       # number of replacements
-system.cpu.dcache.sampled_refs                1400878                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1400295                       # number of replacements
+system.cpu.dcache.sampled_refs                1400807                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.995490                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 12436050                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                511.995488                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 12436569                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               21271000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   832764                       # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles       37803166                       # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred          42143                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved        613837                       # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts        71397647                       # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles          37493968                       # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles           12849862                       # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles         1515496                       # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts         134350                       # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles        1084548                       # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses                  1235511                       # DTB accesses
-system.cpu.dtb.data_acv                           814                       # DTB access violations
-system.cpu.dtb.data_hits                     16593720                       # DTB hits
-system.cpu.dtb.data_misses                      46888                       # DTB misses
+system.cpu.dcache.writebacks                   832735                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles       37803322                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred          42125                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved        613661                       # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts        71395902                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles          37491497                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles           12847985                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles         1515320                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts         134367                       # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles        1084591                       # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses                  1236212                       # DTB accesses
+system.cpu.dtb.data_acv                           809                       # DTB access violations
+system.cpu.dtb.data_hits                     16593947                       # DTB hits
+system.cpu.dtb.data_misses                      46903                       # DTB misses
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                   910670                       # DTB read accesses
-system.cpu.dtb.read_acv                           580                       # DTB read access violations
-system.cpu.dtb.read_hits                     10006545                       # DTB read hits
-system.cpu.dtb.read_misses                      38646                       # DTB read misses
-system.cpu.dtb.write_accesses                  324841                       # DTB write accesses
-system.cpu.dtb.write_acv                          234                       # DTB write access violations
-system.cpu.dtb.write_hits                     6587175                       # DTB write hits
+system.cpu.dtb.read_accesses                   911157                       # DTB read accesses
+system.cpu.dtb.read_acv                           576                       # DTB read access violations
+system.cpu.dtb.read_hits                     10006781                       # DTB read hits
+system.cpu.dtb.read_misses                      38661                       # DTB read misses
+system.cpu.dtb.write_accesses                  325055                       # DTB write accesses
+system.cpu.dtb.write_acv                          233                       # DTB write access violations
+system.cpu.dtb.write_hits                     6587166                       # DTB write hits
 system.cpu.dtb.write_misses                      8242                       # DTB write misses
-system.cpu.fetch.Branches                    14339384                       # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines                   8856318                       # Number of cache lines fetched
-system.cpu.fetch.Cycles                      14115387                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes                454337                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts                       72663163                       # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles                43087                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles                  884394                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate                  0.114621                       # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles            8856315                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches            7638080                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate                        0.580831                       # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples           90747041                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.800722                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.110012                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches                    14338397                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                   8855922                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                      14113501                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                454413                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                       72660960                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                42720                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                  884189                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.114619                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles            8855919                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches            7635647                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        0.580841                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples           90742716                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.800736                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.110037                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 76631654     84.45%     84.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1046048      1.15%     85.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1970042      2.17%     87.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   921005      1.01%     88.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2984540      3.29%     92.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   648959      0.72%     92.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   776516      0.86%     93.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1074251      1.18%     94.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4694026      5.17%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 76629215     84.45%     84.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1044484      1.15%     85.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1968851      2.17%     87.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   922109      1.02%     88.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2984062      3.29%     92.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   649093      0.72%     92.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   777227      0.86%     93.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1074028      1.18%     94.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4693647      5.17%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             90747041                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                    164450                       # number of floating regfile reads
+system.cpu.fetch.rateDist::total             90742716                       # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads                    164464                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                   166718                       # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses::0         8856318                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8856318                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14954.328072                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses::0         8855922                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8855922                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14953.893584                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.426022                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0             7816051                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7816051                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency    15556494000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0       0.117460                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0           1040267                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1040267                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits             47648                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency  11850308500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.112080                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.313504                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::0             7815698                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7815698                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency    15555399000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0       0.117461                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0           1040224                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1040224                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits             47681                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency  11849289500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.112077                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses          992619                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs        12375                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_mshr_misses          992543                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs 12554.545455                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                   7.875653                       # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs                56                       # number of cycles access was blocked
+system.cpu.icache.avg_refs                   7.875900                       # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs                55                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs       693000                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs       690500                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::0          8856318                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0          8855922                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8856318                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14954.328072                       # average overall miss latency
+system.cpu.icache.demand_accesses::total      8855922                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14953.893584                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11938.426022                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::0              7816051                       # number of demand (read+write) hits
+system.cpu.icache.demand_avg_mshr_miss_latency 11938.313504                       # average overall mshr miss latency
+system.cpu.icache.demand_hits::0              7815698                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7816051                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency     15556494000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0        0.117460                       # miss rate for demand accesses
+system.cpu.icache.demand_hits::total          7815698                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency     15555399000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0        0.117461                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::0            1040267                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::0            1040224                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1040267                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits              47648                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency  11850308500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0     0.112080                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_misses::total        1040224                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits              47681                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency  11849289500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0     0.112077                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses           992619                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses           992543                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0                   0.995726                       # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0            509.811601                       # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0         8856318                       # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0                   0.995724                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            509.810451                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0         8855922                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8856318                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14954.328072                       # average overall miss latency
+system.cpu.icache.overall_accesses::total      8855922                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0 14953.893584                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11938.426022                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11938.313504                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0             7816051                       # number of overall hits
+system.cpu.icache.overall_hits::0             7815698                       # number of overall hits
 system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total         7816051                       # number of overall hits
-system.cpu.icache.overall_miss_latency    15556494000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0       0.117460                       # miss rate for overall accesses
+system.cpu.icache.overall_hits::total         7815698                       # number of overall hits
+system.cpu.icache.overall_miss_latency    15555399000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0       0.117461                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::0           1040267                       # number of overall misses
+system.cpu.icache.overall_misses::0           1040224                       # number of overall misses
 system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total       1040267                       # number of overall misses
-system.cpu.icache.overall_mshr_hits             47648                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency  11850308500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0     0.112080                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_misses::total       1040224                       # number of overall misses
+system.cpu.icache.overall_mshr_hits             47681                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency  11849289500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0     0.112077                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses          992619                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses          992543                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements                 991921                       # number of replacements
-system.cpu.icache.sampled_refs                 992432                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                 991845                       # number of replacements
+system.cpu.icache.sampled_refs                 992356                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                509.811601                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  7816050                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                509.810451                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  7815697                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle            24432989000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                       92                       # number of writebacks
-system.cpu.idleCycles                        34355081                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches                  9120774                       # Number of branches executed
-system.cpu.iew.EXEC:nop                       3587033                       # number of nop insts executed
-system.cpu.iew.EXEC:rate                     0.456767                       # Inst execution rate
-system.cpu.iew.EXEC:refs                     16683612                       # number of memory reference insts executed
-system.cpu.iew.EXEC:stores                    6610329                       # Number of stores executed
+system.cpu.icache.writebacks                      176                       # number of writebacks
+system.cpu.idleCycles                        34353421                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                  9120660                       # Number of branches executed
+system.cpu.iew.EXEC:nop                       3587020                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.456799                       # Inst execution rate
+system.cpu.iew.EXEC:refs                     16683854                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                    6610322                       # Number of stores executed
 system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
-system.cpu.iew.WB:consumers                  35257849                       # num instructions consuming a value
-system.cpu.iew.WB:count                      56697227                       # cumulative count of insts written-back
-system.cpu.iew.WB:fanout                     0.757274                       # average fanout of values written-back
+system.cpu.iew.WB:consumers                  35263910                       # num instructions consuming a value
+system.cpu.iew.WB:count                      56698677                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.757187                       # average fanout of values written-back
 system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers                  26699852                       # num instructions producing a value
-system.cpu.iew.WB:rate                       0.453208                       # insts written-back per cycle
-system.cpu.iew.WB:sent                       56799146                       # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts               837773                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles                 9250897                       # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts              10628246                       # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts            1790214                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts            887997                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts              6943382                       # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts            65075490                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts              10073283                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            520965                       # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts              57142461                       # Number of executed instructions
-system.cpu.iew.iewIQFullEvents                  61275                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers                  26701367                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.453241                       # insts written-back per cycle
+system.cpu.iew.WB:sent                       56800727                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts               837733                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                 9250224                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts              10628233                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts            1789856                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts            887489                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts              6943615                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts            65074740                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts              10073532                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            521272                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts              57143754                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                  61252                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents                 11738                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles                1515496                       # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles                557834                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents                 11749                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                1515320                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                557849                       # Number of cycles IEW is unblocking
 system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked       132328                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads          438613                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses         9607                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked       132030                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads          438592                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses         9600                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation        42661                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads        17611                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads      1521011                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores       554299                       # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents          42661                       # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect       406369                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect         431404                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                 74886349                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40928930                       # number of integer regfile writes
-system.cpu.ipc                               0.424064                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.424064                       # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation        42579                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads        17615                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads      1521167                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores       554622                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents          42579                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect       406353                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect         431380                       # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads                 74888686                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40930439                       # number of integer regfile writes
+system.cpu.ipc                               0.424082                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.424082                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass         7281      0.01%      0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu        39527901     68.55%     68.56% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult          62346      0.11%     68.67% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu        39529083     68.55%     68.56% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult          62345      0.11%     68.67% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     68.67% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatAdd         25607      0.04%     68.71% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     68.71% # Type of FU issued
@@ -415,15 +415,15 @@ system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     68.72%
 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     68.72% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     68.72% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     68.72% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead       10424527     18.08%     86.80% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite       6659257     11.55%     98.35% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess       952873      1.65%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead       10424979     18.08%     86.80% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite       6659276     11.55%     98.35% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess       952821      1.65%    100.00% # Type of FU issued
 system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total         57663428                       # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt                432905                       # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate             0.007507                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total         57665028                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt                432817                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.007506                       # FU busy rate (busy events/executed inst)
 system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu             49058     11.33%     11.33% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu             49052     11.33%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%     11.33% # attempts to use FU when none available
@@ -452,51 +452,51 @@ system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     11.33% #
 system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     11.33% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     11.33% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead           267419     61.77%     73.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite          116428     26.89%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead           267357     61.77%     73.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite          116408     26.90%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples     90747041                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean     0.635430                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.200309                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples     90742716                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.635478                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.200410                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0      62366198     68.73%     68.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1      14061379     15.50%     84.22% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2       6226874      6.86%     91.08% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3       3821617      4.21%     95.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4       2539194      2.80%     98.09% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5       1091409      1.20%     99.29% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6        462366      0.51%     99.80% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7        128599      0.14%     99.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8         49405      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0      62361590     68.72%     68.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1      14062254     15.50%     84.22% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2       6225923      6.86%     91.08% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3       3822183      4.21%     95.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4       2538846      2.80%     98.09% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5       1090826      1.20%     99.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6        462139      0.51%     99.80% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7        129609      0.14%     99.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8         49346      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total     90747041                       # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate                     0.460931                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                  341243                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads              667907                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses       325691                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes             334133                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses               57747809                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads          205867710                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses     56371536                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes          69251365                       # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded                   59448706                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued                  57663428                       # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded             2039751                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined         8060465                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued             28817                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved        1372188                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined      4168617                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total     90742716                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     0.460966                       # Inst issue rate
+system.cpu.iq.fp_alu_accesses                  341264                       # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads              667947                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses       325705                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes             334327                       # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses               57749300                       # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads          205866504                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses     56372972                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes          69249578                       # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded                   59448335                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                  57665028                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded             2039385                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined         8059661                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued             28864                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved        1371832                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined      4166065                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_hits                            0                       # DTB hits
 system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                 1294583                       # ITB accesses
-system.cpu.itb.fetch_acv                          923                       # ITB acv
-system.cpu.itb.fetch_hits                     1255493                       # ITB hits
-system.cpu.itb.fetch_misses                     39090                       # ITB misses
+system.cpu.itb.fetch_accesses                 1294620                       # ITB accesses
+system.cpu.itb.fetch_acv                          913                       # ITB acv
+system.cpu.itb.fetch_hits                     1255661                       # ITB hits
+system.cpu.itb.fetch_misses                     38959                       # ITB misses
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -512,8 +512,8 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175591     91.19%     93.39% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6793      3.53%     96.92% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175578     91.19%     93.39% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6792      3.53%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
@@ -521,42 +521,42 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.93% # nu
 system.cpu.kern.callpal::rti                     5221      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192561                       # number of callpals executed
+system.cpu.kern.callpal::total                 192547                       # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     211718                       # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce                     6427                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0                    74916     40.95%     40.95% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     238      0.13%     41.08% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1890      1.03%     42.11% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105896     57.89%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182940                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73549     49.29%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      238      0.16%     49.45% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1890      1.27%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73550     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149227                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1827171336500     97.88%     97.88% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                97547000      0.01%     97.89% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               392033000      0.02%     97.91% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             39041048500      2.09%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1866701965000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981753                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.hwrei                     211704                       # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce                     6424                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count::0                    74914     40.95%     40.95% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     239      0.13%     41.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1889      1.03%     42.12% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105885     57.88%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182927                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73547     49.29%     49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      239      0.16%     49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1889      1.27%     50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73548     49.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149223                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1826194216500     97.88%     97.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                97924500      0.01%     97.89% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               391796500      0.02%     97.91% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             39039837500      2.09%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1865723775000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981752                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694549                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694603                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.mode_good::kernel                1906                      
 system.cpu.kern.mode_good::user                  1736                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch::kernel              5956                       # number of protection mode switches
+system.cpu.kern.mode_switch::kernel              5959                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1736                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2107                       # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel     0.320013                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch::idle                2104                       # number of protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.319852                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080683                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.400697                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        30086574000      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           3015068000      0.16%      1.77% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1833600315000     98.23%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.080798                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      1.400651                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        30091122000      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           3014546000      0.16%      1.77% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1832618099000     98.23%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
@@ -589,37 +589,37 @@ system.cpu.kern.syscall::132                        4      1.23%     98.77% # nu
 system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
 system.cpu.kern.syscall::total                    326                       # number of syscalls executed
-system.cpu.memDep0.conflictingLoads           3018201                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2591237                       # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads             10628246                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6943382                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                 1993439                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 949389                       # number of misc regfile writes
-system.cpu.numCycles                        125102122                       # number of cpu cycles simulated
+system.cpu.memDep0.conflictingLoads           3018997                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2591949                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads             10628233                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6943615                       # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads                 1993395                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 949366                       # number of misc regfile writes
+system.cpu.numCycles                        125096137                       # number of cpu cycles simulated
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles         13297534                       # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps       38227478                       # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents         1065628                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles          39060011                       # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents        1661101                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents          58596                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups       82213921                       # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts        67573183                       # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands     45293711                       # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles           12514369                       # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles         1515496                       # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles        4654173                       # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps           7066231                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups       474968                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups     81738953                       # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles     19705456                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts      1694142                       # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts           11744700                       # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts       247271                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                    152916375                       # The number of ROB reads
-system.cpu.rob.rob_writes                   131403689                       # The number of ROB writes
-system.cpu.timesIdled                         1310957                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles         13296621                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps       38227330                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents         1065712                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles          39057588                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents        1661249                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents          58583                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups       82211156                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts        67570562                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands     45292482                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles           12512523                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles         1515320                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles        4654421                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps           7065150                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups       475144                       # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups     81736012                       # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles     19706241                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts      1694164                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts           11744747                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts       247277                       # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads                    152910637                       # The number of ROB reads
+system.cpu.rob.rob_writes                   131402179                       # The number of ROB writes
+system.cpu.timesIdled                         1310794                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -650,37 +650,37 @@ system.iocache.ReadReq_mshr_misses                173                       # nu
 system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137707.205574                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137705.665335                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85703.600260                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5722009806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85702.060021                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5721945806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3561155998                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3561091998                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs  6170.205040                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  6170.968690                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs      64639068                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs      64647068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
 system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137614.087573                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1 137612.553721                       # average overall miss latency
 system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85610.497208                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85608.963355                       # average overall mshr miss latency
 system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
 system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5741947804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5741883804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
@@ -688,7 +688,7 @@ system.iocache.demand_misses::0                     0                       # nu
 system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3572097996                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3572033996                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
@@ -696,20 +696,20 @@ system.iocache.demand_mshr_misses               41725                       # nu
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.occ_%::1                      0.081528                       # Average percentage of cache occupancy
-system.iocache.occ_blocks::1                 1.304443                       # Average occupied blocks per context
+system.iocache.occ_%::1                      0.081046                       # Average percentage of cache occupancy
+system.iocache.occ_blocks::1                 1.296738                       # Average occupied blocks per context
 system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137614.087573                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137612.553721                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85610.497208                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85608.963355                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
 system.iocache.overall_hits::0                      0                       # number of overall hits
 system.iocache.overall_hits::1                      0                       # number of overall hits
 system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.overall_miss_latency        5741947804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5741883804                       # number of overall miss cycles
 system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
@@ -717,7 +717,7 @@ system.iocache.overall_misses::0                    0                       # nu
 system.iocache.overall_misses::1                41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3572097996                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3572033996                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
@@ -727,145 +727,145 @@ system.iocache.overall_mshr_uncacheable_misses            0
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     1.304443                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.296738                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle              1711281262000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses::0               300850                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           300850                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52488.966283                       # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0               300822                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           300822                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 52489.461538                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40339.814538                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0                   183845                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               183845                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency          6141471500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0            0.388915                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0                 117005                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             117005                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency     4719960000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0       0.388915                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40340.521368                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                   183822                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               183822                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          6141267000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.388934                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 117000                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             117000                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     4719841000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.388934                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               117005                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0                2092533                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2092533                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0   52046.060634                       # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses               117000                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0                2092337                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2092337                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52046.096131                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40015.025123                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40015.012554                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0                    1785047                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1785047                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           16003435000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0              0.146944                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0                   307486                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               307486                       # number of ReadReq misses
+system.l2c.ReadReq_hits::0                    1784860                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1784860                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           16002977500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.146954                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                   307477                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               307477                       # number of ReadReq misses
 system.l2c.ReadReq_mshr_hits                        1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency      12304020000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.146944                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_latency      12303656000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.146953                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 307485                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    810593000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_misses                 307476                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    810924000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.SCUpgradeReq_accesses::0                 3                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             3                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_hits::0                     3                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
-system.l2c.UpgradeReq_accesses::0                  25                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              25                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0        21400                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_accesses::0                  22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 22928.571429                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency        44000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0                      10                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  10                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_avg_mshr_miss_latency 44285.714286                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                       8                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   8                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_miss_latency             321000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0           0.600000                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0                    15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency        660000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.600000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.636364                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                    14                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                14                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency        620000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.636364                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses                  15                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses                  14                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1115666998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0               832856                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           832856                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0                   832856                       # number of Writeback hits
-system.l2c.Writeback_hits::total               832856                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1115890498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               832911                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           832911                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   832911                       # number of Writeback hits
+system.l2c.Writeback_hits::total               832911                       # number of Writeback hits
 system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          5.629154                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          5.628523                       # Average number of references to valid blocks.
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::0                 2393383                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::0                 2393159                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2393383                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0    52168.141374                       # average overall miss latency
+system.l2c.demand_accesses::total             2393159                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    52168.302405                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40104.548988                       # average overall mshr miss latency
-system.l2c.demand_hits::0                     1968892                       # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency  40104.733837                       # average overall mshr miss latency
+system.l2c.demand_hits::0                     1968682                       # number of demand (read+write) hits
 system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1968892                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            22144906500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0               0.177360                       # miss rate for demand accesses
+system.l2c.demand_hits::total                 1968682                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            22144244500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.177371                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.demand_misses::0                    424491                       # number of demand (read+write) misses
+system.l2c.demand_misses::0                    424477                       # number of demand (read+write) misses
 system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                424491                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                424477                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       17023980000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0          0.177360                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_latency       17023497000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.177371                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  424490                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses                  424476                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.occ_%::0                          0.186942                       # Average percentage of cache occupancy
-system.l2c.occ_%::1                          0.344679                       # Average percentage of cache occupancy
-system.l2c.occ_blocks::0                 12251.423039                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 22588.894949                       # Average occupied blocks per context
-system.l2c.overall_accesses::0                2393383                       # number of overall (read+write) accesses
+system.l2c.occ_%::0                          0.186906                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.344678                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                 12249.050591                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 22588.829074                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                2393159                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2393383                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0   52168.141374                       # average overall miss latency
+system.l2c.overall_accesses::total            2393159                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   52168.302405                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40104.548988                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40104.733837                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::0                    1968892                       # number of overall hits
+system.l2c.overall_hits::0                    1968682                       # number of overall hits
 system.l2c.overall_hits::1                          0                       # number of overall hits
-system.l2c.overall_hits::total                1968892                       # number of overall hits
-system.l2c.overall_miss_latency           22144906500                       # number of overall miss cycles
-system.l2c.overall_miss_rate::0              0.177360                       # miss rate for overall accesses
+system.l2c.overall_hits::total                1968682                       # number of overall hits
+system.l2c.overall_miss_latency           22144244500                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.177371                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.overall_misses::0                   424491                       # number of overall misses
+system.l2c.overall_misses::0                   424477                       # number of overall misses
 system.l2c.overall_misses::1                        0                       # number of overall misses
-system.l2c.overall_misses::total               424491                       # number of overall misses
+system.l2c.overall_misses::total               424477                       # number of overall misses
 system.l2c.overall_mshr_hits                        1                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      17023980000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0         0.177360                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency      17023497000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.177371                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 424490                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   1926259998                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses                 424476                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   1926814498                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.replacements                        390992                       # number of replacements
-system.l2c.sampled_refs                        423734                       # Sample count of references to valid blocks.
+system.l2c.replacements                        390976                       # number of replacements
+system.l2c.sampled_refs                        423725                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     34840.317988                       # Cycle average of tags in use
-system.l2c.total_refs                         2385264                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     34837.879666                       # Cycle average of tags in use
+system.l2c.total_refs                         2384946                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                    5637119000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          117628                       # number of writebacks
+system.l2c.writebacks                          117616                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post