targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have...

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index ddd243800b6128574a02d167b4369e132d889b90..da8c99d6660788e160e00f63e7fb665f9532e7a2 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -42,7 +42,7 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 
                if not self.with_main_ram:
-                       sdram_module = MT46V32M16(self.clk_freq)
+                       sdram_modules = MT46V32M16(self.clk_freq)
                        sdram_controller_settings =  sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
@@ -50,7 +50,7 @@ class BaseSoC(SDRAMSoC):
                        )
                        self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
                                rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
-                       self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
+                       self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings,
                                sdram_controller_settings)