from migen.fhdl.structure import *
from migen.fhdl.structure import _Fragment
from migen.fhdl.tools import rename_clock_domain
-from migen.sim.upper import gen_sim, proxy_sim
class FinalizeError(Exception):
self.finalized = False
return self.finalized
elif name == "_fragment":
- simf = None
- try:
- simf = self.do_simulation
- except AttributeError:
- try:
- simg = self.gen_simulation
- except AttributeError:
- pass
- else:
- simf = gen_sim(simg)
- if simf is not None:
- simf = proxy_sim(self, simf)
- sim = [] if simf is None else [simf]
- self._fragment = _Fragment(sim=sim)
+ self._fragment = _Fragment()
return self._fragment
elif name == "_submodules":
self._submodules = []
(SPECIAL_INPUT, SPECIAL_OUTPUT, SPECIAL_INOUT) = range(3)
-class StopSimulation(Exception):
- pass
-
-
class _Fragment:
- def __init__(self, comb=None, sync=None, specials=None, clock_domains=None, sim=None):
+ def __init__(self, comb=None, sync=None, specials=None, clock_domains=None):
if comb is None: comb = []
if sync is None: sync = dict()
if specials is None: specials = set()
if clock_domains is None: clock_domains = _ClockDomainList()
- if sim is None: sim = []
self.comb = comb
self.sync = sync
self.specials = specials
self.clock_domains = _ClockDomainList(clock_domains)
- self.sim = sim
def __add__(self, other):
newsync = defaultdict(list)
newsync[k].extend(v)
return _Fragment(self.comb + other.comb, newsync,
self.specials | other.specials,
- self.clock_domains + other.clock_domains,
- self.sim + other.sim)
+ self.clock_domains + other.clock_domains)
def __iadd__(self, other):
newsync = defaultdict(list)
self.sync = newsync
self.specials |= other.specials
self.clock_domains += other.clock_domains
- self.sim += other.sim
return self