crg: apply constraint to IO pins, not internal signals

diff --git a/mibuild/crg.py b/mibuild/crg.py
index 7d967742a40f0259d5b469cf5247b2aafde57e1e..83ae9c4e570c09f27f84d4054cdcc6b5fdfe683f 100644 (file)
--- a/mibuild/crg.py
+++ b/mibuild/crg.py
@@ -3,9 +3,11 @@ from migen.fhdl.module import Module
 
 class SimpleCRG(Module):
        def __init__(self, platform, clk_name, rst_name, rst_invert=False):
+                       self._clk = platform.request(clk_name)
+                       self._rst = platform.request(rst_name)
                        self.clock_domains.cd_sys = ClockDomain()
-                       self.comb += self.cd_sys.clk.eq(platform.request(clk_name))
+                       self.comb += self.cd_sys.clk.eq(self._clk)
                        if rst_invert:
-                               self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
+                               self.comb += self.cd_sys.rst.eq(~self._rst)
                        else:
-                               self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
+                               self.comb += self.cd_sys.rst.eq(self._rst)

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 6a1e9d7ed707f52e51b4bebfe653c7d63ea90af4..a6c31c00cba0fef07652da763ac31513ace36d76 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -17,7 +17,7 @@ TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk)
 class CRG_SE(SimpleCRG):
        def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
                SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
-               _add_period_constraint(platform, self.cd_sys.clk, period)
+               _add_period_constraint(platform, self._clk, period)
 
 class CRG_DS(Module):
        def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):