Revert 90be0d8 as it causes endless loops for some designs

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 10bdf7221eede83e2c2d9d385f13e604fa2f775e..eb9d02ad538bd8803391c5509ecd57c219237d6b 100644 (file)
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -88,7 +88,6 @@ struct OptReduceWorker
                RTLIL::SigSpec new_sig_a(new_sig_a_bits);
 
                if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
-                       new_sig_a.sort_and_unify();
                        log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
                        did_something = true;
                        total_count++;