Set the MABI and MArch of the riscv target.

Again, this should be tunable, and synchronized with the core settings.

diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py
index 38c5d5e724b8a8efcca96edb9d6173785f27e535..fd1e4afb961c64a9e09f42fa7f88a00aaee8a4e7 100644 (file)
--- a/litex/soc/integration/cpu_interface.py
+++ b/litex/soc/integration/cpu_interface.py
@@ -35,7 +35,7 @@ def get_cpu_mak(cpu):
     elif cpu == "riscv32":
         assert not clang, "riscv32 not supported with clang."
         triple = "riscv32-unknown-elf"
-        cpuflags = "-mno-save-restore"
+        cpuflags = "-mno-save-restore -march=rv32im -mabi=ilp32"
         clang = False
     else:
         raise ValueError("Unsupported CPU type: "+cpu)