(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 3ee7c38edefcd1bc9dc3b28751ade2927d6c758b..732c6c9809456711cf7a21b05c963bb0392d4f35 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -322,6 +322,16 @@ acting in effect as either a popcount or cntlz depending on which
 mode bits are set.
 In short, Vectorised Branch becomes an extremely powerful tool.
 
+* **Micro-Architectural Implementation Note**: when implemented on
+top of a Multi-Issue Out-of-Order Engine it is possible to pass
+a copy of the predicate and the prerequisite CR Fields to all
+Branch Units, as well as the current value of CTR at the time of
+multi-issue, and for each Branch Unit to compute how many times
+CTR would be subtracted, in a fully-deterministic and parallel
+fashion. A SIMD-based Branch Unit, receiving and processing
+multiple CR Fields covered by multiple predicate bits, would
+do the exact same thing.*
+
 ## CTR-test
 
 Where a standard Scalar v3.0B branch unconditionally decrements
@@ -357,7 +367,7 @@ a predicate mask bit is clear.  **All** other SVP64 operations
 entirely skip an element when sz=0 and a predicate mask bit is zero.
 It is also critical to emphasise that in this unusual mode, 
 no other side-effects occur: **only** CTR is decremented, i.e. the
-rest of the Branch operation iss skipped.
+rest of the Branch operation is skipped.
 
 # VLSET Mode