[arm] Rewrite addsi3_carryin_shift_<optab> in canonical form

The add-with-carry operation which involves a shift doesn't match at present
because it isn't matching the canonical form generated by combine.  Fixing
this is simply a matter of re-ordering the operands.

	* config/arm/arm.md (addsi3_carryin_shift_<optab>): Reorder operands
	to match canonical form.

From-SVN: r277167

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7935f1f544159b8fb7305374cc094d22dff74346..cb2abfe3dca5c2ea8baf8a69796b98531410effa 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-10-18  Richard Earnshaw  <rearnsha@arm.com>
+
+       * config/arm/arm.md (addsi3_carryin_shift_<optab>): Reorder operands
+       to match canonical form.
+
 2019-10-18  Richard Earnshaw  <rearnsha@arm.com>
 
        * config/arm/arm.md (zero_extend<mode>di2): Convert to define_expand.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4a7a64e661331dc5ff86b950a2d6825d274c9874..9754a761fafbbf8ea1afd656375bb06401bb4b3b 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -913,8 +913,8 @@
                  (match_operator:SI 2 "shift_operator"
                    [(match_operand:SI 3 "s_register_operand" "r")
                     (match_operand:SI 4 "reg_or_int_operand" "rM")])
-                 (match_operand:SI 1 "s_register_operand" "r"))
-                (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
+                 (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0)))
+                (match_operand:SI 1 "s_register_operand" "r")))]
   "TARGET_32BIT"
   "adc%?\\t%0, %1, %3%S2"
   [(set_attr "conds" "use")