AtomicSimpleCPU::init()
{
BaseCPU::init();
+ cpuId = tc->readCpuId();
#if FULL_SYSTEM
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
- TheISA::initCPU(tc, tc->readCpuId());
+ TheISA::initCPU(tc, cpuId);
}
#endif
if (hasPhysMemPort) {
physmemPort.getPeerAddressRanges(pmAddrList, snoop);
physMemAddr = *pmAddrList.begin();
}
+ ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
+ data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
+ data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
}
bool
icachePort.snoopRangeSent = false;
dcachePort.snoopRangeSent = false;
- ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
- data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
- data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
}
}
assert(threadContexts.size() == 1);
cpuId = tc->readCpuId();
+ ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
+ data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
+ data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
}
TimingSimpleCPU::init()
{
BaseCPU::init();
+ cpuId = tc->readCpuId();
#if FULL_SYSTEM
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
- TheISA::initCPU(tc, tc->readCpuId());
+ TheISA::initCPU(tc, cpuId);
}
#endif
}