but silent data corruption as well as no means to trap-and-emulate differing
bitwidths.[^vsx256]
-Thus "Silicon-Partner" Scalability
+"Silicon-Partner" Scalability is identical to mixing 32-bit Power ISA
+with 64-bit in the same binary (just as catastrophic), and
is prohibited in the Simple-V Scalable Vector ISA,
-This does
-mean that `RESERVED` space is crucial to have, in order
-to safely provide the option of
+`RESERVED` space is thus crucial to have, in order
+to provide the option of
future expanded register file bitwidths and sizes[^msr],
-under explicitly-distinguishable encoding,
-**at the discretion of and with the full authority of the OPF ISA WG**,
+under **explicitly-distinguishable** encoding,
+**at the discretion of the OPF ISA WG**,
not the implementor ("Silicon Partner").
# Hardware Implementations