test.compat: reenable tests converting to Verilog.

diff --git a/nmigen/compat/fhdl/verilog.py b/nmigen/compat/fhdl/verilog.py
index bced762aeada62a9b5630086aba10bbb4392fc48..ad2f588b0e2d5e8e0d8c40cdc89294859396eadb 100644 (file)
--- a/nmigen/compat/fhdl/verilog.py
+++ b/nmigen/compat/fhdl/verilog.py
@@ -1,6 +1,6 @@
 import warnings
 
-from ...hdl import Fragment
+from ...hdl.ir import Fragment
 from ...back import verilog
 from .conv_output import ConvOutput
 

diff --git a/nmigen/test/compat/support.py b/nmigen/test/compat/support.py
index 2a1292ffe7b36977596d88c94fe63ff0f16e9680..3de32763314b9c3dbb2add873338cfd6418d3b71 100644 (file)
--- a/nmigen/test/compat/support.py
+++ b/nmigen/test/compat/support.py
@@ -1,13 +1,13 @@
 from ...compat import *
-# from ...compat.fhdl import verilog
+from ...compat.fhdl import verilog
 
 
 class SimCase:
     def setUp(self, *args, **kwargs):
         self.tb = self.TestBench(*args, **kwargs)
 
-    # def test_to_verilog(self):
-    #     verilog.convert(self.tb)
+    def test_to_verilog(self):
+        verilog.convert(self.tb)
 
     def run_with(self, generator):
         run_simulation(self.tb, generator)