Re: [libre-riscv-dev] cache SRAM organisation

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+From: Staf Verhaegen <staf@fibraservi.eu>
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+Subject: Re: [libre-riscv-dev] cache SRAM organisation
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+Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 21:28 [+0000]:
+> On Thu, Mar 26, 2020 at 8:08 PM Staf Verhaegen <staf@fibraservi.eu> wrote=
+:
+> > Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 15:15 [+0000]:
+> > > On Thursday, March 26, 2020, Staf Verhaegen <staf@fibraservi.eu> wrot=
+e:
+> > > > I can understand you do this to implement functional units withconf=
+igurable pipeline length but I would strongly discourage to pipelineregiste=
+r files after each other .
+> > >=20
+> > >=20
+> > > "pipeline register files after each other"? apologies i am not clear =
+whatyou mean, here.  do you mean "don't do write-thru on the Regfile"?
+> >=20
+> > No I meant for example connecting the output of one port of an asynchro=
+nous RAM to for example the address input of another port of an asynchronou=
+s RAM.
+>=20
+> ah right, no definitely not.  the connections are:
+> RegisterFile readport[0..R] =3D=3D> FunctionUnit[0..M] operand latches   =
+                                         pipeline stage 0                  =
+                          pipeline stage 1                                 =
+           ...                                            pipeline stage NR=
+egisterFile writeport[0..W] <=3D=3D FunctionUnit[0..M] result latches
+> (and also: )register file bypass forwardingbus <=3D=3D FunctionUnit resul=
+t latchesregister file bypass forwardingbus =3D=3D> FunctionUnit operand la=
+tches
+> so the asynchronous SRAMs will definitely *only* be connected to SFFlatch=
+es.  *not* to other asynchronous SRAMs.
+
+I still feel you intermix synchronous and write-through in this statement, =
+the above seems to be possible with synchronous SRAMs.
+
+greets,
+Staf.
+
+
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