fhdl/verilog: lower complex slices before reset insertion

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index d9683e9404185aa987d6afd8d9e014d77f01b0c2..7a6f7ce68b223d623fc96e5a3dd294db0bf89ad8 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -302,6 +302,7 @@ def convert(f, ios=None, name="top",
                        else:
                                raise KeyError("Unresolved clock domain: '"+cd_name+"'")
        
+       f = lower_complex_slices(f)
        _insert_resets(f)
        f = lower_basics(f)
        fs, lowered_specials = _lower_specials(special_overrides, f.specials)