celltype = basic_cell_type(celltype);
}
// Is this cell a module instance?
- if (celltype[0] != '$') {
- auto instModule = design->module(celltype);
- // If there is no instance for this, issue a warning.
- if (instModule == NULL) {
+ auto instModule = design->module(celltype);
+ // If there is no instance for this, issue a warning.
+ if (instModule == NULL) {
+ // but only if we're sure it is a reference to a module.
+ if (celltype[0] != '$')
log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str());
- } else {
- score = max(score, find_top_mod_score(design, instModule, db) + 1);
- }
+ } else {
+ score = max(score, find_top_mod_score(design, instModule, db) + 1);
}
}
db[module] = score;
set -e
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+echo -n " TOP first - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module TOP(a, y);
input a;
hierarchy -auto-top
EOY
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+echo -n " TOP last - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module aoi12(a, y);
input a;
hierarchy -auto-top
EOY
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module."
+echo -n " no explicit top - "
+../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
read_verilog << EOV
module aoi12(a, y);
input a;