add ctrl skeleton

diff --git a/lib/sata/k7sataphy/ctrl.py b/lib/sata/k7sataphy/ctrl.py
new file mode 100644 (file)
index 0000000..7f762ea
--- /dev/null
+++ b/lib/sata/k7sataphy/ctrl.py
@@ -0,0 +1,106 @@
+from migen.fhdl.std import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.fsm import FSM, NextState
+
+def us(self, t, speed="SATA3", margin=True):
+       clk_freq = {
+               "SATA3" :       300*1000000,
+               "SATA2" :       150*1000000,
+               "SATA1" :        75*1000000
+       }
+       clk_period_us = 1000000/clk_freq
+       if margin:
+               t += clk_period_us/2
+       return ceil(t/clk_period_us)
+
+class K7SATAPHYHostCtrl(Module):
+       def __init__(self, gtx):
+               self.link_up = Signal()
+
+               tx_com_done = Signal()
+               align_timeout = Signal()
+               align_detect = Signal()
+
+               fsm = FSM(reset_state="IDLE")
+               self.submodules += fsm
+
+               fsm.act("RESET",
+                       gtx.txcominit.eq(1),
+                       gtx.txelecidle.eq(1),
+                       If(tx_com_done & ~gtx.rxcominitdet),
+                               NextState("AWAIT_COMINIT")
+                       )
+               )
+               fsm.act("AWAIT_COMINIT",
+                       gtx.txelecidle.eq(1),
+                       If(gtx.rxcominitdet,
+                               NextState("AWAIT_NO_COMINIT")
+                       ).Else(
+                               If(retry_cnt == 0,
+                                       NextState("RESET")
+                               )
+                       )
+               )
+               fsm.act("AWAIT_NO_COMINIT",
+                       gtx.txelecidle.eq(1),
+                       If(~gtx.rxcominitdet,
+                               NextState("CALIBRATE")
+                       )
+               )
+               fsm.act("CALIBRATE",
+                       gtx.txelecidle.eq(1),
+                       NextState("COMWAKE")
+               )
+               fsm.act("COMWAKE",
+                       gtx.txelecidle.eq(1),
+                       gtx.txcomwake.eq(1),
+                       If(tx_com_done,
+                               NextState("AWAIT_COMWAKE")
+                       )
+               )
+               fsm.act("AWAIT_COMWAKE",
+                       gtx.txelecidle.eq(1),
+                       If(gtx.rxcomwakedet,
+                               NextState("AWAIT_NO_COMWAKE")
+                       ).Else(
+                               If(retry_cnt == 0,
+                                       NextState("RESET")
+                               )
+                       )
+               )
+               fsm.act("AWAIT_NO_COMWAKE",
+                       gtx.txelecidle.eq(1),
+                       If(~gtx.rxcomwakedet,
+                               NextState("AWAIT_ALIGN")
+                       )
+               )
+               fsm.act("AWAIT_ALIGN",
+                       gtx.txelecidle.eq(0),
+                       gtx.txdata.eq(0x4A4A), #D10.2
+                       gtx.txcharisk.eq(0b0000),
+                       If(align_detect & ~align_timeout,
+                               NextState("SEND_ALIGN")
+                       ).Elif(~align_detect & align_timeout,
+                               NextState("RESET")
+                       )
+               )
+               fsm.act("SEND_ALIGN",
+                       gtx.txelecidle.eq(0),
+                       gtx.txdata.eq(ALIGN_VAL),
+                       gtx.txcharisk.eq(0b0001),
+                       If(non_align_cnt == 3,
+                               NextState("READY")
+                       )
+               )
+               fsm.act("READY",
+                       gtx.txelecidle.eq(0),
+                       gtx.txdata.eq(SYNC_VAL),
+                       gtx.txcharisk.eq(0b0001),
+                       If(gtx.rxelecidle,
+                               NextState("RESET")
+                       ),
+                       self.link_up.eq(1)
+               )
+
+class K7SATAPHYDeviceCtrl(Module):
+       def __init__(self, gtx):

diff --git a/lib/sata/k7sataphy/std.py b/lib/sata/k7sataphy/std.py
index b8058b946e12396650dcf67dc982e4489bc3219b..283a8c848c71ee2e6baf3284188bf095a9f3e0b2 100644 (file)
--- a/lib/sata/k7sataphy/std.py
+++ b/lib/sata/k7sataphy/std.py
@@ -2,6 +2,25 @@ from migen.fhdl.std import *
 
 K28_5 = 0b1010000011
 
+ALIGN_VAL   = 0x7B4A4ABC
+CONT_VAL    = 0x9999AA7C
+DMAT_VAL    = 0x3636B57C
+EOF_VAL     = 0xD5D5B57C
+HOLD_VAL    = 0xD5D5AA7C
+HOLDA_VAL   = 0x9595AA7C
+PMACK_VAL   = 0x9595957C
+PMNAK_VAL   = 0xF5F5957C
+PMREQ_P_VAL = 0x1717B57C
+PMREQ_S_VAL = 0x7575957C
+R_ERR_VAL   = 0x5656B57C
+R_IP_VAL    = 0x5555B57C
+R_OK_VAL    = 0x3535B57C
+R_RDY_VAL   = 0x4A4A957C
+SOF_VAL     = 0x3737B57C
+SYNC_VAL    = 0xB5B5957C
+WTRM_VAL    = 0x5858B57C
+X_RDY_VAL   = 0x5757B57C
+
 def _ones(width):
        return 2**width-1