#include "debug/Cache.hh"
#include "mem/cache/base.hh"
#include "mem/cache/mshr.hh"
+#include "sim/full_system.hh"
using namespace std;
const string &cstr = cmd.toString();
hits[access_idx]
-#if FULL_SYSTEM
- .init(_numCpus + 1)
-#else
- .init(_numCpus)
-#endif
+ .init(FullSystem ? (_numCpus + 1) : _numCpus)
.name(name() + "." + cstr + "_hits")
.desc("number of " + cstr + " hits")
.flags(total | nozero | nonan)
const string &cstr = cmd.toString();
misses[access_idx]
-#if FULL_SYSTEM
- .init(_numCpus + 1)
-#else
- .init(_numCpus)
-#endif
+ .init(FullSystem ? (_numCpus + 1) : _numCpus)
.name(name() + "." + cstr + "_misses")
.desc("number of " + cstr + " misses")
.flags(total | nozero | nonan)
#include "mem/tport.hh"
#include "params/BaseCache.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/sim_exit.hh"
class MSHR;
* available, meanwhile writeback hit/miss stats are not used
* in any aggregate hit/miss calculations, so just lump them all
* in bucket 0 */
-#if FULL_SYSTEM
- } else if (id == -1) {
+ } else if (FullSystem && id == -1) {
// Device accesses have id -1
// lump device accesses into their own bucket
misses[pkt->cmdToIndex()][_numCpus]++;
-#endif
} else {
misses[pkt->cmdToIndex()][id % _numCpus]++;
}
if (pkt->cmd == MemCmd::Writeback) {
assert(id == -1);
hits[pkt->cmdToIndex()][0]++;
-#if FULL_SYSTEM
- } else if (id == -1) {
+ } else if (FullSystem && id == -1) {
// Device accesses have id -1
// lump device accesses into their own bucket
hits[pkt->cmdToIndex()][_numCpus]++;
-#endif
} else {
/* the % is necessary in case there are switch cpus */
hits[pkt->cmdToIndex()][id % _numCpus]++;