Update README.md

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/README.md b/README.md
index a39737c08c9ca914cf2c46e20e003a06409d1b7b..894b152ce4e360e70a60205279852fb2764d2393 100644 (file)
--- a/README.md
+++ b/README.md
@@ -333,7 +333,8 @@ Verilog Attributes and non-standard features
   is run in ``-pwires`` mode).
 
 - Wires marked with the ``hierconn`` attribute are connected to wires with the
-  same name when they are imported from sub-modules by ``flatten``.
+  same name (format ``cell_name.identifier``) when they are imported from
+  sub-modules by ``flatten``.
 
 - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
   module to mark it as a clock buffer output, and thus prevent ``clkbufmap``