{
RADV_FROM_HANDLE(radv_queue, queue, _queue);
- queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
+ queue->device->ws->ctx_wait_idle(queue->device->hw_ctx,
+ radv_queue_family_to_ring(queue->queue_family_index),
+ queue->queue_idx);
return VK_SUCCESS;
}
{
RADV_FROM_HANDLE(radv_device, device, _device);
- device->ws->ctx_wait_idle(device->hw_ctx);
+ for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
+ for (unsigned q = 0; q < device->queue_count[i]; q++) {
+ radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
+ }
+ }
return VK_SUCCESS;
}
struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
- bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx);
+ bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
+ enum ring_type ring_type, int ring_index);
struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
enum ring_type ring_type);
return r;
}
+static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
+ struct amdgpu_cs_request *request)
+{
+ radv_amdgpu_request_to_fence(ctx,
+ &ctx->last_submission[request->ip_type][request->ring],
+ request);
+}
+
static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
struct radeon_winsys_cs **cs_array,
unsigned cs_count,
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
- ctx->last_seq_no = request.seq_no;
+ radv_assign_last_submit(ctx, &request);
return r;
}
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
- ctx->last_seq_no = request.seq_no;
+ radv_assign_last_submit(ctx, &request);
return 0;
}
}
if (fence)
radv_amdgpu_request_to_fence(ctx, fence, &request);
- ctx->last_seq_no = request.seq_no;
+
+ radv_assign_last_submit(ctx, &request);
+
return 0;
}
FREE(ctx);
}
-static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx)
+static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
+ enum ring_type ring_type, int ring_index)
{
struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
+ int ip_type = ring_to_hw_ip(ring_type);
- if (ctx->last_seq_no) {
+ if (ctx->last_submission[ip_type][ring_index].fence) {
uint32_t expired;
- struct amdgpu_cs_fence fence;
-
- fence.context = ctx->ctx;
- fence.ip_type = AMDGPU_HW_IP_GFX;
- fence.ip_instance = 0;
- fence.ring = 0;
- fence.fence = ctx->last_seq_no;
-
- int ret = amdgpu_cs_query_fence_status(&fence, 1000000000ull, 0,
- &expired);
+ int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index],
+ 1000000000ull, 0, &expired);
if (ret || !expired)
return false;
ws->info.num_tile_pipes = radv_cik_get_num_tile_pipes(&ws->amdinfo);
ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
ws->info.has_virtual_memory = TRUE;
- ws->info.sdma_rings = util_bitcount(dma.available_rings);
- ws->info.compute_rings = util_bitcount(compute.available_rings);
+ ws->info.sdma_rings = MIN2(util_bitcount(dma.available_rings),
+ MAX_RINGS_PER_TYPE);
+ ws->info.compute_rings = MIN2(util_bitcount(compute.available_rings),
+ MAX_RINGS_PER_TYPE);
/* Get the number of good compute units. */
ws->info.num_good_compute_units = 0;