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Merge pull request #976 from YosysHQ/clifford/fix974
authorClifford Wolf <clifford@clifford.at>
Fri, 3 May 2019 13:29:44 +0000 (15:29 +0200)
committerGitHub <noreply@github.com>
Fri, 3 May 2019 13:29:44 +0000 (15:29 +0200)
Fix width detection of memory access with bit slice


Trivial merge