RTLIL::S{0,1} -> State::S{0,1} for headers

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index d2594bc46c1f79021be564f92d696c1a660ea3ab..7f1d355602ed87f4b6bfb4baccf99dd53f041b70 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -273,8 +273,8 @@ struct CellTypes
        static RTLIL::Const eval_not(RTLIL::Const v)
        {
                for (auto &bit : v.bits)
-                       if (bit == RTLIL::S0) bit = RTLIL::S1;
-                       else if (bit == RTLIL::S1) bit = RTLIL::S0;
+                       if (bit == State::S0) bit = State::S1;
+                       else if (bit == State::S1) bit = State::S0;
                return v;
        }
 
@@ -380,15 +380,15 @@ struct CellTypes
 
                        std::vector<RTLIL::State> t = cell->parameters.at("\\LUT").bits;
                        while (GetSize(t) < (1 << width))
-                               t.push_back(RTLIL::S0);
+                               t.push_back(State::S0);
                        t.resize(1 << width);
 
                        for (int i = width-1; i >= 0; i--) {
                                RTLIL::State sel = arg1.bits.at(i);
                                std::vector<RTLIL::State> new_t;
-                               if (sel == RTLIL::S0)
+                               if (sel == State::S0)
                                        new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
-                               else if (sel == RTLIL::S1)
+                               else if (sel == State::S1)
                                        new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
                                else
                                        for (int j = 0; j < GetSize(t)/2; j++)
@@ -407,7 +407,7 @@ struct CellTypes
                        std::vector<RTLIL::State> t = cell->parameters.at("\\TABLE").bits;
 
                        while (GetSize(t) < width*depth*2)
-                               t.push_back(RTLIL::S0);
+                               t.push_back(State::S0);
 
                        RTLIL::State default_ret = State::S0;
 

diff --git a/kernel/consteval.h b/kernel/consteval.h
index f70dfa0fbda03261b24d31518a7dbfaa04ac2ecf..521ce96d4b7845e09ad4d170f19cef899ae386c9 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -114,8 +114,8 @@ struct ConstEval
                                bool carry = sig_ci.as_bool();
 
                                for (int i = 0; i < GetSize(coval); i++) {
-                                       carry = (sig_g[i] == RTLIL::S1) || (sig_p[i] == RTLIL::S1 && carry);
-                                       coval.bits[i] = carry ? RTLIL::S1 : RTLIL::S0;
+                                       carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);
+                                       coval.bits[i] = carry ? State::S1 : State::S0;
                                }
 
                                set(sig_co, coval);
@@ -254,8 +254,8 @@ struct ConstEval
                        sig_a.extend_u0(GetSize(sig_y), signed_a);
                        sig_b.extend_u0(GetSize(sig_y), signed_b);
 
-                       bool carry = sig_ci[0] == RTLIL::S1;
-                       bool b_inv = sig_bi[0] == RTLIL::S1;
+                       bool carry = sig_ci[0] == State::S1;
+                       bool b_inv = sig_bi[0] == State::S1;
 
                        for (int i = 0; i < GetSize(sig_y); i++)
                        {
@@ -264,22 +264,22 @@ struct ConstEval
                                if (!x_inputs.is_fully_def()) {
                                        set(sig_x[i], RTLIL::Sx);
                                } else {
-                                       bool bit_a = sig_a[i] == RTLIL::S1;
-                                       bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv;
+                                       bool bit_a = sig_a[i] == State::S1;
+                                       bool bit_b = (sig_b[i] == State::S1) != b_inv;
                                        bool bit_x = bit_a != bit_b;
-                                       set(sig_x[i], bit_x ? RTLIL::S1 : RTLIL::S0);
+                                       set(sig_x[i], bit_x ? State::S1 : State::S0);
                                }
 
                                if (any_input_undef) {
                                        set(sig_y[i], RTLIL::Sx);
                                        set(sig_co[i], RTLIL::Sx);
                                } else {
-                                       bool bit_a = sig_a[i] == RTLIL::S1;
-                                       bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv;
+                                       bool bit_a = sig_a[i] == State::S1;
+                                       bool bit_b = (sig_b[i] == State::S1) != b_inv;
                                        bool bit_y = (bit_a != bit_b) != carry;
                                        carry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);
-                                       set(sig_y[i], bit_y ? RTLIL::S1 : RTLIL::S0);
-                                       set(sig_co[i], carry ? RTLIL::S1 : RTLIL::S0);
+                                       set(sig_y[i], bit_y ? State::S1 : State::S0);
+                                       set(sig_co[i], carry ? State::S1 : State::S0);
                                }
                        }
                }

diff --git a/kernel/macc.h b/kernel/macc.h
index 286ce567faa2297cf1b21c146527c276aac06f06..c7595ebc18fe9f5aea803b965598ce0f002bb328 100644 (file)
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -70,9 +70,9 @@ struct Macc
                                while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])
                                        port.in_b.remove(GetSize(port.in_b)-1);
                        } else {
-                               while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == RTLIL::S0)
+                               while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == State::S0)
                                        port.in_a.remove(GetSize(port.in_a)-1);
-                               while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == RTLIL::S0)
+                               while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == State::S0)
                                        port.in_b.remove(GetSize(port.in_b)-1);
                        }
 
@@ -80,9 +80,9 @@ struct Macc
                }
 
                for (auto &bit : bit_ports)
-                       if (bit == RTLIL::S1)
+                       if (bit == State::S1)
                                off = const_add(off, RTLIL::Const(1, width), false, false, width);
-                       else if (bit != RTLIL::S0)
+                       else if (bit != State::S0)
                                new_bit_ports.append(bit);
 
                if (off.as_bool()) {
@@ -113,10 +113,10 @@ struct Macc
 #endif
 
                int num_bits = 0;
-               if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 1;
-               if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 2;
-               if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 4;
-               if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 8;
+               if (config_bits[config_cursor++] == State::S1) num_bits |= 1;
+               if (config_bits[config_cursor++] == State::S1) num_bits |= 2;
+               if (config_bits[config_cursor++] == State::S1) num_bits |= 4;
+               if (config_bits[config_cursor++] == State::S1) num_bits |= 8;
 
                int port_a_cursor = 0;
                while (port_a_cursor < GetSize(port_a))
@@ -124,12 +124,12 @@ struct Macc
                        log_assert(config_cursor + 2 + 2*num_bits <= config_width);
 
                        port_t this_port;
-                       this_port.is_signed = config_bits[config_cursor++] == RTLIL::S1;
-                       this_port.do_subtract = config_bits[config_cursor++] == RTLIL::S1;
+                       this_port.is_signed = config_bits[config_cursor++] == State::S1;
+                       this_port.do_subtract = config_bits[config_cursor++] == State::S1;
 
                        int size_a = 0;
                        for (int i = 0; i < num_bits; i++)
-                               if (config_bits[config_cursor++] == RTLIL::S1)
+                               if (config_bits[config_cursor++] == State::S1)
                                        size_a |= 1 << i;
 
                        this_port.in_a = port_a.extract(port_a_cursor, size_a);
@@ -137,7 +137,7 @@ struct Macc
 
                        int size_b = 0;
                        for (int i = 0; i < num_bits; i++)
-                               if (config_bits[config_cursor++] == RTLIL::S1)
+                               if (config_bits[config_cursor++] == State::S1)
                                        size_b |= 1 << i;
 
                        this_port.in_b = port_a.extract(port_a_cursor, size_b);
@@ -166,26 +166,26 @@ struct Macc
                        num_bits++, max_size /= 2;
 
                log_assert(num_bits < 16);
-               config_bits.push_back(num_bits & 1 ? RTLIL::S1 : RTLIL::S0);
-               config_bits.push_back(num_bits & 2 ? RTLIL::S1 : RTLIL::S0);
-               config_bits.push_back(num_bits & 4 ? RTLIL::S1 : RTLIL::S0);
-               config_bits.push_back(num_bits & 8 ? RTLIL::S1 : RTLIL::S0);
+               config_bits.push_back(num_bits & 1 ? State::S1 : State::S0);
+               config_bits.push_back(num_bits & 2 ? State::S1 : State::S0);
+               config_bits.push_back(num_bits & 4 ? State::S1 : State::S0);
+               config_bits.push_back(num_bits & 8 ? State::S1 : State::S0);
 
                for (auto &port : ports)
                {
                        if (GetSize(port.in_a) == 0)
                                continue;
 
-                       config_bits.push_back(port.is_signed ? RTLIL::S1 : RTLIL::S0);
-                       config_bits.push_back(port.do_subtract ? RTLIL::S1 : RTLIL::S0);
+                       config_bits.push_back(port.is_signed ? State::S1 : State::S0);
+                       config_bits.push_back(port.do_subtract ? State::S1 : State::S0);
 
                        int size_a = GetSize(port.in_a);
                        for (int i = 0; i < num_bits; i++)
-                               config_bits.push_back(size_a & (1 << i) ? RTLIL::S1 : RTLIL::S0);
+                               config_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0);
 
                        int size_b = GetSize(port.in_b);
                        for (int i = 0; i < num_bits; i++)
-                               config_bits.push_back(size_b & (1 << i) ? RTLIL::S1 : RTLIL::S0);
+                               config_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0);
 
                        port_a.append(port.in_a);
                        port_a.append(port.in_b);
@@ -202,7 +202,7 @@ struct Macc
        bool eval(RTLIL::Const &result) const
        {
                for (auto &bit : result.bits)
-                       bit = RTLIL::S0;
+                       bit = State::S0;
 
                for (auto &port : ports)
                {

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 99c6839746e261e33e34a416bec39ce321c3c14a..37b5f984c0a781ed869496a948aa505a7f7e3347 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1408,7 +1408,7 @@ struct RTLIL::Process : public RTLIL::AttrObject
 
 inline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }
 inline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
-inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? RTLIL::S1 : RTLIL::S0) { }
+inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { }
 inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
 inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
 inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }

diff --git a/kernel/satgen.h b/kernel/satgen.h
index e9f3ecd440553cbd6c43c0861520dc80ee40e814..596f522ec208bfe53e10f496ac173831c5f472df 100644 (file)
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -1023,7 +1023,7 @@ struct SatGen
 
                        std::vector<int> lut;
                        for (auto bit : cell->getParam("\\LUT").bits)
-                               lut.push_back(bit == RTLIL::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
+                               lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
                        while (GetSize(lut) < (1 << GetSize(a)))
                                lut.push_back(ez->CONST_FALSE);
                        lut.resize(1 << GetSize(a));